ChenXuzheng/FPGA-TankGame-new
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

update to 2021/1/1 only last enermy control to fix

Browse Source
This commit is contained in:
ChenXuzheng
2021-01-01 20:59:42 +08:00
parent 861fb88001
commit 38350c37bb
42 changed files with 1781 additions and 1049 deletions
Download Patch File Download Diff File Expand all files Collapse all files
TankGame.srcs/sources_1/ip/bullet_down_img/bullet_down_img.xml
+128 -128
View File
@@ -1446,100 +1446,6 @@
</spirit:memoryMaps>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_veriloginstantiationtemplate</spirit:name>
<spirit:displayName>Verilog Instantiation Template</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.template</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:fileSetRef>
<spirit:localName>xilinx_veriloginstantiationtemplate_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 22 13:58:25 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:cc5e08b4</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 22 13:58:27 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d72f6b69</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>bullet_down_img</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 22 13:58:27 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d72f6b69</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_project_archive</spirit:name>
<spirit:displayName>Miscellaneous</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:misc.files</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_project_archive_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 22 13:58:27 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:cc5e08b4</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_versioninformation</spirit:name>
<spirit:displayName>Version Information</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:docs.versioninfo</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_versioninformation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 22 13:58:27 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:cc5e08b4</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
<spirit:displayName>VHDL Synthesis</spirit:displayName>
@@ -1552,11 +1458,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:26:41 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:39:54 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:c4d6b101</spirit:value>
<spirit:value>9:f04125b1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1567,7 +1473,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:c4d6b101</spirit:value>
<spirit:value>9:f04125b1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1583,11 +1489,105 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:26:41 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:39:54 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:c4d6b101</spirit:value>
<spirit:value>9:f04125b1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_veriloginstantiationtemplate</spirit:name>
<spirit:displayName>Verilog Instantiation Template</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.template</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:fileSetRef>
<spirit:localName>xilinx_veriloginstantiationtemplate_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Dec 30 13:18:06 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:f04125b1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Dec 30 13:18:06 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:93548381</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>bullet_down_img</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Dec 30 13:18:06 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:93548381</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_project_archive</spirit:name>
<spirit:displayName>Miscellaneous</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:misc.files</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_project_archive_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Dec 30 13:18:06 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:f04125b1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_versioninformation</spirit:name>
<spirit:displayName>Version Information</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:docs.versioninfo</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_versioninformation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Dec 30 13:18:06 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:f04125b1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1601,11 +1601,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:30:53 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 13:18:23 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:c4d6b101</spirit:value>
<spirit:value>9:f04125b1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -3535,6 +3535,33 @@
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>bullet_down_img_ooc.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>bullet_down_img.mif</spirit:name>
<spirit:userFileType>mif</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/bullet_down_img.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_veriloginstantiationtemplate_view_fileset</spirit:name>
<spirit:file>
@@ -3586,33 +3613,6 @@
<spirit:userFileType>text</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>bullet_down_img_ooc.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>bullet_down_img.mif</spirit:name>
<spirit:userFileType>mif</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/bullet_down_img.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
<spirit:file>
TankGame.srcs/sources_1/ip/bullet_down_img/bullet_down_img_sim_netlist.v
+3 -8
View File
@@ -3,8 +3,8 @@
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
// Date : Tue Dec 29 16:30:53 2020
// Host : cxz666 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/bullet_down_img/bullet_down_img_sim_netlist.v
// Command : write_verilog -force -mode funcsim -rename_top bullet_down_img -prefix
// bullet_down_img_ bullet_down_img_sim_netlist.v
// Design : bullet_down_img
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -191,7 +191,6 @@ module bullet_down_img
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module bullet_down_img_blk_mem_gen_generic_cstr
(douta,
clka,
@@ -214,7 +213,6 @@ module bullet_down_img_blk_mem_gen_generic_cstr
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bullet_down_img_blk_mem_gen_prim_width
(douta,
clka,
@@ -237,7 +235,6 @@ module bullet_down_img_blk_mem_gen_prim_width
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bullet_down_img_blk_mem_gen_prim_wrapper_init
(douta,
clka,
@@ -403,7 +400,6 @@ module bullet_down_img_blk_mem_gen_prim_wrapper_init
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module bullet_down_img_blk_mem_gen_top
(douta,
clka,
@@ -451,7 +447,7 @@ endmodule
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "50" *)
(* C_WRITE_DEPTH_B = "50" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
(* downgradeipidentifiedwarnings = "yes" *)
module bullet_down_img_blk_mem_gen_v8_4_4
(clka,
rsta,
@@ -655,7 +651,6 @@ module bullet_down_img_blk_mem_gen_v8_4_4
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
module bullet_down_img_blk_mem_gen_v8_4_4_synth
(douta,
clka,
TankGame.srcs/sources_1/ip/bullet_down_img/bullet_down_img_sim_netlist.vhdl
+2 -14
View File
@@ -3,8 +3,8 @@
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Tue Dec 29 16:30:53 2020
-- Host : cxz666 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/bullet_down_img/bullet_down_img_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top bullet_down_img -prefix
-- bullet_down_img_ bullet_down_img_sim_netlist.vhdl
-- Design : bullet_down_img
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -21,8 +21,6 @@ entity bullet_down_img_blk_mem_gen_prim_wrapper_init is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_down_img_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bullet_down_img_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bullet_down_img_blk_mem_gen_prim_wrapper_init is
@@ -219,8 +217,6 @@ entity bullet_down_img_blk_mem_gen_prim_width is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_down_img_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bullet_down_img_blk_mem_gen_prim_width;
architecture STRUCTURE of bullet_down_img_blk_mem_gen_prim_width is
@@ -244,8 +240,6 @@ entity bullet_down_img_blk_mem_gen_generic_cstr is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_down_img_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bullet_down_img_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bullet_down_img_blk_mem_gen_generic_cstr is
@@ -269,8 +263,6 @@ entity bullet_down_img_blk_mem_gen_top is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_down_img_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bullet_down_img_blk_mem_gen_top;
architecture STRUCTURE of bullet_down_img_blk_mem_gen_top is
@@ -294,8 +286,6 @@ entity bullet_down_img_blk_mem_gen_v8_4_4_synth is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_down_img_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
end bullet_down_img_blk_mem_gen_v8_4_4_synth;
architecture STRUCTURE of bullet_down_img_blk_mem_gen_v8_4_4_synth is
@@ -528,8 +518,6 @@ entity bullet_down_img_blk_mem_gen_v8_4_4 is
attribute C_WRITE_WIDTH_B of bullet_down_img_blk_mem_gen_v8_4_4 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bullet_down_img_blk_mem_gen_v8_4_4 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_down_img_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bullet_down_img_blk_mem_gen_v8_4_4 : entity is "yes";
end bullet_down_img_blk_mem_gen_v8_4_4;
TankGame.srcs/sources_1/ip/bullet_left_img/bullet_left_img.xml
+7 -7
View File
@@ -1552,11 +1552,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:26:41 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:39:54 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:105510ed</spirit:value>
<spirit:value>9:24c2845d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1567,7 +1567,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:105510ed</spirit:value>
<spirit:value>9:24c2845d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1583,11 +1583,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:26:41 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:39:54 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:105510ed</spirit:value>
<spirit:value>9:24c2845d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1601,11 +1601,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:30:54 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:40:32 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:105510ed</spirit:value>
<spirit:value>9:24c2845d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
TankGame.srcs/sources_1/ip/bullet_left_img/bullet_left_img_sim_netlist.v
+4 -9
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
// Date : Tue Dec 29 16:30:54 2020
// Date : Tue Dec 29 16:30:53 2020
// Host : cxz666 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/bullet_left_img/bullet_left_img_sim_netlist.v
// Command : write_verilog -force -mode funcsim -rename_top bullet_left_img -prefix
// bullet_left_img_ bullet_left_img_sim_netlist.v
// Design : bullet_left_img
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -191,7 +191,6 @@ module bullet_left_img
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module bullet_left_img_blk_mem_gen_generic_cstr
(douta,
clka,
@@ -214,7 +213,6 @@ module bullet_left_img_blk_mem_gen_generic_cstr
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bullet_left_img_blk_mem_gen_prim_width
(douta,
clka,
@@ -237,7 +235,6 @@ module bullet_left_img_blk_mem_gen_prim_width
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bullet_left_img_blk_mem_gen_prim_wrapper_init
(douta,
clka,
@@ -403,7 +400,6 @@ module bullet_left_img_blk_mem_gen_prim_wrapper_init
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module bullet_left_img_blk_mem_gen_top
(douta,
clka,
@@ -451,7 +447,7 @@ endmodule
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "50" *)
(* C_WRITE_DEPTH_B = "50" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
(* downgradeipidentifiedwarnings = "yes" *)
module bullet_left_img_blk_mem_gen_v8_4_4
(clka,
rsta,
@@ -655,7 +651,6 @@ module bullet_left_img_blk_mem_gen_v8_4_4
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
module bullet_left_img_blk_mem_gen_v8_4_4_synth
(douta,
clka,
TankGame.srcs/sources_1/ip/bullet_left_img/bullet_left_img_sim_netlist.vhdl
+3 -15
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Tue Dec 29 16:30:54 2020
-- Date : Tue Dec 29 16:30:53 2020
-- Host : cxz666 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/bullet_left_img/bullet_left_img_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top bullet_left_img -prefix
-- bullet_left_img_ bullet_left_img_sim_netlist.vhdl
-- Design : bullet_left_img
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -21,8 +21,6 @@ entity bullet_left_img_blk_mem_gen_prim_wrapper_init is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_left_img_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bullet_left_img_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bullet_left_img_blk_mem_gen_prim_wrapper_init is
@@ -219,8 +217,6 @@ entity bullet_left_img_blk_mem_gen_prim_width is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_left_img_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bullet_left_img_blk_mem_gen_prim_width;
architecture STRUCTURE of bullet_left_img_blk_mem_gen_prim_width is
@@ -244,8 +240,6 @@ entity bullet_left_img_blk_mem_gen_generic_cstr is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_left_img_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bullet_left_img_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bullet_left_img_blk_mem_gen_generic_cstr is
@@ -269,8 +263,6 @@ entity bullet_left_img_blk_mem_gen_top is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_left_img_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bullet_left_img_blk_mem_gen_top;
architecture STRUCTURE of bullet_left_img_blk_mem_gen_top is
@@ -294,8 +286,6 @@ entity bullet_left_img_blk_mem_gen_v8_4_4_synth is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_left_img_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
end bullet_left_img_blk_mem_gen_v8_4_4_synth;
architecture STRUCTURE of bullet_left_img_blk_mem_gen_v8_4_4_synth is
@@ -528,8 +518,6 @@ entity bullet_left_img_blk_mem_gen_v8_4_4 is
attribute C_WRITE_WIDTH_B of bullet_left_img_blk_mem_gen_v8_4_4 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bullet_left_img_blk_mem_gen_v8_4_4 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_left_img_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bullet_left_img_blk_mem_gen_v8_4_4 : entity is "yes";
end bullet_left_img_blk_mem_gen_v8_4_4;
TankGame.srcs/sources_1/ip/bullet_right_img/bullet_right_img.xml
+7 -7
View File
@@ -1552,11 +1552,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:26:42 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:39:54 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:b1718657</spirit:value>
<spirit:value>9:7a24a24f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1567,7 +1567,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:b1718657</spirit:value>
<spirit:value>9:7a24a24f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1583,11 +1583,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:26:42 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:39:54 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:b1718657</spirit:value>
<spirit:value>9:7a24a24f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1601,11 +1601,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:30:54 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:40:33 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:b1718657</spirit:value>
<spirit:value>9:7a24a24f</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
TankGame.srcs/sources_1/ip/bullet_right_img/bullet_right_img_sim_netlist.v
+4 -9
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
// Date : Tue Dec 29 16:30:54 2020
// Date : Tue Dec 29 16:30:53 2020
// Host : cxz666 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/bullet_right_img/bullet_right_img_sim_netlist.v
// Command : write_verilog -force -mode funcsim -rename_top bullet_right_img -prefix
// bullet_right_img_ bullet_right_img_sim_netlist.v
// Design : bullet_right_img
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -191,7 +191,6 @@ module bullet_right_img
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module bullet_right_img_blk_mem_gen_generic_cstr
(douta,
clka,
@@ -214,7 +213,6 @@ module bullet_right_img_blk_mem_gen_generic_cstr
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bullet_right_img_blk_mem_gen_prim_width
(douta,
clka,
@@ -237,7 +235,6 @@ module bullet_right_img_blk_mem_gen_prim_width
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bullet_right_img_blk_mem_gen_prim_wrapper_init
(douta,
clka,
@@ -403,7 +400,6 @@ module bullet_right_img_blk_mem_gen_prim_wrapper_init
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module bullet_right_img_blk_mem_gen_top
(douta,
clka,
@@ -451,7 +447,7 @@ endmodule
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "50" *)
(* C_WRITE_DEPTH_B = "50" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
(* downgradeipidentifiedwarnings = "yes" *)
module bullet_right_img_blk_mem_gen_v8_4_4
(clka,
rsta,
@@ -655,7 +651,6 @@ module bullet_right_img_blk_mem_gen_v8_4_4
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
module bullet_right_img_blk_mem_gen_v8_4_4_synth
(douta,
clka,
TankGame.srcs/sources_1/ip/bullet_right_img/bullet_right_img_sim_netlist.vhdl
+3 -15
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Tue Dec 29 16:30:54 2020
-- Date : Tue Dec 29 16:30:53 2020
-- Host : cxz666 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/bullet_right_img/bullet_right_img_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top bullet_right_img -prefix
-- bullet_right_img_ bullet_right_img_sim_netlist.vhdl
-- Design : bullet_right_img
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -21,8 +21,6 @@ entity bullet_right_img_blk_mem_gen_prim_wrapper_init is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_right_img_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bullet_right_img_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bullet_right_img_blk_mem_gen_prim_wrapper_init is
@@ -219,8 +217,6 @@ entity bullet_right_img_blk_mem_gen_prim_width is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_right_img_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bullet_right_img_blk_mem_gen_prim_width;
architecture STRUCTURE of bullet_right_img_blk_mem_gen_prim_width is
@@ -244,8 +240,6 @@ entity bullet_right_img_blk_mem_gen_generic_cstr is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_right_img_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bullet_right_img_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bullet_right_img_blk_mem_gen_generic_cstr is
@@ -269,8 +263,6 @@ entity bullet_right_img_blk_mem_gen_top is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_right_img_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bullet_right_img_blk_mem_gen_top;
architecture STRUCTURE of bullet_right_img_blk_mem_gen_top is
@@ -294,8 +286,6 @@ entity bullet_right_img_blk_mem_gen_v8_4_4_synth is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_right_img_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
end bullet_right_img_blk_mem_gen_v8_4_4_synth;
architecture STRUCTURE of bullet_right_img_blk_mem_gen_v8_4_4_synth is
@@ -528,8 +518,6 @@ entity bullet_right_img_blk_mem_gen_v8_4_4 is
attribute C_WRITE_WIDTH_B of bullet_right_img_blk_mem_gen_v8_4_4 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bullet_right_img_blk_mem_gen_v8_4_4 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_right_img_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bullet_right_img_blk_mem_gen_v8_4_4 : entity is "yes";
end bullet_right_img_blk_mem_gen_v8_4_4;
TankGame.srcs/sources_1/ip/bullet_up_img/bullet_up_img.xml
+7 -7
View File
@@ -1552,11 +1552,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:26:40 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:39:53 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:85938ef0</spirit:value>
<spirit:value>9:7100886c</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1567,7 +1567,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:85938ef0</spirit:value>
<spirit:value>9:7100886c</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1583,11 +1583,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:26:40 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:39:53 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:85938ef0</spirit:value>
<spirit:value>9:7100886c</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1601,11 +1601,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:30:53 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:40:32 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:85938ef0</spirit:value>
<spirit:value>9:7100886c</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
TankGame.srcs/sources_1/ip/bullet_up_img/bullet_up_img_sim_netlist.v
+4 -9
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
// Date : Tue Dec 29 16:30:53 2020
// Date : Tue Dec 29 16:30:52 2020
// Host : cxz666 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/bullet_up_img/bullet_up_img_sim_netlist.v
// Command : write_verilog -force -mode funcsim -rename_top bullet_up_img -prefix
// bullet_up_img_ bullet_up_img_sim_netlist.v
// Design : bullet_up_img
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -191,7 +191,6 @@ module bullet_up_img
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module bullet_up_img_blk_mem_gen_generic_cstr
(douta,
clka,
@@ -214,7 +213,6 @@ module bullet_up_img_blk_mem_gen_generic_cstr
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bullet_up_img_blk_mem_gen_prim_width
(douta,
clka,
@@ -237,7 +235,6 @@ module bullet_up_img_blk_mem_gen_prim_width
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bullet_up_img_blk_mem_gen_prim_wrapper_init
(douta,
clka,
@@ -403,7 +400,6 @@ module bullet_up_img_blk_mem_gen_prim_wrapper_init
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module bullet_up_img_blk_mem_gen_top
(douta,
clka,
@@ -451,7 +447,7 @@ endmodule
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "50" *)
(* C_WRITE_DEPTH_B = "50" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
(* downgradeipidentifiedwarnings = "yes" *)
module bullet_up_img_blk_mem_gen_v8_4_4
(clka,
rsta,
@@ -655,7 +651,6 @@ module bullet_up_img_blk_mem_gen_v8_4_4
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
module bullet_up_img_blk_mem_gen_v8_4_4_synth
(douta,
clka,
TankGame.srcs/sources_1/ip/bullet_up_img/bullet_up_img_sim_netlist.vhdl
+3 -15
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Tue Dec 29 16:30:53 2020
-- Date : Tue Dec 29 16:30:52 2020
-- Host : cxz666 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/bullet_up_img/bullet_up_img_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top bullet_up_img -prefix
-- bullet_up_img_ bullet_up_img_sim_netlist.vhdl
-- Design : bullet_up_img
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -21,8 +21,6 @@ entity bullet_up_img_blk_mem_gen_prim_wrapper_init is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_up_img_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bullet_up_img_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bullet_up_img_blk_mem_gen_prim_wrapper_init is
@@ -219,8 +217,6 @@ entity bullet_up_img_blk_mem_gen_prim_width is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_up_img_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bullet_up_img_blk_mem_gen_prim_width;
architecture STRUCTURE of bullet_up_img_blk_mem_gen_prim_width is
@@ -244,8 +240,6 @@ entity bullet_up_img_blk_mem_gen_generic_cstr is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_up_img_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bullet_up_img_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bullet_up_img_blk_mem_gen_generic_cstr is
@@ -269,8 +263,6 @@ entity bullet_up_img_blk_mem_gen_top is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_up_img_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bullet_up_img_blk_mem_gen_top;
architecture STRUCTURE of bullet_up_img_blk_mem_gen_top is
@@ -294,8 +286,6 @@ entity bullet_up_img_blk_mem_gen_v8_4_4_synth is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_up_img_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
end bullet_up_img_blk_mem_gen_v8_4_4_synth;
architecture STRUCTURE of bullet_up_img_blk_mem_gen_v8_4_4_synth is
@@ -528,8 +518,6 @@ entity bullet_up_img_blk_mem_gen_v8_4_4 is
attribute C_WRITE_WIDTH_B of bullet_up_img_blk_mem_gen_v8_4_4 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bullet_up_img_blk_mem_gen_v8_4_4 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_up_img_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bullet_up_img_blk_mem_gen_v8_4_4 : entity is "yes";
end bullet_up_img_blk_mem_gen_v8_4_4;
TankGame.srcs/sources_1/ip/gameover_380_180/gameover_380_180.xml
+80 -80
View File
@@ -1465,57 +1465,6 @@
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
<spirit:displayName>VHDL Synthesis</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 12:18:03 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a566edfa</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_synthesisconstraints</spirit:name>
<spirit:displayName>Synthesis Constraints</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a566edfa</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>gameover_380_180</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 12:18:03 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a566edfa</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
@@ -1591,6 +1540,57 @@
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
<spirit:displayName>VHDL Synthesis</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Dec 30 00:40:02 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:c54f3c26</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_synthesisconstraints</spirit:name>
<spirit:displayName>Synthesis Constraints</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:c54f3c26</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>gameover_380_180</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Dec 30 00:40:02 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:c54f3c26</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_externalfiles</spirit:name>
<spirit:displayName>External Files</spirit:displayName>
@@ -1601,11 +1601,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 12:20:02 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:40:43 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a566edfa</spirit:value>
<spirit:value>9:c54f3c26</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -3549,33 +3549,6 @@
<spirit:userFileType>verilogTemplate</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>gameover_380_180_ooc.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>gameover_380_180.mif</spirit:name>
<spirit:userFileType>mif</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/gameover_380_180.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
@@ -3616,6 +3589,33 @@
<spirit:userFileType>text</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>gameover_380_180_ooc.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>gameover_380_180.mif</spirit:name>
<spirit:userFileType>mif</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/gameover_380_180.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
<spirit:file>
TankGame.srcs/sources_1/ip/gameover_380_180/gameover_380_180_sim_netlist.v
+4 -11
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
// Date : Tue Dec 29 20:20:02 2020
// Date : Tue Dec 29 20:20:01 2020
// Host : cxz666 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// e:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/gameover_380_180/gameover_380_180_sim_netlist.v
// Command : write_verilog -force -mode funcsim -rename_top gameover_380_180 -prefix
// gameover_380_180_ gameover_380_180_sim_netlist.v
// Design : gameover_380_180
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -191,7 +191,6 @@ module gameover_380_180
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "bindec" *)
module gameover_380_180_bindec
(ena_array,
addra,
@@ -376,7 +375,6 @@ module gameover_380_180_bindec
.O(ena_array[10]));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module gameover_380_180_blk_mem_gen_generic_cstr
(douta,
clka,
@@ -766,7 +764,6 @@ module gameover_380_180_blk_mem_gen_generic_cstr
.ena_array(ena_array[4]));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_mux" *)
module gameover_380_180_blk_mem_gen_mux
(douta,
DOADO,
@@ -1687,7 +1684,6 @@ module gameover_380_180_blk_mem_gen_mux
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module gameover_380_180_blk_mem_gen_prim_width
(DOUTA,
clka,
@@ -2345,7 +2341,6 @@ module gameover_380_180_blk_mem_gen_prim_width__parameterized9
.ena_array(ena_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module gameover_380_180_blk_mem_gen_prim_wrapper_init
(DOUTA,
clka,
@@ -8181,7 +8176,6 @@ module gameover_380_180_blk_mem_gen_prim_wrapper_init__parameterized9
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module gameover_380_180_blk_mem_gen_top
(douta,
clka,
@@ -8229,7 +8223,7 @@ endmodule
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "68400" *)
(* C_WRITE_DEPTH_B = "68400" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
(* downgradeipidentifiedwarnings = "yes" *)
module gameover_380_180_blk_mem_gen_v8_4_4
(clka,
rsta,
@@ -8455,7 +8449,6 @@ module gameover_380_180_blk_mem_gen_v8_4_4
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
module gameover_380_180_blk_mem_gen_v8_4_4_synth
(douta,
clka,
TankGame.srcs/sources_1/ip/gameover_380_180/gameover_380_180_sim_netlist.vhdl
+3 -19
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Tue Dec 29 20:20:02 2020
-- Date : Tue Dec 29 20:20:01 2020
-- Host : cxz666 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- e:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/gameover_380_180/gameover_380_180_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top gameover_380_180 -prefix
-- gameover_380_180_ gameover_380_180_sim_netlist.vhdl
-- Design : gameover_380_180
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -20,8 +20,6 @@ entity gameover_380_180_bindec is
addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gameover_380_180_bindec : entity is "bindec";
end gameover_380_180_bindec;
architecture STRUCTURE of gameover_380_180_bindec is
@@ -298,8 +296,6 @@ entity gameover_380_180_blk_mem_gen_mux is
\douta[11]_INST_0_i_2_6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\douta[11]_INST_0_i_2_7\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end gameover_380_180_blk_mem_gen_mux;
architecture STRUCTURE of gameover_380_180_blk_mem_gen_mux is
@@ -1340,8 +1336,6 @@ entity gameover_380_180_blk_mem_gen_prim_wrapper_init is
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end gameover_380_180_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of gameover_380_180_blk_mem_gen_prim_wrapper_init is
@@ -7274,8 +7268,6 @@ entity gameover_380_180_blk_mem_gen_prim_width is
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end gameover_380_180_blk_mem_gen_prim_width;
architecture STRUCTURE of gameover_380_180_blk_mem_gen_prim_width is
@@ -7899,8 +7891,6 @@ entity gameover_380_180_blk_mem_gen_generic_cstr is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end gameover_380_180_blk_mem_gen_generic_cstr;
architecture STRUCTURE of gameover_380_180_blk_mem_gen_generic_cstr is
@@ -8583,8 +8573,6 @@ entity gameover_380_180_blk_mem_gen_top is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_top : entity is "blk_mem_gen_top";
end gameover_380_180_blk_mem_gen_top;
architecture STRUCTURE of gameover_380_180_blk_mem_gen_top is
@@ -8608,8 +8596,6 @@ entity gameover_380_180_blk_mem_gen_v8_4_4_synth is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
end gameover_380_180_blk_mem_gen_v8_4_4_synth;
architecture STRUCTURE of gameover_380_180_blk_mem_gen_v8_4_4_synth is
@@ -8842,8 +8828,6 @@ entity gameover_380_180_blk_mem_gen_v8_4_4 is
attribute C_WRITE_WIDTH_B of gameover_380_180_blk_mem_gen_v8_4_4 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of gameover_380_180_blk_mem_gen_v8_4_4 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of gameover_380_180_blk_mem_gen_v8_4_4 : entity is "yes";
end gameover_380_180_blk_mem_gen_v8_4_4;
TankGame.srcs/sources_1/ip/startpic_450_200/startpic_450_200.xml
+80 -80
View File
@@ -1465,57 +1465,6 @@
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
<spirit:displayName>VHDL Synthesis</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 12:29:56 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:ba70ca63</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_synthesisconstraints</spirit:name>
<spirit:displayName>Synthesis Constraints</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:ba70ca63</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>startpic_450_200</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 12:29:56 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:ba70ca63</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
@@ -1591,6 +1540,57 @@
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
<spirit:displayName>VHDL Synthesis</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Dec 30 00:40:12 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:17e55f2b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_synthesisconstraints</spirit:name>
<spirit:displayName>Synthesis Constraints</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:17e55f2b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>startpic_450_200</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Dec 30 00:40:12 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:17e55f2b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_externalfiles</spirit:name>
<spirit:displayName>External Files</spirit:displayName>
@@ -1601,11 +1601,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 12:32:03 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:40:43 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:ba70ca63</spirit:value>
<spirit:value>9:17e55f2b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -3549,33 +3549,6 @@
<spirit:userFileType>verilogTemplate</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>startpic_450_200_ooc.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>startpic_450_200.mif</spirit:name>
<spirit:userFileType>mif</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/startpic_450_200.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
@@ -3616,6 +3589,33 @@
<spirit:userFileType>text</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>startpic_450_200_ooc.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>startpic_450_200.mif</spirit:name>
<spirit:userFileType>mif</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/startpic_450_200.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
<spirit:file>
TankGame.srcs/sources_1/ip/startpic_450_200/startpic_450_200_sim_netlist.v
+4 -11
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
// Date : Tue Dec 29 20:32:03 2020
// Date : Tue Dec 29 20:32:02 2020
// Host : cxz666 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// e:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/startpic_450_200/startpic_450_200_sim_netlist.v
// Command : write_verilog -force -mode funcsim -rename_top startpic_450_200 -prefix
// startpic_450_200_ startpic_450_200_sim_netlist.v
// Design : startpic_450_200
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -191,7 +191,6 @@ module startpic_450_200
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "bindec" *)
module startpic_450_200_bindec
(ena_array,
addra,
@@ -416,7 +415,6 @@ module startpic_450_200_bindec
.O(ena_array[10]));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module startpic_450_200_blk_mem_gen_generic_cstr
(douta,
clka,
@@ -911,7 +909,6 @@ module startpic_450_200_blk_mem_gen_generic_cstr
.ena_array(ena_array[2]));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_mux" *)
module startpic_450_200_blk_mem_gen_mux
(douta,
DOADO,
@@ -2027,7 +2024,6 @@ module startpic_450_200_blk_mem_gen_mux
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module startpic_450_200_blk_mem_gen_prim_width
(DOUTA,
clka,
@@ -2891,7 +2887,6 @@ module startpic_450_200_blk_mem_gen_prim_width__parameterized9
.ena_array(ena_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module startpic_450_200_blk_mem_gen_prim_wrapper_init
(DOUTA,
clka,
@@ -10354,7 +10349,6 @@ module startpic_450_200_blk_mem_gen_prim_wrapper_init__parameterized9
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module startpic_450_200_blk_mem_gen_top
(douta,
clka,
@@ -10402,7 +10396,7 @@ endmodule
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "90000" *)
(* C_WRITE_DEPTH_B = "90000" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
(* downgradeipidentifiedwarnings = "yes" *)
module startpic_450_200_blk_mem_gen_v8_4_4
(clka,
rsta,
@@ -10628,7 +10622,6 @@ module startpic_450_200_blk_mem_gen_v8_4_4
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
module startpic_450_200_blk_mem_gen_v8_4_4_synth
(douta,
clka,
TankGame.srcs/sources_1/ip/startpic_450_200/startpic_450_200_sim_netlist.vhdl
+3 -19
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Tue Dec 29 20:32:03 2020
-- Date : Tue Dec 29 20:32:02 2020
-- Host : cxz666 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- e:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/startpic_450_200/startpic_450_200_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top startpic_450_200 -prefix
-- startpic_450_200_ startpic_450_200_sim_netlist.vhdl
-- Design : startpic_450_200
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -20,8 +20,6 @@ entity startpic_450_200_bindec is
addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of startpic_450_200_bindec : entity is "bindec";
end startpic_450_200_bindec;
architecture STRUCTURE of startpic_450_200_bindec is
@@ -362,8 +360,6 @@ entity startpic_450_200_blk_mem_gen_mux is
\douta[11]_INST_0_i_1_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\douta[11]_INST_0_i_1_4\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end startpic_450_200_blk_mem_gen_mux;
architecture STRUCTURE of startpic_450_200_blk_mem_gen_mux is
@@ -1615,8 +1611,6 @@ entity startpic_450_200_blk_mem_gen_prim_wrapper_init is
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end startpic_450_200_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of startpic_450_200_blk_mem_gen_prim_wrapper_init is
@@ -9212,8 +9206,6 @@ entity startpic_450_200_blk_mem_gen_prim_width is
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end startpic_450_200_blk_mem_gen_prim_width;
architecture STRUCTURE of startpic_450_200_blk_mem_gen_prim_width is
@@ -10036,8 +10028,6 @@ entity startpic_450_200_blk_mem_gen_generic_cstr is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end startpic_450_200_blk_mem_gen_generic_cstr;
architecture STRUCTURE of startpic_450_200_blk_mem_gen_generic_cstr is
@@ -10910,8 +10900,6 @@ entity startpic_450_200_blk_mem_gen_top is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_top : entity is "blk_mem_gen_top";
end startpic_450_200_blk_mem_gen_top;
architecture STRUCTURE of startpic_450_200_blk_mem_gen_top is
@@ -10935,8 +10923,6 @@ entity startpic_450_200_blk_mem_gen_v8_4_4_synth is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
end startpic_450_200_blk_mem_gen_v8_4_4_synth;
architecture STRUCTURE of startpic_450_200_blk_mem_gen_v8_4_4_synth is
@@ -11169,8 +11155,6 @@ entity startpic_450_200_blk_mem_gen_v8_4_4 is
attribute C_WRITE_WIDTH_B of startpic_450_200_blk_mem_gen_v8_4_4 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of startpic_450_200_blk_mem_gen_v8_4_4 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of startpic_450_200_blk_mem_gen_v8_4_4 : entity is "yes";
end startpic_450_200_blk_mem_gen_v8_4_4;
TankGame.srcs/sources_1/ip/tank_down_img/tank_down_img.xml
+7 -7
View File
@@ -1552,11 +1552,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:26:40 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:39:53 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d4e82092</spirit:value>
<spirit:value>9:e07fb422</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1567,7 +1567,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d4e82092</spirit:value>
<spirit:value>9:e07fb422</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1583,11 +1583,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:26:40 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:39:53 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d4e82092</spirit:value>
<spirit:value>9:e07fb422</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1601,11 +1601,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:28:49 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:40:32 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d4e82092</spirit:value>
<spirit:value>9:e07fb422</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
TankGame.srcs/sources_1/ip/tank_down_img/tank_down_img_sim_netlist.v
+4 -9
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
// Date : Tue Dec 29 16:28:49 2020
// Date : Tue Dec 29 16:28:48 2020
// Host : cxz666 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/tank_down_img/tank_down_img_sim_netlist.v
// Command : write_verilog -force -mode funcsim -rename_top tank_down_img -prefix
// tank_down_img_ tank_down_img_sim_netlist.v
// Design : tank_down_img
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -191,7 +191,6 @@ module tank_down_img
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module tank_down_img_blk_mem_gen_generic_cstr
(douta,
clka,
@@ -214,7 +213,6 @@ module tank_down_img_blk_mem_gen_generic_cstr
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module tank_down_img_blk_mem_gen_prim_width
(douta,
clka,
@@ -237,7 +235,6 @@ module tank_down_img_blk_mem_gen_prim_width
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module tank_down_img_blk_mem_gen_prim_wrapper_init
(douta,
clka,
@@ -387,7 +384,6 @@ module tank_down_img_blk_mem_gen_prim_wrapper_init
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module tank_down_img_blk_mem_gen_top
(douta,
clka,
@@ -435,7 +431,7 @@ endmodule
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "1024" *)
(* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
(* downgradeipidentifiedwarnings = "yes" *)
module tank_down_img_blk_mem_gen_v8_4_4
(clka,
rsta,
@@ -647,7 +643,6 @@ module tank_down_img_blk_mem_gen_v8_4_4
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
module tank_down_img_blk_mem_gen_v8_4_4_synth
(douta,
clka,
TankGame.srcs/sources_1/ip/tank_down_img/tank_down_img_sim_netlist.vhdl
+3 -15
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Tue Dec 29 16:28:49 2020
-- Date : Tue Dec 29 16:28:48 2020
-- Host : cxz666 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/tank_down_img/tank_down_img_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top tank_down_img -prefix
-- tank_down_img_ tank_down_img_sim_netlist.vhdl
-- Design : tank_down_img
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -21,8 +21,6 @@ entity tank_down_img_blk_mem_gen_prim_wrapper_init is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_down_img_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end tank_down_img_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of tank_down_img_blk_mem_gen_prim_wrapper_init is
@@ -182,8 +180,6 @@ entity tank_down_img_blk_mem_gen_prim_width is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_down_img_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end tank_down_img_blk_mem_gen_prim_width;
architecture STRUCTURE of tank_down_img_blk_mem_gen_prim_width is
@@ -207,8 +203,6 @@ entity tank_down_img_blk_mem_gen_generic_cstr is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_down_img_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end tank_down_img_blk_mem_gen_generic_cstr;
architecture STRUCTURE of tank_down_img_blk_mem_gen_generic_cstr is
@@ -232,8 +226,6 @@ entity tank_down_img_blk_mem_gen_top is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_down_img_blk_mem_gen_top : entity is "blk_mem_gen_top";
end tank_down_img_blk_mem_gen_top;
architecture STRUCTURE of tank_down_img_blk_mem_gen_top is
@@ -257,8 +249,6 @@ entity tank_down_img_blk_mem_gen_v8_4_4_synth is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_down_img_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
end tank_down_img_blk_mem_gen_v8_4_4_synth;
architecture STRUCTURE of tank_down_img_blk_mem_gen_v8_4_4_synth is
@@ -491,8 +481,6 @@ entity tank_down_img_blk_mem_gen_v8_4_4 is
attribute C_WRITE_WIDTH_B of tank_down_img_blk_mem_gen_v8_4_4 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of tank_down_img_blk_mem_gen_v8_4_4 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_down_img_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of tank_down_img_blk_mem_gen_v8_4_4 : entity is "yes";
end tank_down_img_blk_mem_gen_v8_4_4;
TankGame.srcs/sources_1/ip/tank_left_img/tank_left_img.xml
+7 -7
View File
@@ -1552,11 +1552,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:26:36 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:39:50 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:7b15ce1f</spirit:value>
<spirit:value>9:4f825aaf</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1567,7 +1567,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:7b15ce1f</spirit:value>
<spirit:value>9:4f825aaf</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1583,11 +1583,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:26:36 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:39:50 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:7b15ce1f</spirit:value>
<spirit:value>9:4f825aaf</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1601,11 +1601,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:28:49 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:40:33 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:7b15ce1f</spirit:value>
<spirit:value>9:4f825aaf</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
TankGame.srcs/sources_1/ip/tank_left_img/tank_left_img_sim_netlist.v
+3 -8
View File
@@ -3,8 +3,8 @@
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
// Date : Tue Dec 29 16:28:49 2020
// Host : cxz666 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/tank_left_img/tank_left_img_sim_netlist.v
// Command : write_verilog -force -mode funcsim -rename_top tank_left_img -prefix
// tank_left_img_ tank_left_img_sim_netlist.v
// Design : tank_left_img
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -191,7 +191,6 @@ module tank_left_img
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module tank_left_img_blk_mem_gen_generic_cstr
(douta,
clka,
@@ -214,7 +213,6 @@ module tank_left_img_blk_mem_gen_generic_cstr
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module tank_left_img_blk_mem_gen_prim_width
(douta,
clka,
@@ -237,7 +235,6 @@ module tank_left_img_blk_mem_gen_prim_width
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module tank_left_img_blk_mem_gen_prim_wrapper_init
(douta,
clka,
@@ -387,7 +384,6 @@ module tank_left_img_blk_mem_gen_prim_wrapper_init
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module tank_left_img_blk_mem_gen_top
(douta,
clka,
@@ -435,7 +431,7 @@ endmodule
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "1024" *)
(* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
(* downgradeipidentifiedwarnings = "yes" *)
module tank_left_img_blk_mem_gen_v8_4_4
(clka,
rsta,
@@ -647,7 +643,6 @@ module tank_left_img_blk_mem_gen_v8_4_4
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
module tank_left_img_blk_mem_gen_v8_4_4_synth
(douta,
clka,
TankGame.srcs/sources_1/ip/tank_left_img/tank_left_img_sim_netlist.vhdl
+2 -14
View File
@@ -3,8 +3,8 @@
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Tue Dec 29 16:28:49 2020
-- Host : cxz666 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/tank_left_img/tank_left_img_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top tank_left_img -prefix
-- tank_left_img_ tank_left_img_sim_netlist.vhdl
-- Design : tank_left_img
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -21,8 +21,6 @@ entity tank_left_img_blk_mem_gen_prim_wrapper_init is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_left_img_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end tank_left_img_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of tank_left_img_blk_mem_gen_prim_wrapper_init is
@@ -182,8 +180,6 @@ entity tank_left_img_blk_mem_gen_prim_width is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_left_img_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end tank_left_img_blk_mem_gen_prim_width;
architecture STRUCTURE of tank_left_img_blk_mem_gen_prim_width is
@@ -207,8 +203,6 @@ entity tank_left_img_blk_mem_gen_generic_cstr is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_left_img_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end tank_left_img_blk_mem_gen_generic_cstr;
architecture STRUCTURE of tank_left_img_blk_mem_gen_generic_cstr is
@@ -232,8 +226,6 @@ entity tank_left_img_blk_mem_gen_top is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_left_img_blk_mem_gen_top : entity is "blk_mem_gen_top";
end tank_left_img_blk_mem_gen_top;
architecture STRUCTURE of tank_left_img_blk_mem_gen_top is
@@ -257,8 +249,6 @@ entity tank_left_img_blk_mem_gen_v8_4_4_synth is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_left_img_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
end tank_left_img_blk_mem_gen_v8_4_4_synth;
architecture STRUCTURE of tank_left_img_blk_mem_gen_v8_4_4_synth is
@@ -491,8 +481,6 @@ entity tank_left_img_blk_mem_gen_v8_4_4 is
attribute C_WRITE_WIDTH_B of tank_left_img_blk_mem_gen_v8_4_4 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of tank_left_img_blk_mem_gen_v8_4_4 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_left_img_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of tank_left_img_blk_mem_gen_v8_4_4 : entity is "yes";
end tank_left_img_blk_mem_gen_v8_4_4;
TankGame.srcs/sources_1/ip/tank_right_img/tank_right_img.xml
+7 -7
View File
@@ -1552,11 +1552,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:26:37 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:39:51 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:bae1e80d</spirit:value>
<spirit:value>9:71b4cc15</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1567,7 +1567,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:bae1e80d</spirit:value>
<spirit:value>9:71b4cc15</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1583,11 +1583,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:26:37 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:39:51 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:bae1e80d</spirit:value>
<spirit:value>9:71b4cc15</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1601,11 +1601,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:28:49 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:40:32 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:bae1e80d</spirit:value>
<spirit:value>9:71b4cc15</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
TankGame.srcs/sources_1/ip/tank_right_img/tank_right_img_sim_netlist.v
+3 -8
View File
@@ -3,8 +3,8 @@
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
// Date : Tue Dec 29 16:28:49 2020
// Host : cxz666 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/tank_right_img/tank_right_img_sim_netlist.v
// Command : write_verilog -force -mode funcsim -rename_top tank_right_img -prefix
// tank_right_img_ tank_right_img_sim_netlist.v
// Design : tank_right_img
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -191,7 +191,6 @@ module tank_right_img
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module tank_right_img_blk_mem_gen_generic_cstr
(douta,
clka,
@@ -214,7 +213,6 @@ module tank_right_img_blk_mem_gen_generic_cstr
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module tank_right_img_blk_mem_gen_prim_width
(douta,
clka,
@@ -237,7 +235,6 @@ module tank_right_img_blk_mem_gen_prim_width
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module tank_right_img_blk_mem_gen_prim_wrapper_init
(douta,
clka,
@@ -387,7 +384,6 @@ module tank_right_img_blk_mem_gen_prim_wrapper_init
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module tank_right_img_blk_mem_gen_top
(douta,
clka,
@@ -435,7 +431,7 @@ endmodule
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "1024" *)
(* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
(* downgradeipidentifiedwarnings = "yes" *)
module tank_right_img_blk_mem_gen_v8_4_4
(clka,
rsta,
@@ -647,7 +643,6 @@ module tank_right_img_blk_mem_gen_v8_4_4
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
module tank_right_img_blk_mem_gen_v8_4_4_synth
(douta,
clka,
TankGame.srcs/sources_1/ip/tank_right_img/tank_right_img_sim_netlist.vhdl
+2 -14
View File
@@ -3,8 +3,8 @@
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Tue Dec 29 16:28:49 2020
-- Host : cxz666 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/tank_right_img/tank_right_img_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top tank_right_img -prefix
-- tank_right_img_ tank_right_img_sim_netlist.vhdl
-- Design : tank_right_img
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -21,8 +21,6 @@ entity tank_right_img_blk_mem_gen_prim_wrapper_init is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_right_img_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end tank_right_img_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of tank_right_img_blk_mem_gen_prim_wrapper_init is
@@ -182,8 +180,6 @@ entity tank_right_img_blk_mem_gen_prim_width is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_right_img_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end tank_right_img_blk_mem_gen_prim_width;
architecture STRUCTURE of tank_right_img_blk_mem_gen_prim_width is
@@ -207,8 +203,6 @@ entity tank_right_img_blk_mem_gen_generic_cstr is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_right_img_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end tank_right_img_blk_mem_gen_generic_cstr;
architecture STRUCTURE of tank_right_img_blk_mem_gen_generic_cstr is
@@ -232,8 +226,6 @@ entity tank_right_img_blk_mem_gen_top is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_right_img_blk_mem_gen_top : entity is "blk_mem_gen_top";
end tank_right_img_blk_mem_gen_top;
architecture STRUCTURE of tank_right_img_blk_mem_gen_top is
@@ -257,8 +249,6 @@ entity tank_right_img_blk_mem_gen_v8_4_4_synth is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_right_img_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
end tank_right_img_blk_mem_gen_v8_4_4_synth;
architecture STRUCTURE of tank_right_img_blk_mem_gen_v8_4_4_synth is
@@ -491,8 +481,6 @@ entity tank_right_img_blk_mem_gen_v8_4_4 is
attribute C_WRITE_WIDTH_B of tank_right_img_blk_mem_gen_v8_4_4 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of tank_right_img_blk_mem_gen_v8_4_4 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_right_img_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of tank_right_img_blk_mem_gen_v8_4_4 : entity is "yes";
end tank_right_img_blk_mem_gen_v8_4_4;
TankGame.srcs/sources_1/ip/tank_up_img/tank_up_img.xml
+7 -7
View File
@@ -1552,11 +1552,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:26:39 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:39:52 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a68d50f1</spirit:value>
<spirit:value>9:521e566d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1567,7 +1567,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a68d50f1</spirit:value>
<spirit:value>9:521e566d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1583,11 +1583,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:26:39 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:39:52 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a68d50f1</spirit:value>
<spirit:value>9:521e566d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1601,11 +1601,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:28:51 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:40:33 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a68d50f1</spirit:value>
<spirit:value>9:521e566d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
TankGame.srcs/sources_1/ip/tank_up_img/tank_up_img_sim_netlist.v
+4 -9
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
// Date : Tue Dec 29 16:28:51 2020
// Date : Tue Dec 29 16:28:50 2020
// Host : cxz666 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/tank_up_img/tank_up_img_sim_netlist.v
// Command : write_verilog -force -mode funcsim -rename_top tank_up_img -prefix
// tank_up_img_ tank_up_img_sim_netlist.v
// Design : tank_up_img
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -191,7 +191,6 @@ module tank_up_img
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module tank_up_img_blk_mem_gen_generic_cstr
(douta,
clka,
@@ -214,7 +213,6 @@ module tank_up_img_blk_mem_gen_generic_cstr
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module tank_up_img_blk_mem_gen_prim_width
(douta,
clka,
@@ -237,7 +235,6 @@ module tank_up_img_blk_mem_gen_prim_width
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module tank_up_img_blk_mem_gen_prim_wrapper_init
(douta,
clka,
@@ -387,7 +384,6 @@ module tank_up_img_blk_mem_gen_prim_wrapper_init
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module tank_up_img_blk_mem_gen_top
(douta,
clka,
@@ -435,7 +431,7 @@ endmodule
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "1024" *)
(* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
(* downgradeipidentifiedwarnings = "yes" *)
module tank_up_img_blk_mem_gen_v8_4_4
(clka,
rsta,
@@ -647,7 +643,6 @@ module tank_up_img_blk_mem_gen_v8_4_4
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
module tank_up_img_blk_mem_gen_v8_4_4_synth
(douta,
clka,
TankGame.srcs/sources_1/ip/tank_up_img/tank_up_img_sim_netlist.vhdl
+3 -15
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Tue Dec 29 16:28:51 2020
-- Date : Tue Dec 29 16:28:50 2020
-- Host : cxz666 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/tank_up_img/tank_up_img_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top tank_up_img -prefix
-- tank_up_img_ tank_up_img_sim_netlist.vhdl
-- Design : tank_up_img
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -21,8 +21,6 @@ entity tank_up_img_blk_mem_gen_prim_wrapper_init is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_up_img_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end tank_up_img_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of tank_up_img_blk_mem_gen_prim_wrapper_init is
@@ -182,8 +180,6 @@ entity tank_up_img_blk_mem_gen_prim_width is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_up_img_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end tank_up_img_blk_mem_gen_prim_width;
architecture STRUCTURE of tank_up_img_blk_mem_gen_prim_width is
@@ -207,8 +203,6 @@ entity tank_up_img_blk_mem_gen_generic_cstr is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_up_img_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end tank_up_img_blk_mem_gen_generic_cstr;
architecture STRUCTURE of tank_up_img_blk_mem_gen_generic_cstr is
@@ -232,8 +226,6 @@ entity tank_up_img_blk_mem_gen_top is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_up_img_blk_mem_gen_top : entity is "blk_mem_gen_top";
end tank_up_img_blk_mem_gen_top;
architecture STRUCTURE of tank_up_img_blk_mem_gen_top is
@@ -257,8 +249,6 @@ entity tank_up_img_blk_mem_gen_v8_4_4_synth is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_up_img_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
end tank_up_img_blk_mem_gen_v8_4_4_synth;
architecture STRUCTURE of tank_up_img_blk_mem_gen_v8_4_4_synth is
@@ -491,8 +481,6 @@ entity tank_up_img_blk_mem_gen_v8_4_4 is
attribute C_WRITE_WIDTH_B of tank_up_img_blk_mem_gen_v8_4_4 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of tank_up_img_blk_mem_gen_v8_4_4 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_up_img_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of tank_up_img_blk_mem_gen_v8_4_4 : entity is "yes";
end tank_up_img_blk_mem_gen_v8_4_4;