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update to 2021/1/1 only last enermy control to fix

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ChenXuzheng
2021-01-01 20:59:42 +08:00
parent 861fb88001
commit 38350c37bb
42 changed files with 1781 additions and 1049 deletions
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TankGame.srcs/sources_1/ip/bullet_down_img/bullet_down_img.xml
+128 -128
View File
@@ -1446,100 +1446,6 @@
</spirit:memoryMaps>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_veriloginstantiationtemplate</spirit:name>
<spirit:displayName>Verilog Instantiation Template</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.template</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:fileSetRef>
<spirit:localName>xilinx_veriloginstantiationtemplate_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 22 13:58:25 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:cc5e08b4</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 22 13:58:27 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d72f6b69</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>bullet_down_img</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 22 13:58:27 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:d72f6b69</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_project_archive</spirit:name>
<spirit:displayName>Miscellaneous</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:misc.files</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_project_archive_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 22 13:58:27 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:cc5e08b4</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_versioninformation</spirit:name>
<spirit:displayName>Version Information</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:docs.versioninfo</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_versioninformation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 22 13:58:27 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:cc5e08b4</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
<spirit:displayName>VHDL Synthesis</spirit:displayName>
@@ -1552,11 +1458,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:26:41 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:39:54 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:c4d6b101</spirit:value>
<spirit:value>9:f04125b1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1567,7 +1473,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:c4d6b101</spirit:value>
<spirit:value>9:f04125b1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1583,11 +1489,105 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:26:41 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:39:54 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:c4d6b101</spirit:value>
<spirit:value>9:f04125b1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_veriloginstantiationtemplate</spirit:name>
<spirit:displayName>Verilog Instantiation Template</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.template</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:fileSetRef>
<spirit:localName>xilinx_veriloginstantiationtemplate_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Dec 30 13:18:06 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:f04125b1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Dec 30 13:18:06 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:93548381</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>bullet_down_img</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Dec 30 13:18:06 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:93548381</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_project_archive</spirit:name>
<spirit:displayName>Miscellaneous</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:misc.files</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_project_archive_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Dec 30 13:18:06 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:f04125b1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_versioninformation</spirit:name>
<spirit:displayName>Version Information</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:docs.versioninfo</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_versioninformation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Dec 30 13:18:06 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:f04125b1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1601,11 +1601,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:30:53 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 13:18:23 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:c4d6b101</spirit:value>
<spirit:value>9:f04125b1</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -3535,6 +3535,33 @@
</spirit:choice>
</spirit:choices>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>bullet_down_img_ooc.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>bullet_down_img.mif</spirit:name>
<spirit:userFileType>mif</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/bullet_down_img.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_veriloginstantiationtemplate_view_fileset</spirit:name>
<spirit:file>
@@ -3586,33 +3613,6 @@
<spirit:userFileType>text</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>bullet_down_img_ooc.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>bullet_down_img.mif</spirit:name>
<spirit:userFileType>mif</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/bullet_down_img.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
<spirit:file>
TankGame.srcs/sources_1/ip/bullet_down_img/bullet_down_img_sim_netlist.v
+3 -8
View File
@@ -3,8 +3,8 @@
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
// Date : Tue Dec 29 16:30:53 2020
// Host : cxz666 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/bullet_down_img/bullet_down_img_sim_netlist.v
// Command : write_verilog -force -mode funcsim -rename_top bullet_down_img -prefix
// bullet_down_img_ bullet_down_img_sim_netlist.v
// Design : bullet_down_img
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -191,7 +191,6 @@ module bullet_down_img
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module bullet_down_img_blk_mem_gen_generic_cstr
(douta,
clka,
@@ -214,7 +213,6 @@ module bullet_down_img_blk_mem_gen_generic_cstr
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bullet_down_img_blk_mem_gen_prim_width
(douta,
clka,
@@ -237,7 +235,6 @@ module bullet_down_img_blk_mem_gen_prim_width
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bullet_down_img_blk_mem_gen_prim_wrapper_init
(douta,
clka,
@@ -403,7 +400,6 @@ module bullet_down_img_blk_mem_gen_prim_wrapper_init
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module bullet_down_img_blk_mem_gen_top
(douta,
clka,
@@ -451,7 +447,7 @@ endmodule
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "50" *)
(* C_WRITE_DEPTH_B = "50" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
(* downgradeipidentifiedwarnings = "yes" *)
module bullet_down_img_blk_mem_gen_v8_4_4
(clka,
rsta,
@@ -655,7 +651,6 @@ module bullet_down_img_blk_mem_gen_v8_4_4
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
module bullet_down_img_blk_mem_gen_v8_4_4_synth
(douta,
clka,
TankGame.srcs/sources_1/ip/bullet_down_img/bullet_down_img_sim_netlist.vhdl
+2 -14
View File
@@ -3,8 +3,8 @@
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Tue Dec 29 16:30:53 2020
-- Host : cxz666 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/bullet_down_img/bullet_down_img_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top bullet_down_img -prefix
-- bullet_down_img_ bullet_down_img_sim_netlist.vhdl
-- Design : bullet_down_img
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -21,8 +21,6 @@ entity bullet_down_img_blk_mem_gen_prim_wrapper_init is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_down_img_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bullet_down_img_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bullet_down_img_blk_mem_gen_prim_wrapper_init is
@@ -219,8 +217,6 @@ entity bullet_down_img_blk_mem_gen_prim_width is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_down_img_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bullet_down_img_blk_mem_gen_prim_width;
architecture STRUCTURE of bullet_down_img_blk_mem_gen_prim_width is
@@ -244,8 +240,6 @@ entity bullet_down_img_blk_mem_gen_generic_cstr is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_down_img_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bullet_down_img_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bullet_down_img_blk_mem_gen_generic_cstr is
@@ -269,8 +263,6 @@ entity bullet_down_img_blk_mem_gen_top is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_down_img_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bullet_down_img_blk_mem_gen_top;
architecture STRUCTURE of bullet_down_img_blk_mem_gen_top is
@@ -294,8 +286,6 @@ entity bullet_down_img_blk_mem_gen_v8_4_4_synth is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_down_img_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
end bullet_down_img_blk_mem_gen_v8_4_4_synth;
architecture STRUCTURE of bullet_down_img_blk_mem_gen_v8_4_4_synth is
@@ -528,8 +518,6 @@ entity bullet_down_img_blk_mem_gen_v8_4_4 is
attribute C_WRITE_WIDTH_B of bullet_down_img_blk_mem_gen_v8_4_4 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bullet_down_img_blk_mem_gen_v8_4_4 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bullet_down_img_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bullet_down_img_blk_mem_gen_v8_4_4 : entity is "yes";
end bullet_down_img_blk_mem_gen_v8_4_4;