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update to 2021/1/1 only last enermy control to fix

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ChenXuzheng
2021-01-01 20:59:42 +08:00
parent 861fb88001
commit 38350c37bb
42 changed files with 1781 additions and 1049 deletions
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TankGame.srcs/sources_1/ip/gameover_380_180/gameover_380_180.xml
+80 -80
View File
@@ -1465,57 +1465,6 @@
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
<spirit:displayName>VHDL Synthesis</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 12:18:03 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a566edfa</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_synthesisconstraints</spirit:name>
<spirit:displayName>Synthesis Constraints</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a566edfa</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>gameover_380_180</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 12:18:03 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a566edfa</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
@@ -1591,6 +1540,57 @@
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
<spirit:displayName>VHDL Synthesis</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Dec 30 00:40:02 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:c54f3c26</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_synthesisconstraints</spirit:name>
<spirit:displayName>Synthesis Constraints</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:c54f3c26</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
<spirit:language>vhdl</spirit:language>
<spirit:modelName>gameover_380_180</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Wed Dec 30 00:40:02 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:c54f3c26</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_externalfiles</spirit:name>
<spirit:displayName>External Files</spirit:displayName>
@@ -1601,11 +1601,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 12:20:02 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:40:43 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a566edfa</spirit:value>
<spirit:value>9:c54f3c26</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -3549,33 +3549,6 @@
<spirit:userFileType>verilogTemplate</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>gameover_380_180_ooc.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>gameover_380_180.mif</spirit:name>
<spirit:userFileType>mif</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/gameover_380_180.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
<spirit:file>
@@ -3616,6 +3589,33 @@
<spirit:userFileType>text</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
<spirit:file>
<spirit:name>gameover_380_180_ooc.xdc</spirit:name>
<spirit:userFileType>xdc</spirit:userFileType>
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>gameover_380_180.mif</spirit:name>
<spirit:userFileType>mif</spirit:userFileType>
</spirit:file>
<spirit:file>
<spirit:name>hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
<spirit:file>
<spirit:name>synth/gameover_380_180.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
<spirit:file>
TankGame.srcs/sources_1/ip/gameover_380_180/gameover_380_180_sim_netlist.v
+4 -11
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
// Date : Tue Dec 29 20:20:02 2020
// Date : Tue Dec 29 20:20:01 2020
// Host : cxz666 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// e:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/gameover_380_180/gameover_380_180_sim_netlist.v
// Command : write_verilog -force -mode funcsim -rename_top gameover_380_180 -prefix
// gameover_380_180_ gameover_380_180_sim_netlist.v
// Design : gameover_380_180
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -191,7 +191,6 @@ module gameover_380_180
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "bindec" *)
module gameover_380_180_bindec
(ena_array,
addra,
@@ -376,7 +375,6 @@ module gameover_380_180_bindec
.O(ena_array[10]));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module gameover_380_180_blk_mem_gen_generic_cstr
(douta,
clka,
@@ -766,7 +764,6 @@ module gameover_380_180_blk_mem_gen_generic_cstr
.ena_array(ena_array[4]));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_mux" *)
module gameover_380_180_blk_mem_gen_mux
(douta,
DOADO,
@@ -1687,7 +1684,6 @@ module gameover_380_180_blk_mem_gen_mux
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module gameover_380_180_blk_mem_gen_prim_width
(DOUTA,
clka,
@@ -2345,7 +2341,6 @@ module gameover_380_180_blk_mem_gen_prim_width__parameterized9
.ena_array(ena_array));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module gameover_380_180_blk_mem_gen_prim_wrapper_init
(DOUTA,
clka,
@@ -8181,7 +8176,6 @@ module gameover_380_180_blk_mem_gen_prim_wrapper_init__parameterized9
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module gameover_380_180_blk_mem_gen_top
(douta,
clka,
@@ -8229,7 +8223,7 @@ endmodule
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "68400" *)
(* C_WRITE_DEPTH_B = "68400" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
(* downgradeipidentifiedwarnings = "yes" *)
module gameover_380_180_blk_mem_gen_v8_4_4
(clka,
rsta,
@@ -8455,7 +8449,6 @@ module gameover_380_180_blk_mem_gen_v8_4_4
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
module gameover_380_180_blk_mem_gen_v8_4_4_synth
(douta,
clka,
TankGame.srcs/sources_1/ip/gameover_380_180/gameover_380_180_sim_netlist.vhdl
+3 -19
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Tue Dec 29 20:20:02 2020
-- Date : Tue Dec 29 20:20:01 2020
-- Host : cxz666 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- e:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/gameover_380_180/gameover_380_180_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top gameover_380_180 -prefix
-- gameover_380_180_ gameover_380_180_sim_netlist.vhdl
-- Design : gameover_380_180
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -20,8 +20,6 @@ entity gameover_380_180_bindec is
addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
ena : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gameover_380_180_bindec : entity is "bindec";
end gameover_380_180_bindec;
architecture STRUCTURE of gameover_380_180_bindec is
@@ -298,8 +296,6 @@ entity gameover_380_180_blk_mem_gen_mux is
\douta[11]_INST_0_i_2_6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\douta[11]_INST_0_i_2_7\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end gameover_380_180_blk_mem_gen_mux;
architecture STRUCTURE of gameover_380_180_blk_mem_gen_mux is
@@ -1340,8 +1336,6 @@ entity gameover_380_180_blk_mem_gen_prim_wrapper_init is
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end gameover_380_180_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of gameover_380_180_blk_mem_gen_prim_wrapper_init is
@@ -7274,8 +7268,6 @@ entity gameover_380_180_blk_mem_gen_prim_width is
\^ena\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end gameover_380_180_blk_mem_gen_prim_width;
architecture STRUCTURE of gameover_380_180_blk_mem_gen_prim_width is
@@ -7899,8 +7891,6 @@ entity gameover_380_180_blk_mem_gen_generic_cstr is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end gameover_380_180_blk_mem_gen_generic_cstr;
architecture STRUCTURE of gameover_380_180_blk_mem_gen_generic_cstr is
@@ -8583,8 +8573,6 @@ entity gameover_380_180_blk_mem_gen_top is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_top : entity is "blk_mem_gen_top";
end gameover_380_180_blk_mem_gen_top;
architecture STRUCTURE of gameover_380_180_blk_mem_gen_top is
@@ -8608,8 +8596,6 @@ entity gameover_380_180_blk_mem_gen_v8_4_4_synth is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
end gameover_380_180_blk_mem_gen_v8_4_4_synth;
architecture STRUCTURE of gameover_380_180_blk_mem_gen_v8_4_4_synth is
@@ -8842,8 +8828,6 @@ entity gameover_380_180_blk_mem_gen_v8_4_4 is
attribute C_WRITE_WIDTH_B of gameover_380_180_blk_mem_gen_v8_4_4 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of gameover_380_180_blk_mem_gen_v8_4_4 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of gameover_380_180_blk_mem_gen_v8_4_4 : entity is "yes";
end gameover_380_180_blk_mem_gen_v8_4_4;