update to 2021/1/1 only last enermy control to fix
This commit is contained in:
@@ -1465,57 +1465,6 @@
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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||||
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
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||||
<spirit:displayName>VHDL Synthesis</spirit:displayName>
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||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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||||
<spirit:language>vhdl</spirit:language>
|
||||
<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
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||||
<spirit:fileSetRef>
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||||
<spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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||||
<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Tue Dec 29 12:29:56 UTC 2020</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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||||
<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:ba70ca63</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_synthesisconstraints</spirit:name>
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||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:ba70ca63</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
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<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
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<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
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<spirit:language>vhdl</spirit:language>
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<spirit:modelName>startpic_450_200</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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||||
<spirit:parameter>
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||||
<spirit:name>GENtimestamp</spirit:name>
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||||
<spirit:value>Tue Dec 29 12:29:56 UTC 2020</spirit:value>
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||||
</spirit:parameter>
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||||
<spirit:parameter>
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||||
<spirit:name>outputProductCRC</spirit:name>
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||||
<spirit:value>9:ba70ca63</spirit:value>
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||||
</spirit:parameter>
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||||
</spirit:parameters>
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||||
</spirit:view>
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||||
<spirit:view>
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<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
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<spirit:displayName>Simulation</spirit:displayName>
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@@ -1591,6 +1540,57 @@
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_vhdlsynthesis</spirit:name>
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<spirit:displayName>VHDL Synthesis</spirit:displayName>
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<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:language>vhdl</spirit:language>
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<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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||||
<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Wed Dec 30 00:40:12 UTC 2020</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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||||
<spirit:value>9:17e55f2b</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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||||
<spirit:view>
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||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
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||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
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||||
<spirit:parameters>
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||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:17e55f2b</spirit:value>
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||||
</spirit:parameter>
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||||
</spirit:parameters>
|
||||
</spirit:view>
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||||
<spirit:view>
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||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
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<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
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||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
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||||
<spirit:language>vhdl</spirit:language>
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||||
<spirit:modelName>startpic_450_200</spirit:modelName>
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||||
<spirit:fileSetRef>
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||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
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||||
</spirit:fileSetRef>
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||||
<spirit:parameters>
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||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
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||||
<spirit:value>Wed Dec 30 00:40:12 UTC 2020</spirit:value>
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||||
</spirit:parameter>
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||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:17e55f2b</spirit:value>
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||||
</spirit:parameter>
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||||
</spirit:parameters>
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||||
</spirit:view>
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||||
<spirit:view>
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||||
<spirit:name>xilinx_externalfiles</spirit:name>
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||||
<spirit:displayName>External Files</spirit:displayName>
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||||
@@ -1601,11 +1601,11 @@
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<spirit:parameters>
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||||
<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Tue Dec 29 12:32:03 UTC 2020</spirit:value>
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||||
<spirit:value>Wed Dec 30 00:40:43 UTC 2020</spirit:value>
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||||
</spirit:parameter>
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||||
<spirit:parameter>
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||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:ba70ca63</spirit:value>
|
||||
<spirit:value>9:17e55f2b</spirit:value>
|
||||
</spirit:parameter>
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||||
</spirit:parameters>
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</spirit:view>
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||||
@@ -3549,33 +3549,6 @@
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<spirit:userFileType>verilogTemplate</spirit:userFileType>
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</spirit:file>
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</spirit:fileSet>
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||||
<spirit:fileSet>
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||||
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
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||||
<spirit:file>
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||||
<spirit:name>startpic_450_200_ooc.xdc</spirit:name>
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||||
<spirit:userFileType>xdc</spirit:userFileType>
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||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
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||||
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
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||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
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||||
</spirit:file>
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||||
<spirit:file>
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||||
<spirit:name>startpic_450_200.mif</spirit:name>
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||||
<spirit:userFileType>mif</spirit:userFileType>
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</spirit:file>
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<spirit:file>
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||||
<spirit:name>hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd</spirit:name>
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||||
<spirit:fileType>vhdlSource</spirit:fileType>
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||||
<spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
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||||
</spirit:file>
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||||
</spirit:fileSet>
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||||
<spirit:fileSet>
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||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
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||||
<spirit:file>
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||||
<spirit:name>synth/startpic_450_200.vhd</spirit:name>
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||||
<spirit:fileType>vhdlSource</spirit:fileType>
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||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
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||||
</spirit:file>
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||||
</spirit:fileSet>
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||||
<spirit:fileSet>
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||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
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||||
<spirit:file>
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||||
@@ -3616,6 +3589,33 @@
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<spirit:userFileType>text</spirit:userFileType>
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</spirit:file>
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</spirit:fileSet>
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||||
<spirit:fileSet>
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||||
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
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||||
<spirit:file>
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||||
<spirit:name>startpic_450_200_ooc.xdc</spirit:name>
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||||
<spirit:userFileType>xdc</spirit:userFileType>
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||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
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||||
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
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||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
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||||
</spirit:file>
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||||
<spirit:file>
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||||
<spirit:name>startpic_450_200.mif</spirit:name>
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||||
<spirit:userFileType>mif</spirit:userFileType>
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||||
</spirit:file>
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||||
<spirit:file>
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||||
<spirit:name>hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd</spirit:name>
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||||
<spirit:fileType>vhdlSource</spirit:fileType>
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||||
<spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
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||||
</spirit:file>
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||||
</spirit:fileSet>
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||||
<spirit:fileSet>
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||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
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||||
<spirit:file>
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||||
<spirit:name>synth/startpic_450_200.vhd</spirit:name>
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||||
<spirit:fileType>vhdlSource</spirit:fileType>
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||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
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||||
</spirit:file>
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||||
</spirit:fileSet>
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||||
<spirit:fileSet>
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||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
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||||
<spirit:file>
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||||
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@@ -1,10 +1,10 @@
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||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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||||
// --------------------------------------------------------------------------------
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||||
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||
// Date : Tue Dec 29 20:32:03 2020
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||||
// Date : Tue Dec 29 20:32:02 2020
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||||
// Host : cxz666 running 64-bit major release (build 9200)
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||||
// Command : write_verilog -force -mode funcsim
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||||
// e:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/startpic_450_200/startpic_450_200_sim_netlist.v
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||||
// Command : write_verilog -force -mode funcsim -rename_top startpic_450_200 -prefix
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||||
// startpic_450_200_ startpic_450_200_sim_netlist.v
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// Design : startpic_450_200
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||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
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||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
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||||
@@ -191,7 +191,6 @@ module startpic_450_200
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||||
.web(1'b0));
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endmodule
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||||
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||||
(* ORIG_REF_NAME = "bindec" *)
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||||
module startpic_450_200_bindec
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(ena_array,
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addra,
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@@ -416,7 +415,6 @@ module startpic_450_200_bindec
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.O(ena_array[10]));
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endmodule
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||||
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||||
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
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||||
module startpic_450_200_blk_mem_gen_generic_cstr
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||||
(douta,
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||||
clka,
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||||
@@ -911,7 +909,6 @@ module startpic_450_200_blk_mem_gen_generic_cstr
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||||
.ena_array(ena_array[2]));
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||||
endmodule
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||||
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||||
(* ORIG_REF_NAME = "blk_mem_gen_mux" *)
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||||
module startpic_450_200_blk_mem_gen_mux
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(douta,
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||||
DOADO,
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||||
@@ -2027,7 +2024,6 @@ module startpic_450_200_blk_mem_gen_mux
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||||
.R(1'b0));
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||||
endmodule
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||||
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||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
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||||
module startpic_450_200_blk_mem_gen_prim_width
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(DOUTA,
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clka,
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||||
@@ -2891,7 +2887,6 @@ module startpic_450_200_blk_mem_gen_prim_width__parameterized9
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.ena_array(ena_array));
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endmodule
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(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
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module startpic_450_200_blk_mem_gen_prim_wrapper_init
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(DOUTA,
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clka,
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@@ -10354,7 +10349,6 @@ module startpic_450_200_blk_mem_gen_prim_wrapper_init__parameterized9
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.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
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||||
endmodule
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||||
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||||
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
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module startpic_450_200_blk_mem_gen_top
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(douta,
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clka,
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@@ -10402,7 +10396,7 @@ endmodule
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||||
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "90000" *)
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||||
(* C_WRITE_DEPTH_B = "90000" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
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||||
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
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||||
(* downgradeipidentifiedwarnings = "yes" *)
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||||
module startpic_450_200_blk_mem_gen_v8_4_4
|
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(clka,
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rsta,
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@@ -10628,7 +10622,6 @@ module startpic_450_200_blk_mem_gen_v8_4_4
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.ena(ena));
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endmodule
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||||
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(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
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||||
module startpic_450_200_blk_mem_gen_v8_4_4_synth
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(douta,
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clka,
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@@ -1,10 +1,10 @@
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||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||
-- Date : Tue Dec 29 20:32:03 2020
|
||||
-- Date : Tue Dec 29 20:32:02 2020
|
||||
-- Host : cxz666 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim
|
||||
-- e:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/startpic_450_200/startpic_450_200_sim_netlist.vhdl
|
||||
-- Command : write_vhdl -force -mode funcsim -rename_top startpic_450_200 -prefix
|
||||
-- startpic_450_200_ startpic_450_200_sim_netlist.vhdl
|
||||
-- Design : startpic_450_200
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
@@ -20,8 +20,6 @@ entity startpic_450_200_bindec is
|
||||
addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
|
||||
ena : in STD_LOGIC
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of startpic_450_200_bindec : entity is "bindec";
|
||||
end startpic_450_200_bindec;
|
||||
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||||
architecture STRUCTURE of startpic_450_200_bindec is
|
||||
@@ -362,8 +360,6 @@ entity startpic_450_200_blk_mem_gen_mux is
|
||||
\douta[11]_INST_0_i_1_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
\douta[11]_INST_0_i_1_4\ : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
|
||||
end startpic_450_200_blk_mem_gen_mux;
|
||||
|
||||
architecture STRUCTURE of startpic_450_200_blk_mem_gen_mux is
|
||||
@@ -1615,8 +1611,6 @@ entity startpic_450_200_blk_mem_gen_prim_wrapper_init is
|
||||
\^ena\ : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
|
||||
end startpic_450_200_blk_mem_gen_prim_wrapper_init;
|
||||
|
||||
architecture STRUCTURE of startpic_450_200_blk_mem_gen_prim_wrapper_init is
|
||||
@@ -9212,8 +9206,6 @@ entity startpic_450_200_blk_mem_gen_prim_width is
|
||||
\^ena\ : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
|
||||
end startpic_450_200_blk_mem_gen_prim_width;
|
||||
|
||||
architecture STRUCTURE of startpic_450_200_blk_mem_gen_prim_width is
|
||||
@@ -10036,8 +10028,6 @@ entity startpic_450_200_blk_mem_gen_generic_cstr is
|
||||
ena : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
|
||||
end startpic_450_200_blk_mem_gen_generic_cstr;
|
||||
|
||||
architecture STRUCTURE of startpic_450_200_blk_mem_gen_generic_cstr is
|
||||
@@ -10910,8 +10900,6 @@ entity startpic_450_200_blk_mem_gen_top is
|
||||
ena : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_top : entity is "blk_mem_gen_top";
|
||||
end startpic_450_200_blk_mem_gen_top;
|
||||
|
||||
architecture STRUCTURE of startpic_450_200_blk_mem_gen_top is
|
||||
@@ -10935,8 +10923,6 @@ entity startpic_450_200_blk_mem_gen_v8_4_4_synth is
|
||||
ena : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
|
||||
end startpic_450_200_blk_mem_gen_v8_4_4_synth;
|
||||
|
||||
architecture STRUCTURE of startpic_450_200_blk_mem_gen_v8_4_4_synth is
|
||||
@@ -11169,8 +11155,6 @@ entity startpic_450_200_blk_mem_gen_v8_4_4 is
|
||||
attribute C_WRITE_WIDTH_B of startpic_450_200_blk_mem_gen_v8_4_4 : entity is 12;
|
||||
attribute C_XDEVICEFAMILY : string;
|
||||
attribute C_XDEVICEFAMILY of startpic_450_200_blk_mem_gen_v8_4_4 : entity is "artix7";
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
|
||||
attribute downgradeipidentifiedwarnings : string;
|
||||
attribute downgradeipidentifiedwarnings of startpic_450_200_blk_mem_gen_v8_4_4 : entity is "yes";
|
||||
end startpic_450_200_blk_mem_gen_v8_4_4;
|
||||
|
||||
Reference in New Issue
Block a user