ChenXuzheng/FPGA-TankGame-new
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update to 2021/1/1 only last enermy control to fix

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ChenXuzheng
2021-01-01 20:59:42 +08:00
parent 861fb88001
commit 38350c37bb
42 changed files with 1781 additions and 1049 deletions
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TankGame.srcs/sources_1/ip/tank_up_img/tank_up_img.xml
+7 -7
View File
@@ -1552,11 +1552,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:26:39 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:39:52 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a68d50f1</spirit:value>
<spirit:value>9:521e566d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1567,7 +1567,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a68d50f1</spirit:value>
<spirit:value>9:521e566d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1583,11 +1583,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:26:39 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:39:52 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a68d50f1</spirit:value>
<spirit:value>9:521e566d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1601,11 +1601,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Tue Dec 29 08:28:51 UTC 2020</spirit:value>
<spirit:value>Wed Dec 30 00:40:33 UTC 2020</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:a68d50f1</spirit:value>
<spirit:value>9:521e566d</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
TankGame.srcs/sources_1/ip/tank_up_img/tank_up_img_sim_netlist.v
+4 -9
View File
@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
// Date : Tue Dec 29 16:28:51 2020
// Date : Tue Dec 29 16:28:50 2020
// Host : cxz666 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/tank_up_img/tank_up_img_sim_netlist.v
// Command : write_verilog -force -mode funcsim -rename_top tank_up_img -prefix
// tank_up_img_ tank_up_img_sim_netlist.v
// Design : tank_up_img
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -191,7 +191,6 @@ module tank_up_img
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module tank_up_img_blk_mem_gen_generic_cstr
(douta,
clka,
@@ -214,7 +213,6 @@ module tank_up_img_blk_mem_gen_generic_cstr
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module tank_up_img_blk_mem_gen_prim_width
(douta,
clka,
@@ -237,7 +235,6 @@ module tank_up_img_blk_mem_gen_prim_width
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module tank_up_img_blk_mem_gen_prim_wrapper_init
(douta,
clka,
@@ -387,7 +384,6 @@ module tank_up_img_blk_mem_gen_prim_wrapper_init
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module tank_up_img_blk_mem_gen_top
(douta,
clka,
@@ -435,7 +431,7 @@ endmodule
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "1024" *)
(* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
(* downgradeipidentifiedwarnings = "yes" *)
module tank_up_img_blk_mem_gen_v8_4_4
(clka,
rsta,
@@ -647,7 +643,6 @@ module tank_up_img_blk_mem_gen_v8_4_4
.ena(ena));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
module tank_up_img_blk_mem_gen_v8_4_4_synth
(douta,
clka,
TankGame.srcs/sources_1/ip/tank_up_img/tank_up_img_sim_netlist.vhdl
+3 -15
View File
@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Tue Dec 29 16:28:51 2020
-- Date : Tue Dec 29 16:28:50 2020
-- Host : cxz666 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/tank_up_img/tank_up_img_sim_netlist.vhdl
-- Command : write_vhdl -force -mode funcsim -rename_top tank_up_img -prefix
-- tank_up_img_ tank_up_img_sim_netlist.vhdl
-- Design : tank_up_img
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
@@ -21,8 +21,6 @@ entity tank_up_img_blk_mem_gen_prim_wrapper_init is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_up_img_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end tank_up_img_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of tank_up_img_blk_mem_gen_prim_wrapper_init is
@@ -182,8 +180,6 @@ entity tank_up_img_blk_mem_gen_prim_width is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_up_img_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end tank_up_img_blk_mem_gen_prim_width;
architecture STRUCTURE of tank_up_img_blk_mem_gen_prim_width is
@@ -207,8 +203,6 @@ entity tank_up_img_blk_mem_gen_generic_cstr is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_up_img_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end tank_up_img_blk_mem_gen_generic_cstr;
architecture STRUCTURE of tank_up_img_blk_mem_gen_generic_cstr is
@@ -232,8 +226,6 @@ entity tank_up_img_blk_mem_gen_top is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_up_img_blk_mem_gen_top : entity is "blk_mem_gen_top";
end tank_up_img_blk_mem_gen_top;
architecture STRUCTURE of tank_up_img_blk_mem_gen_top is
@@ -257,8 +249,6 @@ entity tank_up_img_blk_mem_gen_v8_4_4_synth is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_up_img_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
end tank_up_img_blk_mem_gen_v8_4_4_synth;
architecture STRUCTURE of tank_up_img_blk_mem_gen_v8_4_4_synth is
@@ -491,8 +481,6 @@ entity tank_up_img_blk_mem_gen_v8_4_4 is
attribute C_WRITE_WIDTH_B of tank_up_img_blk_mem_gen_v8_4_4 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of tank_up_img_blk_mem_gen_v8_4_4 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of tank_up_img_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of tank_up_img_blk_mem_gen_v8_4_4 : entity is "yes";
end tank_up_img_blk_mem_gen_v8_4_4;