update to 2021/1/1 only last enermy control to fix
parent
861fb88001
commit
38350c37bb
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@ -1446,100 +1446,6 @@
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</spirit:memoryMaps>
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</spirit:memoryMaps>
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<spirit:model>
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<spirit:model>
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<spirit:views>
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<spirit:views>
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<spirit:view>
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<spirit:name>xilinx_veriloginstantiationtemplate</spirit:name>
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<spirit:displayName>Verilog Instantiation Template</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.template</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_veriloginstantiationtemplate_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Tue Dec 22 13:58:25 UTC 2020</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:cc5e08b4</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
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<spirit:displayName>Simulation</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Tue Dec 22 13:58:27 UTC 2020</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:d72f6b69</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
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<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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<spirit:modelName>bullet_down_img</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Tue Dec 22 13:58:27 UTC 2020</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:d72f6b69</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_project_archive</spirit:name>
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<spirit:displayName>Miscellaneous</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:misc.files</spirit:envIdentifier>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_project_archive_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Tue Dec 22 13:58:27 UTC 2020</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:cc5e08b4</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_versioninformation</spirit:name>
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<spirit:displayName>Version Information</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:docs.versioninfo</spirit:envIdentifier>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_versioninformation_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Tue Dec 22 13:58:27 UTC 2020</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:cc5e08b4</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:view>
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<spirit:name>xilinx_vhdlsynthesis</spirit:name>
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<spirit:name>xilinx_vhdlsynthesis</spirit:name>
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<spirit:displayName>VHDL Synthesis</spirit:displayName>
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<spirit:displayName>VHDL Synthesis</spirit:displayName>
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@ -1552,11 +1458,11 @@
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<spirit:parameters>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Tue Dec 29 08:26:41 UTC 2020</spirit:value>
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<spirit:value>Wed Dec 30 00:39:54 UTC 2020</spirit:value>
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</spirit:parameter>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:c4d6b101</spirit:value>
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<spirit:value>9:f04125b1</spirit:value>
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</spirit:parameter>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:parameters>
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</spirit:view>
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</spirit:view>
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@ -1567,7 +1473,7 @@
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<spirit:parameters>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:c4d6b101</spirit:value>
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<spirit:value>9:f04125b1</spirit:value>
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</spirit:parameter>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:parameters>
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</spirit:view>
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</spirit:view>
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@ -1583,11 +1489,105 @@
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<spirit:parameters>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Tue Dec 29 08:26:41 UTC 2020</spirit:value>
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<spirit:value>Wed Dec 30 00:39:54 UTC 2020</spirit:value>
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</spirit:parameter>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:c4d6b101</spirit:value>
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<spirit:value>9:f04125b1</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_veriloginstantiationtemplate</spirit:name>
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<spirit:displayName>Verilog Instantiation Template</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.template</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_veriloginstantiationtemplate_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Wed Dec 30 13:18:06 UTC 2020</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:f04125b1</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
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<spirit:displayName>Simulation</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Wed Dec 30 13:18:06 UTC 2020</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:93548381</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
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<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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<spirit:modelName>bullet_down_img</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Wed Dec 30 13:18:06 UTC 2020</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:93548381</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_project_archive</spirit:name>
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<spirit:displayName>Miscellaneous</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:misc.files</spirit:envIdentifier>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_project_archive_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Wed Dec 30 13:18:06 UTC 2020</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:f04125b1</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_versioninformation</spirit:name>
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<spirit:displayName>Version Information</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:docs.versioninfo</spirit:envIdentifier>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_versioninformation_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Wed Dec 30 13:18:06 UTC 2020</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:f04125b1</spirit:value>
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</spirit:parameter>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:parameters>
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</spirit:view>
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</spirit:view>
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<spirit:parameters>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:parameter>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:name>GENtimestamp</spirit:name>
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<spirit:value>Tue Dec 29 08:30:53 UTC 2020</spirit:value>
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<spirit:value>Wed Dec 30 13:18:23 UTC 2020</spirit:value>
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</spirit:parameter>
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</spirit:parameter>
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<spirit:parameter>
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<spirit:parameter>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:name>outputProductCRC</spirit:name>
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<spirit:value>9:c4d6b101</spirit:value>
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<spirit:value>9:f04125b1</spirit:value>
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</spirit:parameter>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:parameters>
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</spirit:view>
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</spirit:view>
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</spirit:choice>
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</spirit:choice>
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</spirit:choices>
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</spirit:choices>
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<spirit:fileSets>
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<spirit:fileSets>
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<spirit:fileSet>
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<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>bullet_down_img_ooc.xdc</spirit:name>
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<spirit:userFileType>xdc</spirit:userFileType>
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<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
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<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
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<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
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</spirit:file>
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<spirit:file>
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<spirit:name>bullet_down_img.mif</spirit:name>
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<spirit:userFileType>mif</spirit:userFileType>
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</spirit:file>
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<spirit:file>
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<spirit:name>hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd</spirit:name>
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<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
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</spirit:file>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>synth/bullet_down_img.vhd</spirit:name>
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<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:logicalName>xil_defaultlib</spirit:logicalName>
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</spirit:file>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_veriloginstantiationtemplate_view_fileset</spirit:name>
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<spirit:name>xilinx_veriloginstantiationtemplate_view_fileset</spirit:name>
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<spirit:file>
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<spirit:file>
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@ -3586,33 +3613,6 @@
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<spirit:userFileType>text</spirit:userFileType>
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<spirit:userFileType>text</spirit:userFileType>
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</spirit:file>
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</spirit:file>
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</spirit:fileSet>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>bullet_down_img_ooc.xdc</spirit:name>
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<spirit:userFileType>xdc</spirit:userFileType>
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<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
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<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
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<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
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</spirit:file>
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<spirit:file>
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<spirit:name>bullet_down_img.mif</spirit:name>
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<spirit:userFileType>mif</spirit:userFileType>
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</spirit:file>
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<spirit:file>
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<spirit:name>hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd</spirit:name>
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<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
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</spirit:file>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>synth/bullet_down_img.vhd</spirit:name>
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<spirit:fileType>vhdlSource</spirit:fileType>
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<spirit:logicalName>xil_defaultlib</spirit:logicalName>
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</spirit:file>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
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<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
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<spirit:file>
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<spirit:file>
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|
|
@ -3,8 +3,8 @@
|
||||||
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
// Date : Tue Dec 29 16:30:53 2020
|
// Date : Tue Dec 29 16:30:53 2020
|
||||||
// Host : cxz666 running 64-bit major release (build 9200)
|
// Host : cxz666 running 64-bit major release (build 9200)
|
||||||
// Command : write_verilog -force -mode funcsim
|
// Command : write_verilog -force -mode funcsim -rename_top bullet_down_img -prefix
|
||||||
// E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/bullet_down_img/bullet_down_img_sim_netlist.v
|
// bullet_down_img_ bullet_down_img_sim_netlist.v
|
||||||
// Design : bullet_down_img
|
// Design : bullet_down_img
|
||||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
|
@ -191,7 +191,6 @@ module bullet_down_img
|
||||||
.web(1'b0));
|
.web(1'b0));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
|
|
||||||
module bullet_down_img_blk_mem_gen_generic_cstr
|
module bullet_down_img_blk_mem_gen_generic_cstr
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -214,7 +213,6 @@ module bullet_down_img_blk_mem_gen_generic_cstr
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
|
|
||||||
module bullet_down_img_blk_mem_gen_prim_width
|
module bullet_down_img_blk_mem_gen_prim_width
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -237,7 +235,6 @@ module bullet_down_img_blk_mem_gen_prim_width
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
|
|
||||||
module bullet_down_img_blk_mem_gen_prim_wrapper_init
|
module bullet_down_img_blk_mem_gen_prim_wrapper_init
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -403,7 +400,6 @@ module bullet_down_img_blk_mem_gen_prim_wrapper_init
|
||||||
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
|
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
|
|
||||||
module bullet_down_img_blk_mem_gen_top
|
module bullet_down_img_blk_mem_gen_top
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -451,7 +447,7 @@ endmodule
|
||||||
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "50" *)
|
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "50" *)
|
||||||
(* C_WRITE_DEPTH_B = "50" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
(* C_WRITE_DEPTH_B = "50" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
||||||
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
|
(* downgradeipidentifiedwarnings = "yes" *)
|
||||||
module bullet_down_img_blk_mem_gen_v8_4_4
|
module bullet_down_img_blk_mem_gen_v8_4_4
|
||||||
(clka,
|
(clka,
|
||||||
rsta,
|
rsta,
|
||||||
|
|
@ -655,7 +651,6 @@ module bullet_down_img_blk_mem_gen_v8_4_4
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
|
|
||||||
module bullet_down_img_blk_mem_gen_v8_4_4_synth
|
module bullet_down_img_blk_mem_gen_v8_4_4_synth
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
|
||||||
|
|
@ -3,8 +3,8 @@
|
||||||
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
-- Date : Tue Dec 29 16:30:53 2020
|
-- Date : Tue Dec 29 16:30:53 2020
|
||||||
-- Host : cxz666 running 64-bit major release (build 9200)
|
-- Host : cxz666 running 64-bit major release (build 9200)
|
||||||
-- Command : write_vhdl -force -mode funcsim
|
-- Command : write_vhdl -force -mode funcsim -rename_top bullet_down_img -prefix
|
||||||
-- E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/bullet_down_img/bullet_down_img_sim_netlist.vhdl
|
-- bullet_down_img_ bullet_down_img_sim_netlist.vhdl
|
||||||
-- Design : bullet_down_img
|
-- Design : bullet_down_img
|
||||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
|
@ -21,8 +21,6 @@ entity bullet_down_img_blk_mem_gen_prim_wrapper_init is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_down_img_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
|
|
||||||
end bullet_down_img_blk_mem_gen_prim_wrapper_init;
|
end bullet_down_img_blk_mem_gen_prim_wrapper_init;
|
||||||
|
|
||||||
architecture STRUCTURE of bullet_down_img_blk_mem_gen_prim_wrapper_init is
|
architecture STRUCTURE of bullet_down_img_blk_mem_gen_prim_wrapper_init is
|
||||||
|
|
@ -219,8 +217,6 @@ entity bullet_down_img_blk_mem_gen_prim_width is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_down_img_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
|
|
||||||
end bullet_down_img_blk_mem_gen_prim_width;
|
end bullet_down_img_blk_mem_gen_prim_width;
|
||||||
|
|
||||||
architecture STRUCTURE of bullet_down_img_blk_mem_gen_prim_width is
|
architecture STRUCTURE of bullet_down_img_blk_mem_gen_prim_width is
|
||||||
|
|
@ -244,8 +240,6 @@ entity bullet_down_img_blk_mem_gen_generic_cstr is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_down_img_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
|
|
||||||
end bullet_down_img_blk_mem_gen_generic_cstr;
|
end bullet_down_img_blk_mem_gen_generic_cstr;
|
||||||
|
|
||||||
architecture STRUCTURE of bullet_down_img_blk_mem_gen_generic_cstr is
|
architecture STRUCTURE of bullet_down_img_blk_mem_gen_generic_cstr is
|
||||||
|
|
@ -269,8 +263,6 @@ entity bullet_down_img_blk_mem_gen_top is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_down_img_blk_mem_gen_top : entity is "blk_mem_gen_top";
|
|
||||||
end bullet_down_img_blk_mem_gen_top;
|
end bullet_down_img_blk_mem_gen_top;
|
||||||
|
|
||||||
architecture STRUCTURE of bullet_down_img_blk_mem_gen_top is
|
architecture STRUCTURE of bullet_down_img_blk_mem_gen_top is
|
||||||
|
|
@ -294,8 +286,6 @@ entity bullet_down_img_blk_mem_gen_v8_4_4_synth is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_down_img_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
|
|
||||||
end bullet_down_img_blk_mem_gen_v8_4_4_synth;
|
end bullet_down_img_blk_mem_gen_v8_4_4_synth;
|
||||||
|
|
||||||
architecture STRUCTURE of bullet_down_img_blk_mem_gen_v8_4_4_synth is
|
architecture STRUCTURE of bullet_down_img_blk_mem_gen_v8_4_4_synth is
|
||||||
|
|
@ -528,8 +518,6 @@ entity bullet_down_img_blk_mem_gen_v8_4_4 is
|
||||||
attribute C_WRITE_WIDTH_B of bullet_down_img_blk_mem_gen_v8_4_4 : entity is 12;
|
attribute C_WRITE_WIDTH_B of bullet_down_img_blk_mem_gen_v8_4_4 : entity is 12;
|
||||||
attribute C_XDEVICEFAMILY : string;
|
attribute C_XDEVICEFAMILY : string;
|
||||||
attribute C_XDEVICEFAMILY of bullet_down_img_blk_mem_gen_v8_4_4 : entity is "artix7";
|
attribute C_XDEVICEFAMILY of bullet_down_img_blk_mem_gen_v8_4_4 : entity is "artix7";
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_down_img_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
|
|
||||||
attribute downgradeipidentifiedwarnings : string;
|
attribute downgradeipidentifiedwarnings : string;
|
||||||
attribute downgradeipidentifiedwarnings of bullet_down_img_blk_mem_gen_v8_4_4 : entity is "yes";
|
attribute downgradeipidentifiedwarnings of bullet_down_img_blk_mem_gen_v8_4_4 : entity is "yes";
|
||||||
end bullet_down_img_blk_mem_gen_v8_4_4;
|
end bullet_down_img_blk_mem_gen_v8_4_4;
|
||||||
|
|
|
||||||
|
|
@ -1552,11 +1552,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:26:41 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:39:54 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:105510ed</spirit:value>
|
<spirit:value>9:24c2845d</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1567,7 +1567,7 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:105510ed</spirit:value>
|
<spirit:value>9:24c2845d</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1583,11 +1583,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:26:41 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:39:54 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:105510ed</spirit:value>
|
<spirit:value>9:24c2845d</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1601,11 +1601,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:30:54 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:40:32 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:105510ed</spirit:value>
|
<spirit:value>9:24c2845d</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
|
||||||
|
|
@ -1,10 +1,10 @@
|
||||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
// --------------------------------------------------------------------------------
|
// --------------------------------------------------------------------------------
|
||||||
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
// Date : Tue Dec 29 16:30:54 2020
|
// Date : Tue Dec 29 16:30:53 2020
|
||||||
// Host : cxz666 running 64-bit major release (build 9200)
|
// Host : cxz666 running 64-bit major release (build 9200)
|
||||||
// Command : write_verilog -force -mode funcsim
|
// Command : write_verilog -force -mode funcsim -rename_top bullet_left_img -prefix
|
||||||
// E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/bullet_left_img/bullet_left_img_sim_netlist.v
|
// bullet_left_img_ bullet_left_img_sim_netlist.v
|
||||||
// Design : bullet_left_img
|
// Design : bullet_left_img
|
||||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
|
@ -191,7 +191,6 @@ module bullet_left_img
|
||||||
.web(1'b0));
|
.web(1'b0));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
|
|
||||||
module bullet_left_img_blk_mem_gen_generic_cstr
|
module bullet_left_img_blk_mem_gen_generic_cstr
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -214,7 +213,6 @@ module bullet_left_img_blk_mem_gen_generic_cstr
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
|
|
||||||
module bullet_left_img_blk_mem_gen_prim_width
|
module bullet_left_img_blk_mem_gen_prim_width
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -237,7 +235,6 @@ module bullet_left_img_blk_mem_gen_prim_width
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
|
|
||||||
module bullet_left_img_blk_mem_gen_prim_wrapper_init
|
module bullet_left_img_blk_mem_gen_prim_wrapper_init
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -403,7 +400,6 @@ module bullet_left_img_blk_mem_gen_prim_wrapper_init
|
||||||
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
|
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
|
|
||||||
module bullet_left_img_blk_mem_gen_top
|
module bullet_left_img_blk_mem_gen_top
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -451,7 +447,7 @@ endmodule
|
||||||
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "50" *)
|
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "50" *)
|
||||||
(* C_WRITE_DEPTH_B = "50" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
(* C_WRITE_DEPTH_B = "50" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
||||||
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
|
(* downgradeipidentifiedwarnings = "yes" *)
|
||||||
module bullet_left_img_blk_mem_gen_v8_4_4
|
module bullet_left_img_blk_mem_gen_v8_4_4
|
||||||
(clka,
|
(clka,
|
||||||
rsta,
|
rsta,
|
||||||
|
|
@ -655,7 +651,6 @@ module bullet_left_img_blk_mem_gen_v8_4_4
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
|
|
||||||
module bullet_left_img_blk_mem_gen_v8_4_4_synth
|
module bullet_left_img_blk_mem_gen_v8_4_4_synth
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
|
||||||
|
|
@ -1,10 +1,10 @@
|
||||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
||||||
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
-- Date : Tue Dec 29 16:30:54 2020
|
-- Date : Tue Dec 29 16:30:53 2020
|
||||||
-- Host : cxz666 running 64-bit major release (build 9200)
|
-- Host : cxz666 running 64-bit major release (build 9200)
|
||||||
-- Command : write_vhdl -force -mode funcsim
|
-- Command : write_vhdl -force -mode funcsim -rename_top bullet_left_img -prefix
|
||||||
-- E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/bullet_left_img/bullet_left_img_sim_netlist.vhdl
|
-- bullet_left_img_ bullet_left_img_sim_netlist.vhdl
|
||||||
-- Design : bullet_left_img
|
-- Design : bullet_left_img
|
||||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
|
@ -21,8 +21,6 @@ entity bullet_left_img_blk_mem_gen_prim_wrapper_init is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_left_img_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
|
|
||||||
end bullet_left_img_blk_mem_gen_prim_wrapper_init;
|
end bullet_left_img_blk_mem_gen_prim_wrapper_init;
|
||||||
|
|
||||||
architecture STRUCTURE of bullet_left_img_blk_mem_gen_prim_wrapper_init is
|
architecture STRUCTURE of bullet_left_img_blk_mem_gen_prim_wrapper_init is
|
||||||
|
|
@ -219,8 +217,6 @@ entity bullet_left_img_blk_mem_gen_prim_width is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_left_img_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
|
|
||||||
end bullet_left_img_blk_mem_gen_prim_width;
|
end bullet_left_img_blk_mem_gen_prim_width;
|
||||||
|
|
||||||
architecture STRUCTURE of bullet_left_img_blk_mem_gen_prim_width is
|
architecture STRUCTURE of bullet_left_img_blk_mem_gen_prim_width is
|
||||||
|
|
@ -244,8 +240,6 @@ entity bullet_left_img_blk_mem_gen_generic_cstr is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_left_img_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
|
|
||||||
end bullet_left_img_blk_mem_gen_generic_cstr;
|
end bullet_left_img_blk_mem_gen_generic_cstr;
|
||||||
|
|
||||||
architecture STRUCTURE of bullet_left_img_blk_mem_gen_generic_cstr is
|
architecture STRUCTURE of bullet_left_img_blk_mem_gen_generic_cstr is
|
||||||
|
|
@ -269,8 +263,6 @@ entity bullet_left_img_blk_mem_gen_top is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_left_img_blk_mem_gen_top : entity is "blk_mem_gen_top";
|
|
||||||
end bullet_left_img_blk_mem_gen_top;
|
end bullet_left_img_blk_mem_gen_top;
|
||||||
|
|
||||||
architecture STRUCTURE of bullet_left_img_blk_mem_gen_top is
|
architecture STRUCTURE of bullet_left_img_blk_mem_gen_top is
|
||||||
|
|
@ -294,8 +286,6 @@ entity bullet_left_img_blk_mem_gen_v8_4_4_synth is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_left_img_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
|
|
||||||
end bullet_left_img_blk_mem_gen_v8_4_4_synth;
|
end bullet_left_img_blk_mem_gen_v8_4_4_synth;
|
||||||
|
|
||||||
architecture STRUCTURE of bullet_left_img_blk_mem_gen_v8_4_4_synth is
|
architecture STRUCTURE of bullet_left_img_blk_mem_gen_v8_4_4_synth is
|
||||||
|
|
@ -528,8 +518,6 @@ entity bullet_left_img_blk_mem_gen_v8_4_4 is
|
||||||
attribute C_WRITE_WIDTH_B of bullet_left_img_blk_mem_gen_v8_4_4 : entity is 12;
|
attribute C_WRITE_WIDTH_B of bullet_left_img_blk_mem_gen_v8_4_4 : entity is 12;
|
||||||
attribute C_XDEVICEFAMILY : string;
|
attribute C_XDEVICEFAMILY : string;
|
||||||
attribute C_XDEVICEFAMILY of bullet_left_img_blk_mem_gen_v8_4_4 : entity is "artix7";
|
attribute C_XDEVICEFAMILY of bullet_left_img_blk_mem_gen_v8_4_4 : entity is "artix7";
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_left_img_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
|
|
||||||
attribute downgradeipidentifiedwarnings : string;
|
attribute downgradeipidentifiedwarnings : string;
|
||||||
attribute downgradeipidentifiedwarnings of bullet_left_img_blk_mem_gen_v8_4_4 : entity is "yes";
|
attribute downgradeipidentifiedwarnings of bullet_left_img_blk_mem_gen_v8_4_4 : entity is "yes";
|
||||||
end bullet_left_img_blk_mem_gen_v8_4_4;
|
end bullet_left_img_blk_mem_gen_v8_4_4;
|
||||||
|
|
|
||||||
|
|
@ -1552,11 +1552,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:26:42 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:39:54 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:b1718657</spirit:value>
|
<spirit:value>9:7a24a24f</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1567,7 +1567,7 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:b1718657</spirit:value>
|
<spirit:value>9:7a24a24f</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1583,11 +1583,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:26:42 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:39:54 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:b1718657</spirit:value>
|
<spirit:value>9:7a24a24f</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1601,11 +1601,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:30:54 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:40:33 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:b1718657</spirit:value>
|
<spirit:value>9:7a24a24f</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
|
||||||
|
|
@ -1,10 +1,10 @@
|
||||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
// --------------------------------------------------------------------------------
|
// --------------------------------------------------------------------------------
|
||||||
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
// Date : Tue Dec 29 16:30:54 2020
|
// Date : Tue Dec 29 16:30:53 2020
|
||||||
// Host : cxz666 running 64-bit major release (build 9200)
|
// Host : cxz666 running 64-bit major release (build 9200)
|
||||||
// Command : write_verilog -force -mode funcsim
|
// Command : write_verilog -force -mode funcsim -rename_top bullet_right_img -prefix
|
||||||
// E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/bullet_right_img/bullet_right_img_sim_netlist.v
|
// bullet_right_img_ bullet_right_img_sim_netlist.v
|
||||||
// Design : bullet_right_img
|
// Design : bullet_right_img
|
||||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
|
@ -191,7 +191,6 @@ module bullet_right_img
|
||||||
.web(1'b0));
|
.web(1'b0));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
|
|
||||||
module bullet_right_img_blk_mem_gen_generic_cstr
|
module bullet_right_img_blk_mem_gen_generic_cstr
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -214,7 +213,6 @@ module bullet_right_img_blk_mem_gen_generic_cstr
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
|
|
||||||
module bullet_right_img_blk_mem_gen_prim_width
|
module bullet_right_img_blk_mem_gen_prim_width
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -237,7 +235,6 @@ module bullet_right_img_blk_mem_gen_prim_width
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
|
|
||||||
module bullet_right_img_blk_mem_gen_prim_wrapper_init
|
module bullet_right_img_blk_mem_gen_prim_wrapper_init
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -403,7 +400,6 @@ module bullet_right_img_blk_mem_gen_prim_wrapper_init
|
||||||
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
|
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
|
|
||||||
module bullet_right_img_blk_mem_gen_top
|
module bullet_right_img_blk_mem_gen_top
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -451,7 +447,7 @@ endmodule
|
||||||
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "50" *)
|
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "50" *)
|
||||||
(* C_WRITE_DEPTH_B = "50" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
(* C_WRITE_DEPTH_B = "50" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
||||||
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
|
(* downgradeipidentifiedwarnings = "yes" *)
|
||||||
module bullet_right_img_blk_mem_gen_v8_4_4
|
module bullet_right_img_blk_mem_gen_v8_4_4
|
||||||
(clka,
|
(clka,
|
||||||
rsta,
|
rsta,
|
||||||
|
|
@ -655,7 +651,6 @@ module bullet_right_img_blk_mem_gen_v8_4_4
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
|
|
||||||
module bullet_right_img_blk_mem_gen_v8_4_4_synth
|
module bullet_right_img_blk_mem_gen_v8_4_4_synth
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
|
||||||
|
|
@ -1,10 +1,10 @@
|
||||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
||||||
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
-- Date : Tue Dec 29 16:30:54 2020
|
-- Date : Tue Dec 29 16:30:53 2020
|
||||||
-- Host : cxz666 running 64-bit major release (build 9200)
|
-- Host : cxz666 running 64-bit major release (build 9200)
|
||||||
-- Command : write_vhdl -force -mode funcsim
|
-- Command : write_vhdl -force -mode funcsim -rename_top bullet_right_img -prefix
|
||||||
-- E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/bullet_right_img/bullet_right_img_sim_netlist.vhdl
|
-- bullet_right_img_ bullet_right_img_sim_netlist.vhdl
|
||||||
-- Design : bullet_right_img
|
-- Design : bullet_right_img
|
||||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
|
@ -21,8 +21,6 @@ entity bullet_right_img_blk_mem_gen_prim_wrapper_init is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_right_img_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
|
|
||||||
end bullet_right_img_blk_mem_gen_prim_wrapper_init;
|
end bullet_right_img_blk_mem_gen_prim_wrapper_init;
|
||||||
|
|
||||||
architecture STRUCTURE of bullet_right_img_blk_mem_gen_prim_wrapper_init is
|
architecture STRUCTURE of bullet_right_img_blk_mem_gen_prim_wrapper_init is
|
||||||
|
|
@ -219,8 +217,6 @@ entity bullet_right_img_blk_mem_gen_prim_width is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_right_img_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
|
|
||||||
end bullet_right_img_blk_mem_gen_prim_width;
|
end bullet_right_img_blk_mem_gen_prim_width;
|
||||||
|
|
||||||
architecture STRUCTURE of bullet_right_img_blk_mem_gen_prim_width is
|
architecture STRUCTURE of bullet_right_img_blk_mem_gen_prim_width is
|
||||||
|
|
@ -244,8 +240,6 @@ entity bullet_right_img_blk_mem_gen_generic_cstr is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_right_img_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
|
|
||||||
end bullet_right_img_blk_mem_gen_generic_cstr;
|
end bullet_right_img_blk_mem_gen_generic_cstr;
|
||||||
|
|
||||||
architecture STRUCTURE of bullet_right_img_blk_mem_gen_generic_cstr is
|
architecture STRUCTURE of bullet_right_img_blk_mem_gen_generic_cstr is
|
||||||
|
|
@ -269,8 +263,6 @@ entity bullet_right_img_blk_mem_gen_top is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_right_img_blk_mem_gen_top : entity is "blk_mem_gen_top";
|
|
||||||
end bullet_right_img_blk_mem_gen_top;
|
end bullet_right_img_blk_mem_gen_top;
|
||||||
|
|
||||||
architecture STRUCTURE of bullet_right_img_blk_mem_gen_top is
|
architecture STRUCTURE of bullet_right_img_blk_mem_gen_top is
|
||||||
|
|
@ -294,8 +286,6 @@ entity bullet_right_img_blk_mem_gen_v8_4_4_synth is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_right_img_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
|
|
||||||
end bullet_right_img_blk_mem_gen_v8_4_4_synth;
|
end bullet_right_img_blk_mem_gen_v8_4_4_synth;
|
||||||
|
|
||||||
architecture STRUCTURE of bullet_right_img_blk_mem_gen_v8_4_4_synth is
|
architecture STRUCTURE of bullet_right_img_blk_mem_gen_v8_4_4_synth is
|
||||||
|
|
@ -528,8 +518,6 @@ entity bullet_right_img_blk_mem_gen_v8_4_4 is
|
||||||
attribute C_WRITE_WIDTH_B of bullet_right_img_blk_mem_gen_v8_4_4 : entity is 12;
|
attribute C_WRITE_WIDTH_B of bullet_right_img_blk_mem_gen_v8_4_4 : entity is 12;
|
||||||
attribute C_XDEVICEFAMILY : string;
|
attribute C_XDEVICEFAMILY : string;
|
||||||
attribute C_XDEVICEFAMILY of bullet_right_img_blk_mem_gen_v8_4_4 : entity is "artix7";
|
attribute C_XDEVICEFAMILY of bullet_right_img_blk_mem_gen_v8_4_4 : entity is "artix7";
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_right_img_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
|
|
||||||
attribute downgradeipidentifiedwarnings : string;
|
attribute downgradeipidentifiedwarnings : string;
|
||||||
attribute downgradeipidentifiedwarnings of bullet_right_img_blk_mem_gen_v8_4_4 : entity is "yes";
|
attribute downgradeipidentifiedwarnings of bullet_right_img_blk_mem_gen_v8_4_4 : entity is "yes";
|
||||||
end bullet_right_img_blk_mem_gen_v8_4_4;
|
end bullet_right_img_blk_mem_gen_v8_4_4;
|
||||||
|
|
|
||||||
|
|
@ -1552,11 +1552,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:26:40 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:39:53 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:85938ef0</spirit:value>
|
<spirit:value>9:7100886c</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1567,7 +1567,7 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:85938ef0</spirit:value>
|
<spirit:value>9:7100886c</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1583,11 +1583,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:26:40 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:39:53 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:85938ef0</spirit:value>
|
<spirit:value>9:7100886c</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1601,11 +1601,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:30:53 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:40:32 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:85938ef0</spirit:value>
|
<spirit:value>9:7100886c</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
|
||||||
|
|
@ -1,10 +1,10 @@
|
||||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
// --------------------------------------------------------------------------------
|
// --------------------------------------------------------------------------------
|
||||||
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
// Date : Tue Dec 29 16:30:53 2020
|
// Date : Tue Dec 29 16:30:52 2020
|
||||||
// Host : cxz666 running 64-bit major release (build 9200)
|
// Host : cxz666 running 64-bit major release (build 9200)
|
||||||
// Command : write_verilog -force -mode funcsim
|
// Command : write_verilog -force -mode funcsim -rename_top bullet_up_img -prefix
|
||||||
// E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/bullet_up_img/bullet_up_img_sim_netlist.v
|
// bullet_up_img_ bullet_up_img_sim_netlist.v
|
||||||
// Design : bullet_up_img
|
// Design : bullet_up_img
|
||||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
|
@ -191,7 +191,6 @@ module bullet_up_img
|
||||||
.web(1'b0));
|
.web(1'b0));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
|
|
||||||
module bullet_up_img_blk_mem_gen_generic_cstr
|
module bullet_up_img_blk_mem_gen_generic_cstr
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -214,7 +213,6 @@ module bullet_up_img_blk_mem_gen_generic_cstr
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
|
|
||||||
module bullet_up_img_blk_mem_gen_prim_width
|
module bullet_up_img_blk_mem_gen_prim_width
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -237,7 +235,6 @@ module bullet_up_img_blk_mem_gen_prim_width
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
|
|
||||||
module bullet_up_img_blk_mem_gen_prim_wrapper_init
|
module bullet_up_img_blk_mem_gen_prim_wrapper_init
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -403,7 +400,6 @@ module bullet_up_img_blk_mem_gen_prim_wrapper_init
|
||||||
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
|
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
|
|
||||||
module bullet_up_img_blk_mem_gen_top
|
module bullet_up_img_blk_mem_gen_top
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -451,7 +447,7 @@ endmodule
|
||||||
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "50" *)
|
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "50" *)
|
||||||
(* C_WRITE_DEPTH_B = "50" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
(* C_WRITE_DEPTH_B = "50" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
||||||
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
|
(* downgradeipidentifiedwarnings = "yes" *)
|
||||||
module bullet_up_img_blk_mem_gen_v8_4_4
|
module bullet_up_img_blk_mem_gen_v8_4_4
|
||||||
(clka,
|
(clka,
|
||||||
rsta,
|
rsta,
|
||||||
|
|
@ -655,7 +651,6 @@ module bullet_up_img_blk_mem_gen_v8_4_4
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
|
|
||||||
module bullet_up_img_blk_mem_gen_v8_4_4_synth
|
module bullet_up_img_blk_mem_gen_v8_4_4_synth
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
|
||||||
|
|
@ -1,10 +1,10 @@
|
||||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
||||||
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
-- Date : Tue Dec 29 16:30:53 2020
|
-- Date : Tue Dec 29 16:30:52 2020
|
||||||
-- Host : cxz666 running 64-bit major release (build 9200)
|
-- Host : cxz666 running 64-bit major release (build 9200)
|
||||||
-- Command : write_vhdl -force -mode funcsim
|
-- Command : write_vhdl -force -mode funcsim -rename_top bullet_up_img -prefix
|
||||||
-- E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/bullet_up_img/bullet_up_img_sim_netlist.vhdl
|
-- bullet_up_img_ bullet_up_img_sim_netlist.vhdl
|
||||||
-- Design : bullet_up_img
|
-- Design : bullet_up_img
|
||||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
|
@ -21,8 +21,6 @@ entity bullet_up_img_blk_mem_gen_prim_wrapper_init is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_up_img_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
|
|
||||||
end bullet_up_img_blk_mem_gen_prim_wrapper_init;
|
end bullet_up_img_blk_mem_gen_prim_wrapper_init;
|
||||||
|
|
||||||
architecture STRUCTURE of bullet_up_img_blk_mem_gen_prim_wrapper_init is
|
architecture STRUCTURE of bullet_up_img_blk_mem_gen_prim_wrapper_init is
|
||||||
|
|
@ -219,8 +217,6 @@ entity bullet_up_img_blk_mem_gen_prim_width is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_up_img_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
|
|
||||||
end bullet_up_img_blk_mem_gen_prim_width;
|
end bullet_up_img_blk_mem_gen_prim_width;
|
||||||
|
|
||||||
architecture STRUCTURE of bullet_up_img_blk_mem_gen_prim_width is
|
architecture STRUCTURE of bullet_up_img_blk_mem_gen_prim_width is
|
||||||
|
|
@ -244,8 +240,6 @@ entity bullet_up_img_blk_mem_gen_generic_cstr is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_up_img_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
|
|
||||||
end bullet_up_img_blk_mem_gen_generic_cstr;
|
end bullet_up_img_blk_mem_gen_generic_cstr;
|
||||||
|
|
||||||
architecture STRUCTURE of bullet_up_img_blk_mem_gen_generic_cstr is
|
architecture STRUCTURE of bullet_up_img_blk_mem_gen_generic_cstr is
|
||||||
|
|
@ -269,8 +263,6 @@ entity bullet_up_img_blk_mem_gen_top is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_up_img_blk_mem_gen_top : entity is "blk_mem_gen_top";
|
|
||||||
end bullet_up_img_blk_mem_gen_top;
|
end bullet_up_img_blk_mem_gen_top;
|
||||||
|
|
||||||
architecture STRUCTURE of bullet_up_img_blk_mem_gen_top is
|
architecture STRUCTURE of bullet_up_img_blk_mem_gen_top is
|
||||||
|
|
@ -294,8 +286,6 @@ entity bullet_up_img_blk_mem_gen_v8_4_4_synth is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_up_img_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
|
|
||||||
end bullet_up_img_blk_mem_gen_v8_4_4_synth;
|
end bullet_up_img_blk_mem_gen_v8_4_4_synth;
|
||||||
|
|
||||||
architecture STRUCTURE of bullet_up_img_blk_mem_gen_v8_4_4_synth is
|
architecture STRUCTURE of bullet_up_img_blk_mem_gen_v8_4_4_synth is
|
||||||
|
|
@ -528,8 +518,6 @@ entity bullet_up_img_blk_mem_gen_v8_4_4 is
|
||||||
attribute C_WRITE_WIDTH_B of bullet_up_img_blk_mem_gen_v8_4_4 : entity is 12;
|
attribute C_WRITE_WIDTH_B of bullet_up_img_blk_mem_gen_v8_4_4 : entity is 12;
|
||||||
attribute C_XDEVICEFAMILY : string;
|
attribute C_XDEVICEFAMILY : string;
|
||||||
attribute C_XDEVICEFAMILY of bullet_up_img_blk_mem_gen_v8_4_4 : entity is "artix7";
|
attribute C_XDEVICEFAMILY of bullet_up_img_blk_mem_gen_v8_4_4 : entity is "artix7";
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of bullet_up_img_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
|
|
||||||
attribute downgradeipidentifiedwarnings : string;
|
attribute downgradeipidentifiedwarnings : string;
|
||||||
attribute downgradeipidentifiedwarnings of bullet_up_img_blk_mem_gen_v8_4_4 : entity is "yes";
|
attribute downgradeipidentifiedwarnings of bullet_up_img_blk_mem_gen_v8_4_4 : entity is "yes";
|
||||||
end bullet_up_img_blk_mem_gen_v8_4_4;
|
end bullet_up_img_blk_mem_gen_v8_4_4;
|
||||||
|
|
|
||||||
|
|
@ -1465,57 +1465,6 @@
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
<spirit:view>
|
|
||||||
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
|
|
||||||
<spirit:displayName>VHDL Synthesis</spirit:displayName>
|
|
||||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
|
||||||
<spirit:language>vhdl</spirit:language>
|
|
||||||
<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
|
|
||||||
<spirit:fileSetRef>
|
|
||||||
<spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
|
|
||||||
</spirit:fileSetRef>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
|
||||||
<spirit:value>Tue Dec 29 12:18:03 UTC 2020</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
|
||||||
<spirit:value>9:a566edfa</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:view>
|
|
||||||
<spirit:view>
|
|
||||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
|
||||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
|
||||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
|
||||||
<spirit:value>9:a566edfa</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:view>
|
|
||||||
<spirit:view>
|
|
||||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
|
||||||
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
|
||||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
|
||||||
<spirit:language>vhdl</spirit:language>
|
|
||||||
<spirit:modelName>gameover_380_180</spirit:modelName>
|
|
||||||
<spirit:fileSetRef>
|
|
||||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
|
||||||
</spirit:fileSetRef>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
|
||||||
<spirit:value>Tue Dec 29 12:18:03 UTC 2020</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
|
||||||
<spirit:value>9:a566edfa</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:view>
|
|
||||||
<spirit:view>
|
<spirit:view>
|
||||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||||
<spirit:displayName>Simulation</spirit:displayName>
|
<spirit:displayName>Simulation</spirit:displayName>
|
||||||
|
|
@ -1591,6 +1540,57 @@
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
<spirit:view>
|
||||||
|
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
|
||||||
|
<spirit:displayName>VHDL Synthesis</spirit:displayName>
|
||||||
|
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||||
|
<spirit:language>vhdl</spirit:language>
|
||||||
|
<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
|
||||||
|
<spirit:fileSetRef>
|
||||||
|
<spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
|
||||||
|
</spirit:fileSetRef>
|
||||||
|
<spirit:parameters>
|
||||||
|
<spirit:parameter>
|
||||||
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
|
<spirit:value>Wed Dec 30 00:40:02 UTC 2020</spirit:value>
|
||||||
|
</spirit:parameter>
|
||||||
|
<spirit:parameter>
|
||||||
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
|
<spirit:value>9:c54f3c26</spirit:value>
|
||||||
|
</spirit:parameter>
|
||||||
|
</spirit:parameters>
|
||||||
|
</spirit:view>
|
||||||
|
<spirit:view>
|
||||||
|
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||||
|
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||||
|
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||||
|
<spirit:parameters>
|
||||||
|
<spirit:parameter>
|
||||||
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
|
<spirit:value>9:c54f3c26</spirit:value>
|
||||||
|
</spirit:parameter>
|
||||||
|
</spirit:parameters>
|
||||||
|
</spirit:view>
|
||||||
|
<spirit:view>
|
||||||
|
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
||||||
|
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
||||||
|
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||||
|
<spirit:language>vhdl</spirit:language>
|
||||||
|
<spirit:modelName>gameover_380_180</spirit:modelName>
|
||||||
|
<spirit:fileSetRef>
|
||||||
|
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
||||||
|
</spirit:fileSetRef>
|
||||||
|
<spirit:parameters>
|
||||||
|
<spirit:parameter>
|
||||||
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
|
<spirit:value>Wed Dec 30 00:40:02 UTC 2020</spirit:value>
|
||||||
|
</spirit:parameter>
|
||||||
|
<spirit:parameter>
|
||||||
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
|
<spirit:value>9:c54f3c26</spirit:value>
|
||||||
|
</spirit:parameter>
|
||||||
|
</spirit:parameters>
|
||||||
|
</spirit:view>
|
||||||
<spirit:view>
|
<spirit:view>
|
||||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||||
<spirit:displayName>External Files</spirit:displayName>
|
<spirit:displayName>External Files</spirit:displayName>
|
||||||
|
|
@ -1601,11 +1601,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 12:20:02 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:40:43 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:a566edfa</spirit:value>
|
<spirit:value>9:c54f3c26</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -3549,33 +3549,6 @@
|
||||||
<spirit:userFileType>verilogTemplate</spirit:userFileType>
|
<spirit:userFileType>verilogTemplate</spirit:userFileType>
|
||||||
</spirit:file>
|
</spirit:file>
|
||||||
</spirit:fileSet>
|
</spirit:fileSet>
|
||||||
<spirit:fileSet>
|
|
||||||
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>gameover_380_180_ooc.xdc</spirit:name>
|
|
||||||
<spirit:userFileType>xdc</spirit:userFileType>
|
|
||||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
|
||||||
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
|
||||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
|
||||||
</spirit:file>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>gameover_380_180.mif</spirit:name>
|
|
||||||
<spirit:userFileType>mif</spirit:userFileType>
|
|
||||||
</spirit:file>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd</spirit:name>
|
|
||||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
||||||
<spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
|
|
||||||
</spirit:file>
|
|
||||||
</spirit:fileSet>
|
|
||||||
<spirit:fileSet>
|
|
||||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>synth/gameover_380_180.vhd</spirit:name>
|
|
||||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
||||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
|
||||||
</spirit:file>
|
|
||||||
</spirit:fileSet>
|
|
||||||
<spirit:fileSet>
|
<spirit:fileSet>
|
||||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||||
<spirit:file>
|
<spirit:file>
|
||||||
|
|
@ -3616,6 +3589,33 @@
|
||||||
<spirit:userFileType>text</spirit:userFileType>
|
<spirit:userFileType>text</spirit:userFileType>
|
||||||
</spirit:file>
|
</spirit:file>
|
||||||
</spirit:fileSet>
|
</spirit:fileSet>
|
||||||
|
<spirit:fileSet>
|
||||||
|
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
|
||||||
|
<spirit:file>
|
||||||
|
<spirit:name>gameover_380_180_ooc.xdc</spirit:name>
|
||||||
|
<spirit:userFileType>xdc</spirit:userFileType>
|
||||||
|
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||||
|
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
||||||
|
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||||
|
</spirit:file>
|
||||||
|
<spirit:file>
|
||||||
|
<spirit:name>gameover_380_180.mif</spirit:name>
|
||||||
|
<spirit:userFileType>mif</spirit:userFileType>
|
||||||
|
</spirit:file>
|
||||||
|
<spirit:file>
|
||||||
|
<spirit:name>hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd</spirit:name>
|
||||||
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||||
|
<spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
|
||||||
|
</spirit:file>
|
||||||
|
</spirit:fileSet>
|
||||||
|
<spirit:fileSet>
|
||||||
|
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||||
|
<spirit:file>
|
||||||
|
<spirit:name>synth/gameover_380_180.vhd</spirit:name>
|
||||||
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||||
|
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||||
|
</spirit:file>
|
||||||
|
</spirit:fileSet>
|
||||||
<spirit:fileSet>
|
<spirit:fileSet>
|
||||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||||
<spirit:file>
|
<spirit:file>
|
||||||
|
|
|
||||||
|
|
@ -1,10 +1,10 @@
|
||||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
// --------------------------------------------------------------------------------
|
// --------------------------------------------------------------------------------
|
||||||
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
// Date : Tue Dec 29 20:20:02 2020
|
// Date : Tue Dec 29 20:20:01 2020
|
||||||
// Host : cxz666 running 64-bit major release (build 9200)
|
// Host : cxz666 running 64-bit major release (build 9200)
|
||||||
// Command : write_verilog -force -mode funcsim
|
// Command : write_verilog -force -mode funcsim -rename_top gameover_380_180 -prefix
|
||||||
// e:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/gameover_380_180/gameover_380_180_sim_netlist.v
|
// gameover_380_180_ gameover_380_180_sim_netlist.v
|
||||||
// Design : gameover_380_180
|
// Design : gameover_380_180
|
||||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
|
@ -191,7 +191,6 @@ module gameover_380_180
|
||||||
.web(1'b0));
|
.web(1'b0));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "bindec" *)
|
|
||||||
module gameover_380_180_bindec
|
module gameover_380_180_bindec
|
||||||
(ena_array,
|
(ena_array,
|
||||||
addra,
|
addra,
|
||||||
|
|
@ -376,7 +375,6 @@ module gameover_380_180_bindec
|
||||||
.O(ena_array[10]));
|
.O(ena_array[10]));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
|
|
||||||
module gameover_380_180_blk_mem_gen_generic_cstr
|
module gameover_380_180_blk_mem_gen_generic_cstr
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -766,7 +764,6 @@ module gameover_380_180_blk_mem_gen_generic_cstr
|
||||||
.ena_array(ena_array[4]));
|
.ena_array(ena_array[4]));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_mux" *)
|
|
||||||
module gameover_380_180_blk_mem_gen_mux
|
module gameover_380_180_blk_mem_gen_mux
|
||||||
(douta,
|
(douta,
|
||||||
DOADO,
|
DOADO,
|
||||||
|
|
@ -1687,7 +1684,6 @@ module gameover_380_180_blk_mem_gen_mux
|
||||||
.R(1'b0));
|
.R(1'b0));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
|
|
||||||
module gameover_380_180_blk_mem_gen_prim_width
|
module gameover_380_180_blk_mem_gen_prim_width
|
||||||
(DOUTA,
|
(DOUTA,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -2345,7 +2341,6 @@ module gameover_380_180_blk_mem_gen_prim_width__parameterized9
|
||||||
.ena_array(ena_array));
|
.ena_array(ena_array));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
|
|
||||||
module gameover_380_180_blk_mem_gen_prim_wrapper_init
|
module gameover_380_180_blk_mem_gen_prim_wrapper_init
|
||||||
(DOUTA,
|
(DOUTA,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -8181,7 +8176,6 @@ module gameover_380_180_blk_mem_gen_prim_wrapper_init__parameterized9
|
||||||
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
|
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
|
|
||||||
module gameover_380_180_blk_mem_gen_top
|
module gameover_380_180_blk_mem_gen_top
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -8229,7 +8223,7 @@ endmodule
|
||||||
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "68400" *)
|
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "68400" *)
|
||||||
(* C_WRITE_DEPTH_B = "68400" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
(* C_WRITE_DEPTH_B = "68400" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
||||||
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
|
(* downgradeipidentifiedwarnings = "yes" *)
|
||||||
module gameover_380_180_blk_mem_gen_v8_4_4
|
module gameover_380_180_blk_mem_gen_v8_4_4
|
||||||
(clka,
|
(clka,
|
||||||
rsta,
|
rsta,
|
||||||
|
|
@ -8455,7 +8449,6 @@ module gameover_380_180_blk_mem_gen_v8_4_4
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
|
|
||||||
module gameover_380_180_blk_mem_gen_v8_4_4_synth
|
module gameover_380_180_blk_mem_gen_v8_4_4_synth
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
|
||||||
|
|
@ -1,10 +1,10 @@
|
||||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
||||||
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
-- Date : Tue Dec 29 20:20:02 2020
|
-- Date : Tue Dec 29 20:20:01 2020
|
||||||
-- Host : cxz666 running 64-bit major release (build 9200)
|
-- Host : cxz666 running 64-bit major release (build 9200)
|
||||||
-- Command : write_vhdl -force -mode funcsim
|
-- Command : write_vhdl -force -mode funcsim -rename_top gameover_380_180 -prefix
|
||||||
-- e:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/gameover_380_180/gameover_380_180_sim_netlist.vhdl
|
-- gameover_380_180_ gameover_380_180_sim_netlist.vhdl
|
||||||
-- Design : gameover_380_180
|
-- Design : gameover_380_180
|
||||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
|
@ -20,8 +20,6 @@ entity gameover_380_180_bindec is
|
||||||
addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
|
addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
|
||||||
ena : in STD_LOGIC
|
ena : in STD_LOGIC
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of gameover_380_180_bindec : entity is "bindec";
|
|
||||||
end gameover_380_180_bindec;
|
end gameover_380_180_bindec;
|
||||||
|
|
||||||
architecture STRUCTURE of gameover_380_180_bindec is
|
architecture STRUCTURE of gameover_380_180_bindec is
|
||||||
|
|
@ -298,8 +296,6 @@ entity gameover_380_180_blk_mem_gen_mux is
|
||||||
\douta[11]_INST_0_i_2_6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
|
\douta[11]_INST_0_i_2_6\ : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
\douta[11]_INST_0_i_2_7\ : in STD_LOGIC_VECTOR ( 0 to 0 )
|
\douta[11]_INST_0_i_2_7\ : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
|
|
||||||
end gameover_380_180_blk_mem_gen_mux;
|
end gameover_380_180_blk_mem_gen_mux;
|
||||||
|
|
||||||
architecture STRUCTURE of gameover_380_180_blk_mem_gen_mux is
|
architecture STRUCTURE of gameover_380_180_blk_mem_gen_mux is
|
||||||
|
|
@ -1340,8 +1336,6 @@ entity gameover_380_180_blk_mem_gen_prim_wrapper_init is
|
||||||
\^ena\ : in STD_LOGIC;
|
\^ena\ : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
|
|
||||||
end gameover_380_180_blk_mem_gen_prim_wrapper_init;
|
end gameover_380_180_blk_mem_gen_prim_wrapper_init;
|
||||||
|
|
||||||
architecture STRUCTURE of gameover_380_180_blk_mem_gen_prim_wrapper_init is
|
architecture STRUCTURE of gameover_380_180_blk_mem_gen_prim_wrapper_init is
|
||||||
|
|
@ -7274,8 +7268,6 @@ entity gameover_380_180_blk_mem_gen_prim_width is
|
||||||
\^ena\ : in STD_LOGIC;
|
\^ena\ : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
|
|
||||||
end gameover_380_180_blk_mem_gen_prim_width;
|
end gameover_380_180_blk_mem_gen_prim_width;
|
||||||
|
|
||||||
architecture STRUCTURE of gameover_380_180_blk_mem_gen_prim_width is
|
architecture STRUCTURE of gameover_380_180_blk_mem_gen_prim_width is
|
||||||
|
|
@ -7899,8 +7891,6 @@ entity gameover_380_180_blk_mem_gen_generic_cstr is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
|
|
||||||
end gameover_380_180_blk_mem_gen_generic_cstr;
|
end gameover_380_180_blk_mem_gen_generic_cstr;
|
||||||
|
|
||||||
architecture STRUCTURE of gameover_380_180_blk_mem_gen_generic_cstr is
|
architecture STRUCTURE of gameover_380_180_blk_mem_gen_generic_cstr is
|
||||||
|
|
@ -8583,8 +8573,6 @@ entity gameover_380_180_blk_mem_gen_top is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_top : entity is "blk_mem_gen_top";
|
|
||||||
end gameover_380_180_blk_mem_gen_top;
|
end gameover_380_180_blk_mem_gen_top;
|
||||||
|
|
||||||
architecture STRUCTURE of gameover_380_180_blk_mem_gen_top is
|
architecture STRUCTURE of gameover_380_180_blk_mem_gen_top is
|
||||||
|
|
@ -8608,8 +8596,6 @@ entity gameover_380_180_blk_mem_gen_v8_4_4_synth is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
|
|
||||||
end gameover_380_180_blk_mem_gen_v8_4_4_synth;
|
end gameover_380_180_blk_mem_gen_v8_4_4_synth;
|
||||||
|
|
||||||
architecture STRUCTURE of gameover_380_180_blk_mem_gen_v8_4_4_synth is
|
architecture STRUCTURE of gameover_380_180_blk_mem_gen_v8_4_4_synth is
|
||||||
|
|
@ -8842,8 +8828,6 @@ entity gameover_380_180_blk_mem_gen_v8_4_4 is
|
||||||
attribute C_WRITE_WIDTH_B of gameover_380_180_blk_mem_gen_v8_4_4 : entity is 12;
|
attribute C_WRITE_WIDTH_B of gameover_380_180_blk_mem_gen_v8_4_4 : entity is 12;
|
||||||
attribute C_XDEVICEFAMILY : string;
|
attribute C_XDEVICEFAMILY : string;
|
||||||
attribute C_XDEVICEFAMILY of gameover_380_180_blk_mem_gen_v8_4_4 : entity is "artix7";
|
attribute C_XDEVICEFAMILY of gameover_380_180_blk_mem_gen_v8_4_4 : entity is "artix7";
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of gameover_380_180_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
|
|
||||||
attribute downgradeipidentifiedwarnings : string;
|
attribute downgradeipidentifiedwarnings : string;
|
||||||
attribute downgradeipidentifiedwarnings of gameover_380_180_blk_mem_gen_v8_4_4 : entity is "yes";
|
attribute downgradeipidentifiedwarnings of gameover_380_180_blk_mem_gen_v8_4_4 : entity is "yes";
|
||||||
end gameover_380_180_blk_mem_gen_v8_4_4;
|
end gameover_380_180_blk_mem_gen_v8_4_4;
|
||||||
|
|
|
||||||
|
|
@ -1465,57 +1465,6 @@
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
<spirit:view>
|
|
||||||
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
|
|
||||||
<spirit:displayName>VHDL Synthesis</spirit:displayName>
|
|
||||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
|
||||||
<spirit:language>vhdl</spirit:language>
|
|
||||||
<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
|
|
||||||
<spirit:fileSetRef>
|
|
||||||
<spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
|
|
||||||
</spirit:fileSetRef>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
|
||||||
<spirit:value>Tue Dec 29 12:29:56 UTC 2020</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
|
||||||
<spirit:value>9:ba70ca63</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:view>
|
|
||||||
<spirit:view>
|
|
||||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
|
||||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
|
||||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
|
||||||
<spirit:value>9:ba70ca63</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:view>
|
|
||||||
<spirit:view>
|
|
||||||
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
|
||||||
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
|
||||||
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
|
||||||
<spirit:language>vhdl</spirit:language>
|
|
||||||
<spirit:modelName>startpic_450_200</spirit:modelName>
|
|
||||||
<spirit:fileSetRef>
|
|
||||||
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
|
||||||
</spirit:fileSetRef>
|
|
||||||
<spirit:parameters>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
|
||||||
<spirit:value>Tue Dec 29 12:29:56 UTC 2020</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
<spirit:parameter>
|
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
|
||||||
<spirit:value>9:ba70ca63</spirit:value>
|
|
||||||
</spirit:parameter>
|
|
||||||
</spirit:parameters>
|
|
||||||
</spirit:view>
|
|
||||||
<spirit:view>
|
<spirit:view>
|
||||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||||
<spirit:displayName>Simulation</spirit:displayName>
|
<spirit:displayName>Simulation</spirit:displayName>
|
||||||
|
|
@ -1591,6 +1540,57 @@
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
<spirit:view>
|
||||||
|
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
|
||||||
|
<spirit:displayName>VHDL Synthesis</spirit:displayName>
|
||||||
|
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||||
|
<spirit:language>vhdl</spirit:language>
|
||||||
|
<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
|
||||||
|
<spirit:fileSetRef>
|
||||||
|
<spirit:localName>xilinx_vhdlsynthesis_view_fileset</spirit:localName>
|
||||||
|
</spirit:fileSetRef>
|
||||||
|
<spirit:parameters>
|
||||||
|
<spirit:parameter>
|
||||||
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
|
<spirit:value>Wed Dec 30 00:40:12 UTC 2020</spirit:value>
|
||||||
|
</spirit:parameter>
|
||||||
|
<spirit:parameter>
|
||||||
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
|
<spirit:value>9:17e55f2b</spirit:value>
|
||||||
|
</spirit:parameter>
|
||||||
|
</spirit:parameters>
|
||||||
|
</spirit:view>
|
||||||
|
<spirit:view>
|
||||||
|
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||||
|
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||||
|
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||||
|
<spirit:parameters>
|
||||||
|
<spirit:parameter>
|
||||||
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
|
<spirit:value>9:17e55f2b</spirit:value>
|
||||||
|
</spirit:parameter>
|
||||||
|
</spirit:parameters>
|
||||||
|
</spirit:view>
|
||||||
|
<spirit:view>
|
||||||
|
<spirit:name>xilinx_vhdlsynthesiswrapper</spirit:name>
|
||||||
|
<spirit:displayName>VHDL Synthesis Wrapper</spirit:displayName>
|
||||||
|
<spirit:envIdentifier>vhdlSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||||
|
<spirit:language>vhdl</spirit:language>
|
||||||
|
<spirit:modelName>startpic_450_200</spirit:modelName>
|
||||||
|
<spirit:fileSetRef>
|
||||||
|
<spirit:localName>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:localName>
|
||||||
|
</spirit:fileSetRef>
|
||||||
|
<spirit:parameters>
|
||||||
|
<spirit:parameter>
|
||||||
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
|
<spirit:value>Wed Dec 30 00:40:12 UTC 2020</spirit:value>
|
||||||
|
</spirit:parameter>
|
||||||
|
<spirit:parameter>
|
||||||
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
|
<spirit:value>9:17e55f2b</spirit:value>
|
||||||
|
</spirit:parameter>
|
||||||
|
</spirit:parameters>
|
||||||
|
</spirit:view>
|
||||||
<spirit:view>
|
<spirit:view>
|
||||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||||
<spirit:displayName>External Files</spirit:displayName>
|
<spirit:displayName>External Files</spirit:displayName>
|
||||||
|
|
@ -1601,11 +1601,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 12:32:03 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:40:43 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:ba70ca63</spirit:value>
|
<spirit:value>9:17e55f2b</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -3549,33 +3549,6 @@
|
||||||
<spirit:userFileType>verilogTemplate</spirit:userFileType>
|
<spirit:userFileType>verilogTemplate</spirit:userFileType>
|
||||||
</spirit:file>
|
</spirit:file>
|
||||||
</spirit:fileSet>
|
</spirit:fileSet>
|
||||||
<spirit:fileSet>
|
|
||||||
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>startpic_450_200_ooc.xdc</spirit:name>
|
|
||||||
<spirit:userFileType>xdc</spirit:userFileType>
|
|
||||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
|
||||||
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
|
||||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
|
||||||
</spirit:file>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>startpic_450_200.mif</spirit:name>
|
|
||||||
<spirit:userFileType>mif</spirit:userFileType>
|
|
||||||
</spirit:file>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd</spirit:name>
|
|
||||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
||||||
<spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
|
|
||||||
</spirit:file>
|
|
||||||
</spirit:fileSet>
|
|
||||||
<spirit:fileSet>
|
|
||||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
|
||||||
<spirit:file>
|
|
||||||
<spirit:name>synth/startpic_450_200.vhd</spirit:name>
|
|
||||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
|
||||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
|
||||||
</spirit:file>
|
|
||||||
</spirit:fileSet>
|
|
||||||
<spirit:fileSet>
|
<spirit:fileSet>
|
||||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||||
<spirit:file>
|
<spirit:file>
|
||||||
|
|
@ -3616,6 +3589,33 @@
|
||||||
<spirit:userFileType>text</spirit:userFileType>
|
<spirit:userFileType>text</spirit:userFileType>
|
||||||
</spirit:file>
|
</spirit:file>
|
||||||
</spirit:fileSet>
|
</spirit:fileSet>
|
||||||
|
<spirit:fileSet>
|
||||||
|
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
|
||||||
|
<spirit:file>
|
||||||
|
<spirit:name>startpic_450_200_ooc.xdc</spirit:name>
|
||||||
|
<spirit:userFileType>xdc</spirit:userFileType>
|
||||||
|
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||||
|
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
||||||
|
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||||
|
</spirit:file>
|
||||||
|
<spirit:file>
|
||||||
|
<spirit:name>startpic_450_200.mif</spirit:name>
|
||||||
|
<spirit:userFileType>mif</spirit:userFileType>
|
||||||
|
</spirit:file>
|
||||||
|
<spirit:file>
|
||||||
|
<spirit:name>hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd</spirit:name>
|
||||||
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||||
|
<spirit:logicalName>blk_mem_gen_v8_4_4</spirit:logicalName>
|
||||||
|
</spirit:file>
|
||||||
|
</spirit:fileSet>
|
||||||
|
<spirit:fileSet>
|
||||||
|
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||||
|
<spirit:file>
|
||||||
|
<spirit:name>synth/startpic_450_200.vhd</spirit:name>
|
||||||
|
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||||
|
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||||
|
</spirit:file>
|
||||||
|
</spirit:fileSet>
|
||||||
<spirit:fileSet>
|
<spirit:fileSet>
|
||||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||||
<spirit:file>
|
<spirit:file>
|
||||||
|
|
|
||||||
|
|
@ -1,10 +1,10 @@
|
||||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
// --------------------------------------------------------------------------------
|
// --------------------------------------------------------------------------------
|
||||||
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
// Date : Tue Dec 29 20:32:03 2020
|
// Date : Tue Dec 29 20:32:02 2020
|
||||||
// Host : cxz666 running 64-bit major release (build 9200)
|
// Host : cxz666 running 64-bit major release (build 9200)
|
||||||
// Command : write_verilog -force -mode funcsim
|
// Command : write_verilog -force -mode funcsim -rename_top startpic_450_200 -prefix
|
||||||
// e:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/startpic_450_200/startpic_450_200_sim_netlist.v
|
// startpic_450_200_ startpic_450_200_sim_netlist.v
|
||||||
// Design : startpic_450_200
|
// Design : startpic_450_200
|
||||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
|
@ -191,7 +191,6 @@ module startpic_450_200
|
||||||
.web(1'b0));
|
.web(1'b0));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "bindec" *)
|
|
||||||
module startpic_450_200_bindec
|
module startpic_450_200_bindec
|
||||||
(ena_array,
|
(ena_array,
|
||||||
addra,
|
addra,
|
||||||
|
|
@ -416,7 +415,6 @@ module startpic_450_200_bindec
|
||||||
.O(ena_array[10]));
|
.O(ena_array[10]));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
|
|
||||||
module startpic_450_200_blk_mem_gen_generic_cstr
|
module startpic_450_200_blk_mem_gen_generic_cstr
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -911,7 +909,6 @@ module startpic_450_200_blk_mem_gen_generic_cstr
|
||||||
.ena_array(ena_array[2]));
|
.ena_array(ena_array[2]));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_mux" *)
|
|
||||||
module startpic_450_200_blk_mem_gen_mux
|
module startpic_450_200_blk_mem_gen_mux
|
||||||
(douta,
|
(douta,
|
||||||
DOADO,
|
DOADO,
|
||||||
|
|
@ -2027,7 +2024,6 @@ module startpic_450_200_blk_mem_gen_mux
|
||||||
.R(1'b0));
|
.R(1'b0));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
|
|
||||||
module startpic_450_200_blk_mem_gen_prim_width
|
module startpic_450_200_blk_mem_gen_prim_width
|
||||||
(DOUTA,
|
(DOUTA,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -2891,7 +2887,6 @@ module startpic_450_200_blk_mem_gen_prim_width__parameterized9
|
||||||
.ena_array(ena_array));
|
.ena_array(ena_array));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
|
|
||||||
module startpic_450_200_blk_mem_gen_prim_wrapper_init
|
module startpic_450_200_blk_mem_gen_prim_wrapper_init
|
||||||
(DOUTA,
|
(DOUTA,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -10354,7 +10349,6 @@ module startpic_450_200_blk_mem_gen_prim_wrapper_init__parameterized9
|
||||||
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
|
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
|
|
||||||
module startpic_450_200_blk_mem_gen_top
|
module startpic_450_200_blk_mem_gen_top
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -10402,7 +10396,7 @@ endmodule
|
||||||
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "90000" *)
|
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "90000" *)
|
||||||
(* C_WRITE_DEPTH_B = "90000" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
(* C_WRITE_DEPTH_B = "90000" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
||||||
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
|
(* downgradeipidentifiedwarnings = "yes" *)
|
||||||
module startpic_450_200_blk_mem_gen_v8_4_4
|
module startpic_450_200_blk_mem_gen_v8_4_4
|
||||||
(clka,
|
(clka,
|
||||||
rsta,
|
rsta,
|
||||||
|
|
@ -10628,7 +10622,6 @@ module startpic_450_200_blk_mem_gen_v8_4_4
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
|
|
||||||
module startpic_450_200_blk_mem_gen_v8_4_4_synth
|
module startpic_450_200_blk_mem_gen_v8_4_4_synth
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
|
||||||
|
|
@ -1,10 +1,10 @@
|
||||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
||||||
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
-- Date : Tue Dec 29 20:32:03 2020
|
-- Date : Tue Dec 29 20:32:02 2020
|
||||||
-- Host : cxz666 running 64-bit major release (build 9200)
|
-- Host : cxz666 running 64-bit major release (build 9200)
|
||||||
-- Command : write_vhdl -force -mode funcsim
|
-- Command : write_vhdl -force -mode funcsim -rename_top startpic_450_200 -prefix
|
||||||
-- e:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/startpic_450_200/startpic_450_200_sim_netlist.vhdl
|
-- startpic_450_200_ startpic_450_200_sim_netlist.vhdl
|
||||||
-- Design : startpic_450_200
|
-- Design : startpic_450_200
|
||||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
|
@ -20,8 +20,6 @@ entity startpic_450_200_bindec is
|
||||||
addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
|
addra : in STD_LOGIC_VECTOR ( 4 downto 0 );
|
||||||
ena : in STD_LOGIC
|
ena : in STD_LOGIC
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of startpic_450_200_bindec : entity is "bindec";
|
|
||||||
end startpic_450_200_bindec;
|
end startpic_450_200_bindec;
|
||||||
|
|
||||||
architecture STRUCTURE of startpic_450_200_bindec is
|
architecture STRUCTURE of startpic_450_200_bindec is
|
||||||
|
|
@ -362,8 +360,6 @@ entity startpic_450_200_blk_mem_gen_mux is
|
||||||
\douta[11]_INST_0_i_1_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
|
\douta[11]_INST_0_i_1_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
\douta[11]_INST_0_i_1_4\ : in STD_LOGIC_VECTOR ( 0 to 0 )
|
\douta[11]_INST_0_i_1_4\ : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
|
|
||||||
end startpic_450_200_blk_mem_gen_mux;
|
end startpic_450_200_blk_mem_gen_mux;
|
||||||
|
|
||||||
architecture STRUCTURE of startpic_450_200_blk_mem_gen_mux is
|
architecture STRUCTURE of startpic_450_200_blk_mem_gen_mux is
|
||||||
|
|
@ -1615,8 +1611,6 @@ entity startpic_450_200_blk_mem_gen_prim_wrapper_init is
|
||||||
\^ena\ : in STD_LOGIC;
|
\^ena\ : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
|
|
||||||
end startpic_450_200_blk_mem_gen_prim_wrapper_init;
|
end startpic_450_200_blk_mem_gen_prim_wrapper_init;
|
||||||
|
|
||||||
architecture STRUCTURE of startpic_450_200_blk_mem_gen_prim_wrapper_init is
|
architecture STRUCTURE of startpic_450_200_blk_mem_gen_prim_wrapper_init is
|
||||||
|
|
@ -9212,8 +9206,6 @@ entity startpic_450_200_blk_mem_gen_prim_width is
|
||||||
\^ena\ : in STD_LOGIC;
|
\^ena\ : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
|
|
||||||
end startpic_450_200_blk_mem_gen_prim_width;
|
end startpic_450_200_blk_mem_gen_prim_width;
|
||||||
|
|
||||||
architecture STRUCTURE of startpic_450_200_blk_mem_gen_prim_width is
|
architecture STRUCTURE of startpic_450_200_blk_mem_gen_prim_width is
|
||||||
|
|
@ -10036,8 +10028,6 @@ entity startpic_450_200_blk_mem_gen_generic_cstr is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
|
|
||||||
end startpic_450_200_blk_mem_gen_generic_cstr;
|
end startpic_450_200_blk_mem_gen_generic_cstr;
|
||||||
|
|
||||||
architecture STRUCTURE of startpic_450_200_blk_mem_gen_generic_cstr is
|
architecture STRUCTURE of startpic_450_200_blk_mem_gen_generic_cstr is
|
||||||
|
|
@ -10910,8 +10900,6 @@ entity startpic_450_200_blk_mem_gen_top is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_top : entity is "blk_mem_gen_top";
|
|
||||||
end startpic_450_200_blk_mem_gen_top;
|
end startpic_450_200_blk_mem_gen_top;
|
||||||
|
|
||||||
architecture STRUCTURE of startpic_450_200_blk_mem_gen_top is
|
architecture STRUCTURE of startpic_450_200_blk_mem_gen_top is
|
||||||
|
|
@ -10935,8 +10923,6 @@ entity startpic_450_200_blk_mem_gen_v8_4_4_synth is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 16 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
|
|
||||||
end startpic_450_200_blk_mem_gen_v8_4_4_synth;
|
end startpic_450_200_blk_mem_gen_v8_4_4_synth;
|
||||||
|
|
||||||
architecture STRUCTURE of startpic_450_200_blk_mem_gen_v8_4_4_synth is
|
architecture STRUCTURE of startpic_450_200_blk_mem_gen_v8_4_4_synth is
|
||||||
|
|
@ -11169,8 +11155,6 @@ entity startpic_450_200_blk_mem_gen_v8_4_4 is
|
||||||
attribute C_WRITE_WIDTH_B of startpic_450_200_blk_mem_gen_v8_4_4 : entity is 12;
|
attribute C_WRITE_WIDTH_B of startpic_450_200_blk_mem_gen_v8_4_4 : entity is 12;
|
||||||
attribute C_XDEVICEFAMILY : string;
|
attribute C_XDEVICEFAMILY : string;
|
||||||
attribute C_XDEVICEFAMILY of startpic_450_200_blk_mem_gen_v8_4_4 : entity is "artix7";
|
attribute C_XDEVICEFAMILY of startpic_450_200_blk_mem_gen_v8_4_4 : entity is "artix7";
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of startpic_450_200_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
|
|
||||||
attribute downgradeipidentifiedwarnings : string;
|
attribute downgradeipidentifiedwarnings : string;
|
||||||
attribute downgradeipidentifiedwarnings of startpic_450_200_blk_mem_gen_v8_4_4 : entity is "yes";
|
attribute downgradeipidentifiedwarnings of startpic_450_200_blk_mem_gen_v8_4_4 : entity is "yes";
|
||||||
end startpic_450_200_blk_mem_gen_v8_4_4;
|
end startpic_450_200_blk_mem_gen_v8_4_4;
|
||||||
|
|
|
||||||
|
|
@ -1552,11 +1552,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:26:40 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:39:53 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:d4e82092</spirit:value>
|
<spirit:value>9:e07fb422</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1567,7 +1567,7 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:d4e82092</spirit:value>
|
<spirit:value>9:e07fb422</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1583,11 +1583,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:26:40 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:39:53 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:d4e82092</spirit:value>
|
<spirit:value>9:e07fb422</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1601,11 +1601,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:28:49 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:40:32 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:d4e82092</spirit:value>
|
<spirit:value>9:e07fb422</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
|
||||||
|
|
@ -1,10 +1,10 @@
|
||||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
// --------------------------------------------------------------------------------
|
// --------------------------------------------------------------------------------
|
||||||
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
// Date : Tue Dec 29 16:28:49 2020
|
// Date : Tue Dec 29 16:28:48 2020
|
||||||
// Host : cxz666 running 64-bit major release (build 9200)
|
// Host : cxz666 running 64-bit major release (build 9200)
|
||||||
// Command : write_verilog -force -mode funcsim
|
// Command : write_verilog -force -mode funcsim -rename_top tank_down_img -prefix
|
||||||
// E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/tank_down_img/tank_down_img_sim_netlist.v
|
// tank_down_img_ tank_down_img_sim_netlist.v
|
||||||
// Design : tank_down_img
|
// Design : tank_down_img
|
||||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
|
@ -191,7 +191,6 @@ module tank_down_img
|
||||||
.web(1'b0));
|
.web(1'b0));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
|
|
||||||
module tank_down_img_blk_mem_gen_generic_cstr
|
module tank_down_img_blk_mem_gen_generic_cstr
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -214,7 +213,6 @@ module tank_down_img_blk_mem_gen_generic_cstr
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
|
|
||||||
module tank_down_img_blk_mem_gen_prim_width
|
module tank_down_img_blk_mem_gen_prim_width
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -237,7 +235,6 @@ module tank_down_img_blk_mem_gen_prim_width
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
|
|
||||||
module tank_down_img_blk_mem_gen_prim_wrapper_init
|
module tank_down_img_blk_mem_gen_prim_wrapper_init
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -387,7 +384,6 @@ module tank_down_img_blk_mem_gen_prim_wrapper_init
|
||||||
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
|
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
|
|
||||||
module tank_down_img_blk_mem_gen_top
|
module tank_down_img_blk_mem_gen_top
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -435,7 +431,7 @@ endmodule
|
||||||
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "1024" *)
|
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "1024" *)
|
||||||
(* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
(* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
||||||
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
|
(* downgradeipidentifiedwarnings = "yes" *)
|
||||||
module tank_down_img_blk_mem_gen_v8_4_4
|
module tank_down_img_blk_mem_gen_v8_4_4
|
||||||
(clka,
|
(clka,
|
||||||
rsta,
|
rsta,
|
||||||
|
|
@ -647,7 +643,6 @@ module tank_down_img_blk_mem_gen_v8_4_4
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
|
|
||||||
module tank_down_img_blk_mem_gen_v8_4_4_synth
|
module tank_down_img_blk_mem_gen_v8_4_4_synth
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
|
||||||
|
|
@ -1,10 +1,10 @@
|
||||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
||||||
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
-- Date : Tue Dec 29 16:28:49 2020
|
-- Date : Tue Dec 29 16:28:48 2020
|
||||||
-- Host : cxz666 running 64-bit major release (build 9200)
|
-- Host : cxz666 running 64-bit major release (build 9200)
|
||||||
-- Command : write_vhdl -force -mode funcsim
|
-- Command : write_vhdl -force -mode funcsim -rename_top tank_down_img -prefix
|
||||||
-- E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/tank_down_img/tank_down_img_sim_netlist.vhdl
|
-- tank_down_img_ tank_down_img_sim_netlist.vhdl
|
||||||
-- Design : tank_down_img
|
-- Design : tank_down_img
|
||||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
|
@ -21,8 +21,6 @@ entity tank_down_img_blk_mem_gen_prim_wrapper_init is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_down_img_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
|
|
||||||
end tank_down_img_blk_mem_gen_prim_wrapper_init;
|
end tank_down_img_blk_mem_gen_prim_wrapper_init;
|
||||||
|
|
||||||
architecture STRUCTURE of tank_down_img_blk_mem_gen_prim_wrapper_init is
|
architecture STRUCTURE of tank_down_img_blk_mem_gen_prim_wrapper_init is
|
||||||
|
|
@ -182,8 +180,6 @@ entity tank_down_img_blk_mem_gen_prim_width is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_down_img_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
|
|
||||||
end tank_down_img_blk_mem_gen_prim_width;
|
end tank_down_img_blk_mem_gen_prim_width;
|
||||||
|
|
||||||
architecture STRUCTURE of tank_down_img_blk_mem_gen_prim_width is
|
architecture STRUCTURE of tank_down_img_blk_mem_gen_prim_width is
|
||||||
|
|
@ -207,8 +203,6 @@ entity tank_down_img_blk_mem_gen_generic_cstr is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_down_img_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
|
|
||||||
end tank_down_img_blk_mem_gen_generic_cstr;
|
end tank_down_img_blk_mem_gen_generic_cstr;
|
||||||
|
|
||||||
architecture STRUCTURE of tank_down_img_blk_mem_gen_generic_cstr is
|
architecture STRUCTURE of tank_down_img_blk_mem_gen_generic_cstr is
|
||||||
|
|
@ -232,8 +226,6 @@ entity tank_down_img_blk_mem_gen_top is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_down_img_blk_mem_gen_top : entity is "blk_mem_gen_top";
|
|
||||||
end tank_down_img_blk_mem_gen_top;
|
end tank_down_img_blk_mem_gen_top;
|
||||||
|
|
||||||
architecture STRUCTURE of tank_down_img_blk_mem_gen_top is
|
architecture STRUCTURE of tank_down_img_blk_mem_gen_top is
|
||||||
|
|
@ -257,8 +249,6 @@ entity tank_down_img_blk_mem_gen_v8_4_4_synth is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_down_img_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
|
|
||||||
end tank_down_img_blk_mem_gen_v8_4_4_synth;
|
end tank_down_img_blk_mem_gen_v8_4_4_synth;
|
||||||
|
|
||||||
architecture STRUCTURE of tank_down_img_blk_mem_gen_v8_4_4_synth is
|
architecture STRUCTURE of tank_down_img_blk_mem_gen_v8_4_4_synth is
|
||||||
|
|
@ -491,8 +481,6 @@ entity tank_down_img_blk_mem_gen_v8_4_4 is
|
||||||
attribute C_WRITE_WIDTH_B of tank_down_img_blk_mem_gen_v8_4_4 : entity is 12;
|
attribute C_WRITE_WIDTH_B of tank_down_img_blk_mem_gen_v8_4_4 : entity is 12;
|
||||||
attribute C_XDEVICEFAMILY : string;
|
attribute C_XDEVICEFAMILY : string;
|
||||||
attribute C_XDEVICEFAMILY of tank_down_img_blk_mem_gen_v8_4_4 : entity is "artix7";
|
attribute C_XDEVICEFAMILY of tank_down_img_blk_mem_gen_v8_4_4 : entity is "artix7";
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_down_img_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
|
|
||||||
attribute downgradeipidentifiedwarnings : string;
|
attribute downgradeipidentifiedwarnings : string;
|
||||||
attribute downgradeipidentifiedwarnings of tank_down_img_blk_mem_gen_v8_4_4 : entity is "yes";
|
attribute downgradeipidentifiedwarnings of tank_down_img_blk_mem_gen_v8_4_4 : entity is "yes";
|
||||||
end tank_down_img_blk_mem_gen_v8_4_4;
|
end tank_down_img_blk_mem_gen_v8_4_4;
|
||||||
|
|
|
||||||
|
|
@ -1552,11 +1552,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:26:36 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:39:50 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:7b15ce1f</spirit:value>
|
<spirit:value>9:4f825aaf</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1567,7 +1567,7 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:7b15ce1f</spirit:value>
|
<spirit:value>9:4f825aaf</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1583,11 +1583,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:26:36 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:39:50 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:7b15ce1f</spirit:value>
|
<spirit:value>9:4f825aaf</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1601,11 +1601,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:28:49 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:40:33 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:7b15ce1f</spirit:value>
|
<spirit:value>9:4f825aaf</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
|
||||||
|
|
@ -3,8 +3,8 @@
|
||||||
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
// Date : Tue Dec 29 16:28:49 2020
|
// Date : Tue Dec 29 16:28:49 2020
|
||||||
// Host : cxz666 running 64-bit major release (build 9200)
|
// Host : cxz666 running 64-bit major release (build 9200)
|
||||||
// Command : write_verilog -force -mode funcsim
|
// Command : write_verilog -force -mode funcsim -rename_top tank_left_img -prefix
|
||||||
// E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/tank_left_img/tank_left_img_sim_netlist.v
|
// tank_left_img_ tank_left_img_sim_netlist.v
|
||||||
// Design : tank_left_img
|
// Design : tank_left_img
|
||||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
|
@ -191,7 +191,6 @@ module tank_left_img
|
||||||
.web(1'b0));
|
.web(1'b0));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
|
|
||||||
module tank_left_img_blk_mem_gen_generic_cstr
|
module tank_left_img_blk_mem_gen_generic_cstr
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -214,7 +213,6 @@ module tank_left_img_blk_mem_gen_generic_cstr
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
|
|
||||||
module tank_left_img_blk_mem_gen_prim_width
|
module tank_left_img_blk_mem_gen_prim_width
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -237,7 +235,6 @@ module tank_left_img_blk_mem_gen_prim_width
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
|
|
||||||
module tank_left_img_blk_mem_gen_prim_wrapper_init
|
module tank_left_img_blk_mem_gen_prim_wrapper_init
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -387,7 +384,6 @@ module tank_left_img_blk_mem_gen_prim_wrapper_init
|
||||||
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
|
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
|
|
||||||
module tank_left_img_blk_mem_gen_top
|
module tank_left_img_blk_mem_gen_top
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -435,7 +431,7 @@ endmodule
|
||||||
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "1024" *)
|
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "1024" *)
|
||||||
(* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
(* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
||||||
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
|
(* downgradeipidentifiedwarnings = "yes" *)
|
||||||
module tank_left_img_blk_mem_gen_v8_4_4
|
module tank_left_img_blk_mem_gen_v8_4_4
|
||||||
(clka,
|
(clka,
|
||||||
rsta,
|
rsta,
|
||||||
|
|
@ -647,7 +643,6 @@ module tank_left_img_blk_mem_gen_v8_4_4
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
|
|
||||||
module tank_left_img_blk_mem_gen_v8_4_4_synth
|
module tank_left_img_blk_mem_gen_v8_4_4_synth
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
|
||||||
|
|
@ -3,8 +3,8 @@
|
||||||
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
-- Date : Tue Dec 29 16:28:49 2020
|
-- Date : Tue Dec 29 16:28:49 2020
|
||||||
-- Host : cxz666 running 64-bit major release (build 9200)
|
-- Host : cxz666 running 64-bit major release (build 9200)
|
||||||
-- Command : write_vhdl -force -mode funcsim
|
-- Command : write_vhdl -force -mode funcsim -rename_top tank_left_img -prefix
|
||||||
-- E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/tank_left_img/tank_left_img_sim_netlist.vhdl
|
-- tank_left_img_ tank_left_img_sim_netlist.vhdl
|
||||||
-- Design : tank_left_img
|
-- Design : tank_left_img
|
||||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
|
@ -21,8 +21,6 @@ entity tank_left_img_blk_mem_gen_prim_wrapper_init is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_left_img_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
|
|
||||||
end tank_left_img_blk_mem_gen_prim_wrapper_init;
|
end tank_left_img_blk_mem_gen_prim_wrapper_init;
|
||||||
|
|
||||||
architecture STRUCTURE of tank_left_img_blk_mem_gen_prim_wrapper_init is
|
architecture STRUCTURE of tank_left_img_blk_mem_gen_prim_wrapper_init is
|
||||||
|
|
@ -182,8 +180,6 @@ entity tank_left_img_blk_mem_gen_prim_width is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_left_img_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
|
|
||||||
end tank_left_img_blk_mem_gen_prim_width;
|
end tank_left_img_blk_mem_gen_prim_width;
|
||||||
|
|
||||||
architecture STRUCTURE of tank_left_img_blk_mem_gen_prim_width is
|
architecture STRUCTURE of tank_left_img_blk_mem_gen_prim_width is
|
||||||
|
|
@ -207,8 +203,6 @@ entity tank_left_img_blk_mem_gen_generic_cstr is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_left_img_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
|
|
||||||
end tank_left_img_blk_mem_gen_generic_cstr;
|
end tank_left_img_blk_mem_gen_generic_cstr;
|
||||||
|
|
||||||
architecture STRUCTURE of tank_left_img_blk_mem_gen_generic_cstr is
|
architecture STRUCTURE of tank_left_img_blk_mem_gen_generic_cstr is
|
||||||
|
|
@ -232,8 +226,6 @@ entity tank_left_img_blk_mem_gen_top is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_left_img_blk_mem_gen_top : entity is "blk_mem_gen_top";
|
|
||||||
end tank_left_img_blk_mem_gen_top;
|
end tank_left_img_blk_mem_gen_top;
|
||||||
|
|
||||||
architecture STRUCTURE of tank_left_img_blk_mem_gen_top is
|
architecture STRUCTURE of tank_left_img_blk_mem_gen_top is
|
||||||
|
|
@ -257,8 +249,6 @@ entity tank_left_img_blk_mem_gen_v8_4_4_synth is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_left_img_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
|
|
||||||
end tank_left_img_blk_mem_gen_v8_4_4_synth;
|
end tank_left_img_blk_mem_gen_v8_4_4_synth;
|
||||||
|
|
||||||
architecture STRUCTURE of tank_left_img_blk_mem_gen_v8_4_4_synth is
|
architecture STRUCTURE of tank_left_img_blk_mem_gen_v8_4_4_synth is
|
||||||
|
|
@ -491,8 +481,6 @@ entity tank_left_img_blk_mem_gen_v8_4_4 is
|
||||||
attribute C_WRITE_WIDTH_B of tank_left_img_blk_mem_gen_v8_4_4 : entity is 12;
|
attribute C_WRITE_WIDTH_B of tank_left_img_blk_mem_gen_v8_4_4 : entity is 12;
|
||||||
attribute C_XDEVICEFAMILY : string;
|
attribute C_XDEVICEFAMILY : string;
|
||||||
attribute C_XDEVICEFAMILY of tank_left_img_blk_mem_gen_v8_4_4 : entity is "artix7";
|
attribute C_XDEVICEFAMILY of tank_left_img_blk_mem_gen_v8_4_4 : entity is "artix7";
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_left_img_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
|
|
||||||
attribute downgradeipidentifiedwarnings : string;
|
attribute downgradeipidentifiedwarnings : string;
|
||||||
attribute downgradeipidentifiedwarnings of tank_left_img_blk_mem_gen_v8_4_4 : entity is "yes";
|
attribute downgradeipidentifiedwarnings of tank_left_img_blk_mem_gen_v8_4_4 : entity is "yes";
|
||||||
end tank_left_img_blk_mem_gen_v8_4_4;
|
end tank_left_img_blk_mem_gen_v8_4_4;
|
||||||
|
|
|
||||||
|
|
@ -1552,11 +1552,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:26:37 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:39:51 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:bae1e80d</spirit:value>
|
<spirit:value>9:71b4cc15</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1567,7 +1567,7 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:bae1e80d</spirit:value>
|
<spirit:value>9:71b4cc15</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1583,11 +1583,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:26:37 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:39:51 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:bae1e80d</spirit:value>
|
<spirit:value>9:71b4cc15</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1601,11 +1601,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:28:49 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:40:32 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:bae1e80d</spirit:value>
|
<spirit:value>9:71b4cc15</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
|
||||||
|
|
@ -3,8 +3,8 @@
|
||||||
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
// Date : Tue Dec 29 16:28:49 2020
|
// Date : Tue Dec 29 16:28:49 2020
|
||||||
// Host : cxz666 running 64-bit major release (build 9200)
|
// Host : cxz666 running 64-bit major release (build 9200)
|
||||||
// Command : write_verilog -force -mode funcsim
|
// Command : write_verilog -force -mode funcsim -rename_top tank_right_img -prefix
|
||||||
// E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/tank_right_img/tank_right_img_sim_netlist.v
|
// tank_right_img_ tank_right_img_sim_netlist.v
|
||||||
// Design : tank_right_img
|
// Design : tank_right_img
|
||||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
|
@ -191,7 +191,6 @@ module tank_right_img
|
||||||
.web(1'b0));
|
.web(1'b0));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
|
|
||||||
module tank_right_img_blk_mem_gen_generic_cstr
|
module tank_right_img_blk_mem_gen_generic_cstr
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -214,7 +213,6 @@ module tank_right_img_blk_mem_gen_generic_cstr
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
|
|
||||||
module tank_right_img_blk_mem_gen_prim_width
|
module tank_right_img_blk_mem_gen_prim_width
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -237,7 +235,6 @@ module tank_right_img_blk_mem_gen_prim_width
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
|
|
||||||
module tank_right_img_blk_mem_gen_prim_wrapper_init
|
module tank_right_img_blk_mem_gen_prim_wrapper_init
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -387,7 +384,6 @@ module tank_right_img_blk_mem_gen_prim_wrapper_init
|
||||||
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
|
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
|
|
||||||
module tank_right_img_blk_mem_gen_top
|
module tank_right_img_blk_mem_gen_top
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -435,7 +431,7 @@ endmodule
|
||||||
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "1024" *)
|
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "1024" *)
|
||||||
(* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
(* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
||||||
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
|
(* downgradeipidentifiedwarnings = "yes" *)
|
||||||
module tank_right_img_blk_mem_gen_v8_4_4
|
module tank_right_img_blk_mem_gen_v8_4_4
|
||||||
(clka,
|
(clka,
|
||||||
rsta,
|
rsta,
|
||||||
|
|
@ -647,7 +643,6 @@ module tank_right_img_blk_mem_gen_v8_4_4
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
|
|
||||||
module tank_right_img_blk_mem_gen_v8_4_4_synth
|
module tank_right_img_blk_mem_gen_v8_4_4_synth
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
|
||||||
|
|
@ -3,8 +3,8 @@
|
||||||
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
-- Date : Tue Dec 29 16:28:49 2020
|
-- Date : Tue Dec 29 16:28:49 2020
|
||||||
-- Host : cxz666 running 64-bit major release (build 9200)
|
-- Host : cxz666 running 64-bit major release (build 9200)
|
||||||
-- Command : write_vhdl -force -mode funcsim
|
-- Command : write_vhdl -force -mode funcsim -rename_top tank_right_img -prefix
|
||||||
-- E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/tank_right_img/tank_right_img_sim_netlist.vhdl
|
-- tank_right_img_ tank_right_img_sim_netlist.vhdl
|
||||||
-- Design : tank_right_img
|
-- Design : tank_right_img
|
||||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
|
@ -21,8 +21,6 @@ entity tank_right_img_blk_mem_gen_prim_wrapper_init is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_right_img_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
|
|
||||||
end tank_right_img_blk_mem_gen_prim_wrapper_init;
|
end tank_right_img_blk_mem_gen_prim_wrapper_init;
|
||||||
|
|
||||||
architecture STRUCTURE of tank_right_img_blk_mem_gen_prim_wrapper_init is
|
architecture STRUCTURE of tank_right_img_blk_mem_gen_prim_wrapper_init is
|
||||||
|
|
@ -182,8 +180,6 @@ entity tank_right_img_blk_mem_gen_prim_width is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_right_img_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
|
|
||||||
end tank_right_img_blk_mem_gen_prim_width;
|
end tank_right_img_blk_mem_gen_prim_width;
|
||||||
|
|
||||||
architecture STRUCTURE of tank_right_img_blk_mem_gen_prim_width is
|
architecture STRUCTURE of tank_right_img_blk_mem_gen_prim_width is
|
||||||
|
|
@ -207,8 +203,6 @@ entity tank_right_img_blk_mem_gen_generic_cstr is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_right_img_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
|
|
||||||
end tank_right_img_blk_mem_gen_generic_cstr;
|
end tank_right_img_blk_mem_gen_generic_cstr;
|
||||||
|
|
||||||
architecture STRUCTURE of tank_right_img_blk_mem_gen_generic_cstr is
|
architecture STRUCTURE of tank_right_img_blk_mem_gen_generic_cstr is
|
||||||
|
|
@ -232,8 +226,6 @@ entity tank_right_img_blk_mem_gen_top is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_right_img_blk_mem_gen_top : entity is "blk_mem_gen_top";
|
|
||||||
end tank_right_img_blk_mem_gen_top;
|
end tank_right_img_blk_mem_gen_top;
|
||||||
|
|
||||||
architecture STRUCTURE of tank_right_img_blk_mem_gen_top is
|
architecture STRUCTURE of tank_right_img_blk_mem_gen_top is
|
||||||
|
|
@ -257,8 +249,6 @@ entity tank_right_img_blk_mem_gen_v8_4_4_synth is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_right_img_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
|
|
||||||
end tank_right_img_blk_mem_gen_v8_4_4_synth;
|
end tank_right_img_blk_mem_gen_v8_4_4_synth;
|
||||||
|
|
||||||
architecture STRUCTURE of tank_right_img_blk_mem_gen_v8_4_4_synth is
|
architecture STRUCTURE of tank_right_img_blk_mem_gen_v8_4_4_synth is
|
||||||
|
|
@ -491,8 +481,6 @@ entity tank_right_img_blk_mem_gen_v8_4_4 is
|
||||||
attribute C_WRITE_WIDTH_B of tank_right_img_blk_mem_gen_v8_4_4 : entity is 12;
|
attribute C_WRITE_WIDTH_B of tank_right_img_blk_mem_gen_v8_4_4 : entity is 12;
|
||||||
attribute C_XDEVICEFAMILY : string;
|
attribute C_XDEVICEFAMILY : string;
|
||||||
attribute C_XDEVICEFAMILY of tank_right_img_blk_mem_gen_v8_4_4 : entity is "artix7";
|
attribute C_XDEVICEFAMILY of tank_right_img_blk_mem_gen_v8_4_4 : entity is "artix7";
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_right_img_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
|
|
||||||
attribute downgradeipidentifiedwarnings : string;
|
attribute downgradeipidentifiedwarnings : string;
|
||||||
attribute downgradeipidentifiedwarnings of tank_right_img_blk_mem_gen_v8_4_4 : entity is "yes";
|
attribute downgradeipidentifiedwarnings of tank_right_img_blk_mem_gen_v8_4_4 : entity is "yes";
|
||||||
end tank_right_img_blk_mem_gen_v8_4_4;
|
end tank_right_img_blk_mem_gen_v8_4_4;
|
||||||
|
|
|
||||||
|
|
@ -1552,11 +1552,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:26:39 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:39:52 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:a68d50f1</spirit:value>
|
<spirit:value>9:521e566d</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1567,7 +1567,7 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:a68d50f1</spirit:value>
|
<spirit:value>9:521e566d</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1583,11 +1583,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:26:39 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:39:52 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:a68d50f1</spirit:value>
|
<spirit:value>9:521e566d</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
@ -1601,11 +1601,11 @@
|
||||||
<spirit:parameters>
|
<spirit:parameters>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>GENtimestamp</spirit:name>
|
<spirit:name>GENtimestamp</spirit:name>
|
||||||
<spirit:value>Tue Dec 29 08:28:51 UTC 2020</spirit:value>
|
<spirit:value>Wed Dec 30 00:40:33 UTC 2020</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
<spirit:parameter>
|
<spirit:parameter>
|
||||||
<spirit:name>outputProductCRC</spirit:name>
|
<spirit:name>outputProductCRC</spirit:name>
|
||||||
<spirit:value>9:a68d50f1</spirit:value>
|
<spirit:value>9:521e566d</spirit:value>
|
||||||
</spirit:parameter>
|
</spirit:parameter>
|
||||||
</spirit:parameters>
|
</spirit:parameters>
|
||||||
</spirit:view>
|
</spirit:view>
|
||||||
|
|
|
||||||
|
|
@ -1,10 +1,10 @@
|
||||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
// --------------------------------------------------------------------------------
|
// --------------------------------------------------------------------------------
|
||||||
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
// Date : Tue Dec 29 16:28:51 2020
|
// Date : Tue Dec 29 16:28:50 2020
|
||||||
// Host : cxz666 running 64-bit major release (build 9200)
|
// Host : cxz666 running 64-bit major release (build 9200)
|
||||||
// Command : write_verilog -force -mode funcsim
|
// Command : write_verilog -force -mode funcsim -rename_top tank_up_img -prefix
|
||||||
// E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/tank_up_img/tank_up_img_sim_netlist.v
|
// tank_up_img_ tank_up_img_sim_netlist.v
|
||||||
// Design : tank_up_img
|
// Design : tank_up_img
|
||||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
|
@ -191,7 +191,6 @@ module tank_up_img
|
||||||
.web(1'b0));
|
.web(1'b0));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
|
|
||||||
module tank_up_img_blk_mem_gen_generic_cstr
|
module tank_up_img_blk_mem_gen_generic_cstr
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -214,7 +213,6 @@ module tank_up_img_blk_mem_gen_generic_cstr
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
|
|
||||||
module tank_up_img_blk_mem_gen_prim_width
|
module tank_up_img_blk_mem_gen_prim_width
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -237,7 +235,6 @@ module tank_up_img_blk_mem_gen_prim_width
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
|
|
||||||
module tank_up_img_blk_mem_gen_prim_wrapper_init
|
module tank_up_img_blk_mem_gen_prim_wrapper_init
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -387,7 +384,6 @@ module tank_up_img_blk_mem_gen_prim_wrapper_init
|
||||||
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
|
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
|
|
||||||
module tank_up_img_blk_mem_gen_top
|
module tank_up_img_blk_mem_gen_top
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
@ -435,7 +431,7 @@ endmodule
|
||||||
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "1024" *)
|
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "1024" *)
|
||||||
(* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
(* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
||||||
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
|
(* downgradeipidentifiedwarnings = "yes" *)
|
||||||
module tank_up_img_blk_mem_gen_v8_4_4
|
module tank_up_img_blk_mem_gen_v8_4_4
|
||||||
(clka,
|
(clka,
|
||||||
rsta,
|
rsta,
|
||||||
|
|
@ -647,7 +643,6 @@ module tank_up_img_blk_mem_gen_v8_4_4
|
||||||
.ena(ena));
|
.ena(ena));
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
|
|
||||||
module tank_up_img_blk_mem_gen_v8_4_4_synth
|
module tank_up_img_blk_mem_gen_v8_4_4_synth
|
||||||
(douta,
|
(douta,
|
||||||
clka,
|
clka,
|
||||||
|
|
|
||||||
|
|
@ -1,10 +1,10 @@
|
||||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
||||||
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
-- Date : Tue Dec 29 16:28:51 2020
|
-- Date : Tue Dec 29 16:28:50 2020
|
||||||
-- Host : cxz666 running 64-bit major release (build 9200)
|
-- Host : cxz666 running 64-bit major release (build 9200)
|
||||||
-- Command : write_vhdl -force -mode funcsim
|
-- Command : write_vhdl -force -mode funcsim -rename_top tank_up_img -prefix
|
||||||
-- E:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/tank_up_img/tank_up_img_sim_netlist.vhdl
|
-- tank_up_img_ tank_up_img_sim_netlist.vhdl
|
||||||
-- Design : tank_up_img
|
-- Design : tank_up_img
|
||||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
|
@ -21,8 +21,6 @@ entity tank_up_img_blk_mem_gen_prim_wrapper_init is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_up_img_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
|
|
||||||
end tank_up_img_blk_mem_gen_prim_wrapper_init;
|
end tank_up_img_blk_mem_gen_prim_wrapper_init;
|
||||||
|
|
||||||
architecture STRUCTURE of tank_up_img_blk_mem_gen_prim_wrapper_init is
|
architecture STRUCTURE of tank_up_img_blk_mem_gen_prim_wrapper_init is
|
||||||
|
|
@ -182,8 +180,6 @@ entity tank_up_img_blk_mem_gen_prim_width is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_up_img_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
|
|
||||||
end tank_up_img_blk_mem_gen_prim_width;
|
end tank_up_img_blk_mem_gen_prim_width;
|
||||||
|
|
||||||
architecture STRUCTURE of tank_up_img_blk_mem_gen_prim_width is
|
architecture STRUCTURE of tank_up_img_blk_mem_gen_prim_width is
|
||||||
|
|
@ -207,8 +203,6 @@ entity tank_up_img_blk_mem_gen_generic_cstr is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_up_img_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
|
|
||||||
end tank_up_img_blk_mem_gen_generic_cstr;
|
end tank_up_img_blk_mem_gen_generic_cstr;
|
||||||
|
|
||||||
architecture STRUCTURE of tank_up_img_blk_mem_gen_generic_cstr is
|
architecture STRUCTURE of tank_up_img_blk_mem_gen_generic_cstr is
|
||||||
|
|
@ -232,8 +226,6 @@ entity tank_up_img_blk_mem_gen_top is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_up_img_blk_mem_gen_top : entity is "blk_mem_gen_top";
|
|
||||||
end tank_up_img_blk_mem_gen_top;
|
end tank_up_img_blk_mem_gen_top;
|
||||||
|
|
||||||
architecture STRUCTURE of tank_up_img_blk_mem_gen_top is
|
architecture STRUCTURE of tank_up_img_blk_mem_gen_top is
|
||||||
|
|
@ -257,8 +249,6 @@ entity tank_up_img_blk_mem_gen_v8_4_4_synth is
|
||||||
ena : in STD_LOGIC;
|
ena : in STD_LOGIC;
|
||||||
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||||
);
|
);
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_up_img_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
|
|
||||||
end tank_up_img_blk_mem_gen_v8_4_4_synth;
|
end tank_up_img_blk_mem_gen_v8_4_4_synth;
|
||||||
|
|
||||||
architecture STRUCTURE of tank_up_img_blk_mem_gen_v8_4_4_synth is
|
architecture STRUCTURE of tank_up_img_blk_mem_gen_v8_4_4_synth is
|
||||||
|
|
@ -491,8 +481,6 @@ entity tank_up_img_blk_mem_gen_v8_4_4 is
|
||||||
attribute C_WRITE_WIDTH_B of tank_up_img_blk_mem_gen_v8_4_4 : entity is 12;
|
attribute C_WRITE_WIDTH_B of tank_up_img_blk_mem_gen_v8_4_4 : entity is 12;
|
||||||
attribute C_XDEVICEFAMILY : string;
|
attribute C_XDEVICEFAMILY : string;
|
||||||
attribute C_XDEVICEFAMILY of tank_up_img_blk_mem_gen_v8_4_4 : entity is "artix7";
|
attribute C_XDEVICEFAMILY of tank_up_img_blk_mem_gen_v8_4_4 : entity is "artix7";
|
||||||
attribute ORIG_REF_NAME : string;
|
|
||||||
attribute ORIG_REF_NAME of tank_up_img_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
|
|
||||||
attribute downgradeipidentifiedwarnings : string;
|
attribute downgradeipidentifiedwarnings : string;
|
||||||
attribute downgradeipidentifiedwarnings of tank_up_img_blk_mem_gen_v8_4_4 : entity is "yes";
|
attribute downgradeipidentifiedwarnings of tank_up_img_blk_mem_gen_v8_4_4 : entity is "yes";
|
||||||
end tank_up_img_blk_mem_gen_v8_4_4;
|
end tank_up_img_blk_mem_gen_v8_4_4;
|
||||||
|
|
|
||||||
|
|
@ -31,6 +31,8 @@ module SegAndLed(
|
||||||
input wire [ 4: 0 ] timer,
|
input wire [ 4: 0 ] timer,
|
||||||
input wire enable_game_classic,
|
input wire enable_game_classic,
|
||||||
input wire enable_game_infinity,
|
input wire enable_game_infinity,
|
||||||
|
input wire player1_tank_en,
|
||||||
|
input wire player2_tank_en,
|
||||||
output wire [ 7: 0 ] AN ,
|
output wire [ 7: 0 ] AN ,
|
||||||
output wire [ 7: 0 ] Segment,
|
output wire [ 7: 0 ] Segment,
|
||||||
output reg [ 15: 0 ] LED
|
output reg [ 15: 0 ] LED
|
||||||
|
|
@ -62,9 +64,9 @@ always @( posedge clk ) begin
|
||||||
2'b00:
|
2'b00:
|
||||||
num <= default_num;
|
num <= default_num;
|
||||||
2'b01:
|
2'b01:
|
||||||
num <= { 4'b1010, 4'b0000, score_classic[ 3: 0 ], 4'b000, 4'b1011, 4'b0000, score_classic[ 7: 4 ], 4'b000 };
|
num <= { 4'b1010, 3'b000, player1_tank_en, score_classic[ 3: 0 ], 4'b000, 4'b1011, 3'b000, player2_tank_en, score_classic[ 7: 4 ], 4'b000 };
|
||||||
2'b10:
|
2'b10:
|
||||||
num <= { 4'b1010, 4'b0000, score_infinity[ 3: 0 ], 4'b000, 4'b1011, score_infinity[ 7: 4 ], 3'b000, timer };
|
num <= { 4'b1010, 3'b000, player1_tank_en, 3'b000, player2_tank_en, score_infinity[ 3: 0 ], 4'b1011, score_infinity[ 7: 4 ], 3'b000, timer };
|
||||||
2'b11:
|
2'b11:
|
||||||
num <= { 4'b1000, 4'b1000, 4'b1000, 4'b1000, 4'b1000, 4'b1000, 4'b1000, 4'b1000 };
|
num <= { 4'b1000, 4'b1000, 4'b1000, 4'b1000, 4'b1000, 4'b1000, 4'b1000, 4'b1000 };
|
||||||
default num <= 0;
|
default num <= 0;
|
||||||
|
|
|
||||||
|
|
@ -41,17 +41,23 @@ wire item_addtime;
|
||||||
wire item_test;
|
wire item_test;
|
||||||
wire [ 10: 0 ] vgaH, vgaV;
|
wire [ 10: 0 ] vgaH, vgaV;
|
||||||
wire [ 11: 0 ] VGAData;
|
wire [ 11: 0 ] VGAData;
|
||||||
wire [ 11: 0 ] tankData;
|
|
||||||
wire [ 11: 0 ] backgroundData;
|
wire [ 11: 0 ] backgroundData;
|
||||||
wire [ 1 : 0 ] player1_tank_dir, player2_tank_dir;
|
wire [ 1 : 0 ] player1_tank_dir, player2_tank_dir;
|
||||||
|
wire [ 1: 0 ] enermy1_tank_dir, enermy2_tank_dir, enermy3_tank_dir, enermy4_tank_dir;
|
||||||
wire [ 10: 0 ] player1_tank_H, player1_tank_V, player2_tank_H, player2_tank_V;
|
wire [ 10: 0 ] player1_tank_H, player1_tank_V, player2_tank_H, player2_tank_V;
|
||||||
wire [ 11: 0 ] player1_bullet_data;
|
wire [ 10: 0 ] enermy1_tank_H, enermy1_tank_V, enermy2_tank_H, enermy2_tank_V, enermy3_tank_H, enermy3_tank_V, enermy4_tank_H, enermy4_tank_V;
|
||||||
|
wire [ 11: 0 ] player1_bullet_data, player2_bullet_data;
|
||||||
|
wire [ 11: 0 ] enermy1_bullet_data, enermy2_bullet_data, enermy3_bullet_data, enermy4_bullet_data;
|
||||||
wire [ 11: 0 ] player1_tank_data, player2_tank_data;
|
wire [ 11: 0 ] player1_tank_data, player2_tank_data;
|
||||||
|
wire [ 11: 0 ] enermy1_tank_data, enermy2_tank_data, enermy3_tank_data, enermy4_tank_data;
|
||||||
wire [ 2: 0 ] player1_tank_dir_feedback, player2_tank_dir_feedback;
|
wire [ 2: 0 ] player1_tank_dir_feedback, player2_tank_dir_feedback;
|
||||||
|
wire [ 2: 0 ] enermy1_tank_dir_feedback, enermy2_tank_dir_feedback, enermy3_tank_dir_feedback, enermy4_tank_dir_feedback;
|
||||||
wire player1_tank_en, player2_tank_en;
|
wire player1_tank_en, player2_tank_en;
|
||||||
wire player1_tank_en_feedback, player2_tank_en_feedback;
|
wire player1_tank_en_feedback, player2_tank_en_feedback;
|
||||||
|
wire enermy1_tank_en, enermy2_tank_en, enermy3_tank_en, enermy4_tank_en;
|
||||||
|
wire enermy1_tank_en_feedback, enermy2_tank_en_feedback, enermy3_tank_en_feedback, enermy4_tank_en_feedback;
|
||||||
wire [ 2: 0 ] player1_tank_moving_direction, player2_tank_moving_direction;
|
wire [ 2: 0 ] player1_tank_moving_direction, player2_tank_moving_direction;
|
||||||
|
wire [ 2: 0 ] enermy1_tank_moving_direction, enermy2_tank_moving_direction, enermy3_tank_moving_direction, enermy4_tank_moving_direction;
|
||||||
wire reset_n;
|
wire reset_n;
|
||||||
|
|
||||||
wire gameover_classic, gameover_infinity; //stop the game signal
|
wire gameover_classic, gameover_infinity; //stop the game signal
|
||||||
|
|
@ -69,8 +75,8 @@ wire enable_reward;
|
||||||
|
|
||||||
wire [ 3: 0 ] scorea1, scoreb1;
|
wire [ 3: 0 ] scorea1, scoreb1;
|
||||||
wire [ 3: 0 ] scorea2, scoreb2;
|
wire [ 3: 0 ] scorea2, scoreb2;
|
||||||
wire [ 3: 0 ] scorea3, scoreb3;
|
wire [ 3: 0 ] scorec1, scorec2;
|
||||||
wire [ 3: 0 ] scorea4, scoreb4;
|
wire [ 3: 0 ] scored1, scored2;
|
||||||
wire [ 3: 0 ] player1_HP, player2_HP;
|
wire [ 3: 0 ] player1_HP, player2_HP;
|
||||||
|
|
||||||
wire [ 15: 0 ] LED_classic, LED_infinity;
|
wire [ 15: 0 ] LED_classic, LED_infinity;
|
||||||
|
|
@ -181,7 +187,7 @@ game_logic_infinity u_game_logic_infinity(
|
||||||
vga_driver u_vga_driver(
|
vga_driver u_vga_driver(
|
||||||
.clk_vga( clk_VGA ),
|
.clk_vga( clk_VGA ),
|
||||||
.rst_n( 1'b1 ),
|
.rst_n( 1'b1 ),
|
||||||
.vga_en( 1'b1 ),
|
.vga_en( ),
|
||||||
.HSync( Hsync ),
|
.HSync( Hsync ),
|
||||||
.VSync( Vsync ),
|
.VSync( Vsync ),
|
||||||
.vgaRed( VGARed ),
|
.vgaRed( VGARed ),
|
||||||
|
|
@ -207,6 +213,19 @@ vga_data_selector u_vga_data_selector(
|
||||||
.in2( player1_tank_data ),
|
.in2( player1_tank_data ),
|
||||||
.in3( player1_bullet_data ),
|
.in3( player1_bullet_data ),
|
||||||
.in4( player2_tank_data ),
|
.in4( player2_tank_data ),
|
||||||
|
.in5( player2_bullet_data ),
|
||||||
|
.in6( enermy1_tank_data ),
|
||||||
|
.in7( enermy2_tank_data ),
|
||||||
|
.in8( enermy3_tank_data ),
|
||||||
|
.in9( enermy4_tank_data ),
|
||||||
|
.in10(),
|
||||||
|
.in11(),
|
||||||
|
.in12(),
|
||||||
|
.in13(),
|
||||||
|
.in14(),
|
||||||
|
.in15(),
|
||||||
|
.in16(),
|
||||||
|
.in17(),
|
||||||
.out( VGAData )
|
.out( VGAData )
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
@ -214,6 +233,8 @@ tank_display u_tank1_display(
|
||||||
.clk( clk ),
|
.clk( clk ),
|
||||||
.tankDir( player1_tank_dir ),
|
.tankDir( player1_tank_dir ),
|
||||||
.tank_destroyed( ~player1_tank_en ),
|
.tank_destroyed( ~player1_tank_en ),
|
||||||
|
.mode( mode ),
|
||||||
|
.tank_revive( player1_revive ),
|
||||||
.vgaH( vgaH ),
|
.vgaH( vgaH ),
|
||||||
.vgaV( vgaV ),
|
.vgaV( vgaV ),
|
||||||
.tankH( player1_tank_H ),
|
.tankH( player1_tank_H ),
|
||||||
|
|
@ -225,12 +246,63 @@ tank_display u_tank2_display(
|
||||||
.clk( clk ),
|
.clk( clk ),
|
||||||
.tankDir( player2_tank_dir ),
|
.tankDir( player2_tank_dir ),
|
||||||
.tank_destroyed( ~player2_tank_en ),
|
.tank_destroyed( ~player2_tank_en ),
|
||||||
|
.mode( mode ),
|
||||||
|
.tank_revive( player1_revive ),
|
||||||
.vgaH( vgaH ),
|
.vgaH( vgaH ),
|
||||||
.vgaV( vgaV ),
|
.vgaV( vgaV ),
|
||||||
.tankH( player2_tank_H ),
|
.tankH( player2_tank_H ),
|
||||||
.tankV( player2_tank_V ),
|
.tankV( player2_tank_V ),
|
||||||
.tankData( player2_tank_data )
|
.tankData( player2_tank_data )
|
||||||
);
|
);
|
||||||
|
tank_display enermy1_tank_display(
|
||||||
|
.clk( clk ),
|
||||||
|
.tankDir( enermy1_tank_dir ),
|
||||||
|
.tank_destroyed( ~enermy1_tank_en ),
|
||||||
|
.mode( mode ),
|
||||||
|
.tank_revive( player1_revive ),
|
||||||
|
.vgaH( vgaH ),
|
||||||
|
.vgaV( vgaV ),
|
||||||
|
.tankH( enermy1_tank_H ),
|
||||||
|
.tankV( enermy1_tank_V ),
|
||||||
|
.tankData( enermy1_tank_data )
|
||||||
|
);
|
||||||
|
|
||||||
|
tank_display enermy2_tank_display(
|
||||||
|
.clk( clk ),
|
||||||
|
.tankDir( enermy2_tank_dir ),
|
||||||
|
.tank_destroyed( ~enermy2_tank_en ),
|
||||||
|
.mode( mode ),
|
||||||
|
.tank_revive( player1_revive ),
|
||||||
|
.vgaH( vgaH ),
|
||||||
|
.vgaV( vgaV ),
|
||||||
|
.tankH( enermy2_tank_H ),
|
||||||
|
.tankV( enermy2_tank_V ),
|
||||||
|
.tankData( enermy2_tank_data )
|
||||||
|
);
|
||||||
|
tank_display enermy3_tank_display(
|
||||||
|
.clk( clk ),
|
||||||
|
.tankDir( enermy3_tank_dir ),
|
||||||
|
.tank_destroyed( ~enermy3_tank_en ),
|
||||||
|
.mode( mode ),
|
||||||
|
.tank_revive( player1_revive ),
|
||||||
|
.vgaH( vgaH ),
|
||||||
|
.vgaV( vgaV ),
|
||||||
|
.tankH( enermy3_tank_H ),
|
||||||
|
.tankV( enermy3_tank_V ),
|
||||||
|
.tankData( enermy3_tank_data )
|
||||||
|
);
|
||||||
|
tank_display enermy4_tank_display(
|
||||||
|
.clk( clk ),
|
||||||
|
.tankDir( enermy4_tank_dir ),
|
||||||
|
.tank_destroyed( ~enermy4_tank_en ),
|
||||||
|
.mode( mode ),
|
||||||
|
.tank_revive( player1_revive ),
|
||||||
|
.vgaH( vgaH ),
|
||||||
|
.vgaV( vgaV ),
|
||||||
|
.tankH( enermy4_tank_H ),
|
||||||
|
.tankV( enermy4_tank_V ),
|
||||||
|
.tankData( enermy4_tank_data )
|
||||||
|
);
|
||||||
|
|
||||||
tank_move player1_tank_move(
|
tank_move player1_tank_move(
|
||||||
clk, reset_n, 1,
|
clk, reset_n, 1,
|
||||||
|
|
@ -246,6 +318,32 @@ tank_move player2_tank_move(
|
||||||
player2_tank_H, player2_tank_V, player2_tank_moving_direction
|
player2_tank_H, player2_tank_V, player2_tank_moving_direction
|
||||||
);
|
);
|
||||||
|
|
||||||
|
tank_move enermy1_tank_move(
|
||||||
|
clk, reset_n, 1,
|
||||||
|
0, 0,
|
||||||
|
enermy1_tank_dir, enermy1_tank_en, enermy1_tank_move_en, enermy1_moving,
|
||||||
|
enermy1_tank_H, enermy1_tank_V, enermy1_tank_moving_direction
|
||||||
|
);
|
||||||
|
|
||||||
|
tank_move enermy2_tank_move(
|
||||||
|
clk, reset_n, 1,
|
||||||
|
540, 0,
|
||||||
|
enermy2_tank_dir, enermy2_tank_en, enermy2_tank_move_en, enermy2_moving,
|
||||||
|
enermy2_tank_H, enermy2_tank_V, enermy2_tank_moving_direction
|
||||||
|
);
|
||||||
|
tank_move enermy3_tank_move(
|
||||||
|
clk, reset_n, 1,
|
||||||
|
0, 350,
|
||||||
|
enermy3_tank_dir, enermy3_tank_en, enermy3_tank_move_en, enermy3_moving,
|
||||||
|
enermy3_tank_H, enermy3_tank_V, enermy3_tank_moving_direction
|
||||||
|
);
|
||||||
|
|
||||||
|
tank_move enermy4_tank_move(
|
||||||
|
clk, reset_n, 1,
|
||||||
|
540, 350,
|
||||||
|
enermy4_tank_dir, enermy4_tank_en, enermy4_tank_move_en, enermy4_moving,
|
||||||
|
enermy4_tank_H, enermy4_tank_V, enermy4_tank_moving_direction
|
||||||
|
);
|
||||||
|
|
||||||
control u_control(
|
control u_control(
|
||||||
.clk( clk ),
|
.clk( clk ),
|
||||||
|
|
@ -260,24 +358,47 @@ control u_control(
|
||||||
|
|
||||||
wire player1_bullet_en_feedback, player2_bullet_en_feedback;
|
wire player1_bullet_en_feedback, player2_bullet_en_feedback;
|
||||||
wire player1_bullet_en, player2_bullet_en;
|
wire player1_bullet_en, player2_bullet_en;
|
||||||
wire [ 10: 0 ] player1_bullet_H, player1_bullet_V;
|
wire enermy1_bullet_en_feedback, enermy2_bullet_en_feedback, enermy3_bullet_en_feedback, enermy4_bullet_en_feedback;
|
||||||
wire [ 2: 0 ] player1_bullet_dir;
|
wire enermy1_bullet_en, enermy2_bullet_en, enermy3_bullet_en, enermy4_bullet_en;
|
||||||
|
wire [ 10: 0 ] player1_bullet_H, player1_bullet_V, player2_bullet_H, player2_bullet_V;
|
||||||
|
wire [ 10: 0 ] enermy1_bullet_H, enermy1_bullet_V, enermy2_bullet_H, enermy2_bullet_V,
|
||||||
|
enermy3_bullet_H, enermy3_bullet_V, enermy4_bullet_H, enermy4_bullet_V;
|
||||||
|
wire [ 2: 0 ] player1_bullet_dir, player2_bullet_dir;
|
||||||
|
wire [ 2: 0 ] enermy1_bullet_dir, enermy2_bullet_dir, enermy3_bullet_dir, enermy4_bullet_dir;
|
||||||
wire player1_revive, player2_revive;
|
wire player1_revive, player2_revive;
|
||||||
assign player1_revive = 0;
|
wire enermy1_revive, enermy2_revive, enermy3_revive, enermy4_revive;
|
||||||
assign player2_revive = 0;
|
wire player1_scored, player2_scored;
|
||||||
|
|
||||||
|
|
||||||
control_signals u_control_signals(
|
control_signals u_control_signals(
|
||||||
clk, rst_n,
|
clk, reset_n,
|
||||||
player1_bullet_H, player1_bullet_V, player2_bullet_H, player2_bullet_V,
|
player1_bullet_H, player1_bullet_V, player2_bullet_H, player2_bullet_V,
|
||||||
|
enermy1_bullet_H, enermy1_bullet_V,
|
||||||
|
enermy2_bullet_H, enermy2_bullet_V,
|
||||||
|
enermy3_bullet_H, enermy3_bullet_V,
|
||||||
|
enermy4_bullet_H, enermy4_bullet_V,
|
||||||
player1_bullet_dir, player2_bullet_dir,
|
player1_bullet_dir, player2_bullet_dir,
|
||||||
|
enermy1_bullet_dir, enermy2_bullet_dir, enermy3_bullet_dir, enermy4_bullet_dir,
|
||||||
player1_tank_H, player1_tank_V, player2_tank_H, player2_tank_V,
|
player1_tank_H, player1_tank_V, player2_tank_H, player2_tank_V,
|
||||||
|
enermy1_tank_H, enermy1_tank_V,
|
||||||
|
enermy2_tank_H, enermy2_tank_V,
|
||||||
|
enermy3_tank_H, enermy3_tank_V,
|
||||||
|
enermy4_tank_H, enermy4_tank_V,
|
||||||
// player1_tank_en, player2_tank_en,
|
// player1_tank_en, player2_tank_en,
|
||||||
player1_moving, player2_moving,
|
player1_moving, player2_moving,
|
||||||
|
enermy1_moving, enermy2_moving, enermy3_moving, enermy4_moving,
|
||||||
player1_tank_dir, player2_tank_dir,
|
player1_tank_dir, player2_tank_dir,
|
||||||
|
enermy1_tank_dir, enermy2_tank_dir, enermy3_tank_dir, enermy4_tank_dir,
|
||||||
player1_revive, player2_revive,
|
player1_revive, player2_revive,
|
||||||
|
enermy1_revive, enermy2_revive, enermy3_revive, enermy4_revive,
|
||||||
player1_tank_en, player2_tank_en,
|
player1_tank_en, player2_tank_en,
|
||||||
|
enermy1_tank_en, enermy2_tank_en, enermy3_tank_en, enermy4_tank_en,
|
||||||
player1_tank_move_en, player2_tank_move_en,
|
player1_tank_move_en, player2_tank_move_en,
|
||||||
player1_bullet_en, player2_bullet_en
|
enermy1_tank_move_en, enermy2_tank_move_en, enermy3_tank_move_en, enermy4_tank_move_en,
|
||||||
|
player1_bullet_en, player2_bullet_en,
|
||||||
|
enermy1_bullet_en, enermy2_bullet_en, enermy3_bullet_en, enermy4_bullet_en, player1_scored, player2_scored
|
||||||
|
// scorea1, scorea2, scoreb1, scoreb2, scorec1, scorec2, scored1, scored2
|
||||||
|
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -286,7 +407,7 @@ bullet_control bullet_player1(
|
||||||
.reset_n( 1 ),
|
.reset_n( 1 ),
|
||||||
.tank_H( player1_tank_H ),
|
.tank_H( player1_tank_H ),
|
||||||
.tank_V( player1_tank_V ),
|
.tank_V( player1_tank_V ),
|
||||||
// .tank_en(player1_tank_en),
|
.tank_en( player1_tank_en ),
|
||||||
.tank_dir( player1_tank_dir ),
|
.tank_dir( player1_tank_dir ),
|
||||||
.tank_fire( player1_fire ),
|
.tank_fire( player1_fire ),
|
||||||
.vgaV( vgaV ),
|
.vgaV( vgaV ),
|
||||||
|
|
@ -298,9 +419,34 @@ bullet_control bullet_player1(
|
||||||
.bullet_V_feedback( player1_bullet_V ),
|
.bullet_V_feedback( player1_bullet_V ),
|
||||||
.bullet_direction( player1_bullet_dir )
|
.bullet_direction( player1_bullet_dir )
|
||||||
);
|
);
|
||||||
|
bullet_control bullet_player2(
|
||||||
|
.clk( clk ),
|
||||||
|
.reset_n( 1 ),
|
||||||
|
.tank_H( player2_tank_H ),
|
||||||
|
.tank_V( player2_tank_V ),
|
||||||
|
.tank_en( player2_tank_en ),
|
||||||
|
.tank_dir( player2_tank_dir ),
|
||||||
|
.tank_fire( player2_fire ),
|
||||||
|
.vgaV( vgaV ),
|
||||||
|
.vgaH( vgaH ),
|
||||||
|
.start( 1 ),
|
||||||
|
.ready( player2_bullet_en ),
|
||||||
|
.bulletData( player2_bullet_data ),
|
||||||
|
.bullet_H_feedback( player2_bullet_H ),
|
||||||
|
.bullet_V_feedback( player2_bullet_V ),
|
||||||
|
.bullet_direction( player2_bullet_dir )
|
||||||
|
);
|
||||||
|
cal_score u_cal_score(
|
||||||
|
clk, reset_n, enermy1_tank_en, enermy2_tank_en, enermy3_tank_en, enermy4_tank_en,
|
||||||
|
player1_scored, player2_scored, scorea1, scorea2, scoreb1, scoreb2, scorec1, scorec2, scored1, scored2
|
||||||
|
);
|
||||||
|
|
||||||
|
tank_generate u_tank_generate(
|
||||||
|
clk_4Hz, player1_tank_en, player2_tank_en,
|
||||||
|
enermy1_tank_en, enermy2_tank_en, enermy3_tank_en, enermy4_tank_en,
|
||||||
|
player1_revive, player2_revive, enermy1_revive, enermy2_revive,
|
||||||
|
enermy3_revive, enermy4_revive
|
||||||
|
);
|
||||||
assign item_faster = 0;
|
assign item_faster = 0;
|
||||||
assign item_addtime = 0;
|
assign item_addtime = 0;
|
||||||
assign item_invincible = 0;
|
assign item_invincible = 0;
|
||||||
|
|
@ -337,9 +483,10 @@ SegAndLed u_SegAndLed(
|
||||||
.default_num( num ), //when mode ==00(before begin mode) then output num ,you can also use it as debug
|
.default_num( num ), //when mode ==00(before begin mode) then output num ,you can also use it as debug
|
||||||
.enable_game_classic( enable_game_classic ),
|
.enable_game_classic( enable_game_classic ),
|
||||||
.enable_game_infinity( enable_game_infinity ),
|
.enable_game_infinity( enable_game_infinity ),
|
||||||
|
.player1_tank_en( player1_tank_en ),
|
||||||
|
.player2_tank_en( player2_tank_en ),
|
||||||
.AN( AN ),
|
.AN( AN ),
|
||||||
.Segment( SEGMENT1 ),
|
.Segment( SEGMENT1 ),
|
||||||
.LED( LED )
|
.LED( LED )
|
||||||
|
|
||||||
);
|
);
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -6,32 +6,32 @@ module bullet_control(
|
||||||
input reset_n,
|
input reset_n,
|
||||||
input start,
|
input start,
|
||||||
|
|
||||||
input [10:0] tank_H,
|
input [ 10: 0 ] tank_H,
|
||||||
input [10:0] tank_V,
|
input [ 10: 0 ] tank_V,
|
||||||
input tank_en,
|
input tank_en,
|
||||||
input [1:0] tank_dir,
|
input [ 1: 0 ] tank_dir,
|
||||||
input tank_fire,
|
input tank_fire,
|
||||||
input [10:0] vgaH,
|
input [ 10: 0 ] vgaH,
|
||||||
input [10:0] vgaV,
|
input [ 10: 0 ] vgaV,
|
||||||
input ready,
|
input ready,
|
||||||
|
|
||||||
output [11:0] bulletData,
|
output [ 11: 0 ] bulletData,
|
||||||
output reg [10:0] bullet_H_feedback,
|
output reg [ 10: 0 ] bullet_H_feedback,
|
||||||
output reg [10:0] bullet_V_feedback,
|
output reg [ 10: 0 ] bullet_V_feedback,
|
||||||
output reg [2:0] bullet_direction
|
output reg [ 2: 0 ] bullet_direction
|
||||||
);
|
);
|
||||||
|
|
||||||
parameter BULLET_LONGER = 10;
|
parameter BULLET_LONGER = 10;
|
||||||
parameter BULLET_SHORTER = 5;
|
parameter BULLET_SHORTER = 5;
|
||||||
parameter BULLET_LONGER_CENTER = 5;
|
parameter BULLET_LONGER_CENTER = 5;
|
||||||
parameter BULLET_SHORTER_CENTER = 2;
|
parameter BULLET_SHORTER_CENTER = 2;
|
||||||
parameter HEIGHT = 480;
|
parameter HEIGHT = 480;
|
||||||
parameter WIDTH = 640;
|
parameter WIDTH = 640;
|
||||||
parameter TANK_V_CENTER = 16;
|
parameter TANK_V_CENTER = 16;
|
||||||
parameter TANK_H_CENTER = 16;
|
parameter TANK_H_CENTER = 16;
|
||||||
parameter TANK_HEIGHT = 32, TANK_WIDTH = 32;
|
parameter TANK_HEIGHT = 32, TANK_WIDTH = 32;
|
||||||
|
|
||||||
localparam
|
localparam
|
||||||
UP = 3'd0,
|
UP = 3'd0,
|
||||||
DOWN = 3'd1,
|
DOWN = 3'd1,
|
||||||
LEFT = 3'd2,
|
LEFT = 3'd2,
|
||||||
|
|
@ -39,43 +39,60 @@ module bullet_control(
|
||||||
WAIT = 3'd4,
|
WAIT = 3'd4,
|
||||||
READY = 3'd5;
|
READY = 3'd5;
|
||||||
|
|
||||||
reg counter_en;
|
reg counter_en;
|
||||||
reg [31:0] counter;
|
reg [ 31: 0 ] counter;
|
||||||
reg [2:0] current_state, next_state;
|
reg [ 2: 0 ] current_state, next_state;
|
||||||
|
|
||||||
always @(posedge clk) begin:state_flip_flop
|
always @( posedge clk ) begin:state_flip_flop
|
||||||
if(!reset_n) current_state <= WAIT;
|
if ( !reset_n ) begin
|
||||||
// else if(!tank_en) current_state <= WAIT;
|
current_state <= WAIT;
|
||||||
else current_state <= next_state;
|
end
|
||||||
|
else if ( !tank_en ) begin
|
||||||
|
current_state <= WAIT;
|
||||||
end
|
end
|
||||||
|
|
||||||
always @(*) begin: state_table
|
|
||||||
case(current_state)
|
|
||||||
WAIT: next_state = start ? READY : WAIT;
|
|
||||||
READY: begin
|
|
||||||
if(!tank_fire)
|
|
||||||
next_state = READY;
|
|
||||||
else begin
|
else begin
|
||||||
case(tank_dir)
|
current_state <= next_state;
|
||||||
2'b00: next_state = UP;
|
|
||||||
2'b01: next_state = DOWN;
|
|
||||||
2'b10: next_state = LEFT;
|
|
||||||
2'b11: next_state = RIGHT;
|
|
||||||
endcase
|
|
||||||
end
|
|
||||||
end
|
|
||||||
UP: next_state = ready ? READY : UP;
|
|
||||||
DOWN: next_state = ready ? READY : DOWN;
|
|
||||||
LEFT: next_state = ready ? READY : LEFT;
|
|
||||||
RIGHT: next_state = ready ? READY : RIGHT;
|
|
||||||
default: next_state = READY;
|
|
||||||
endcase
|
|
||||||
end
|
end
|
||||||
|
end
|
||||||
|
|
||||||
always @(*) begin: bullet_logic
|
always @( * ) begin: state_table
|
||||||
|
case ( current_state )
|
||||||
|
WAIT:
|
||||||
|
next_state = start ? READY : WAIT;
|
||||||
|
READY: begin
|
||||||
|
if ( !tank_fire ) begin
|
||||||
|
next_state = READY;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
case ( tank_dir )
|
||||||
|
2'b00:
|
||||||
|
next_state = UP;
|
||||||
|
2'b01:
|
||||||
|
next_state = DOWN;
|
||||||
|
2'b10:
|
||||||
|
next_state = LEFT;
|
||||||
|
2'b11:
|
||||||
|
next_state = RIGHT;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
UP:
|
||||||
|
next_state = ready ? READY : UP;
|
||||||
|
DOWN:
|
||||||
|
next_state = ready ? READY : DOWN;
|
||||||
|
LEFT:
|
||||||
|
next_state = ready ? READY : LEFT;
|
||||||
|
RIGHT:
|
||||||
|
next_state = ready ? READY : RIGHT;
|
||||||
|
default:
|
||||||
|
next_state = READY;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
always @( * ) begin: bullet_logic
|
||||||
counter_en = 0;
|
counter_en = 0;
|
||||||
bullet_direction = 3'b111;
|
bullet_direction = 3'b111;
|
||||||
case(current_state)
|
case ( current_state )
|
||||||
READY: begin
|
READY: begin
|
||||||
counter_en = 0;
|
counter_en = 0;
|
||||||
bullet_direction = 3'b111;
|
bullet_direction = 3'b111;
|
||||||
|
|
@ -97,19 +114,19 @@ module bullet_control(
|
||||||
bullet_direction = 3'b011;
|
bullet_direction = 3'b011;
|
||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
|
||||||
reg bullet_move_en;
|
reg bullet_move_en;
|
||||||
always @(posedge clk) begin: counter_logic
|
always @( posedge clk ) begin: counter_logic
|
||||||
if(!reset_n) begin
|
if ( !reset_n ) begin
|
||||||
counter <= 0;
|
counter <= 0;
|
||||||
bullet_move_en <= 0;
|
bullet_move_en <= 0;
|
||||||
end
|
end
|
||||||
else if(counter == 1_000_000) begin
|
else if ( counter == 1_000_000 ) begin
|
||||||
counter <= 0;
|
counter <= 0;
|
||||||
bullet_move_en <= 1;
|
bullet_move_en <= 1;
|
||||||
end
|
end
|
||||||
else if(counter_en == 0) begin
|
else if ( counter_en == 0 ) begin
|
||||||
counter <= 0;
|
counter <= 0;
|
||||||
bullet_move_en <= 0;
|
bullet_move_en <= 0;
|
||||||
end
|
end
|
||||||
|
|
@ -117,32 +134,32 @@ module bullet_control(
|
||||||
counter <= counter + 1;
|
counter <= counter + 1;
|
||||||
bullet_move_en <= 0;
|
bullet_move_en <= 0;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
always @(posedge clk) begin: bullet_move
|
always @( posedge clk ) begin: bullet_move
|
||||||
if(bullet_direction[2]) begin //if no direction
|
if ( bullet_direction[ 2 ] ) begin //if no direction
|
||||||
case(tank_dir)
|
case ( tank_dir )
|
||||||
2'b00: begin
|
2'b00: begin
|
||||||
bullet_H_feedback <= tank_H + TANK_H_CENTER - BULLET_SHORTER_CENTER;
|
bullet_H_feedback <= tank_H + TANK_H_CENTER - BULLET_SHORTER_CENTER;
|
||||||
bullet_V_feedback <= ( (tank_V >= BULLET_LONGER) ? (tank_V - BULLET_LONGER) : 0);
|
bullet_V_feedback <= ( ( tank_V >= BULLET_LONGER ) ? ( tank_V - BULLET_LONGER ) : 0 );
|
||||||
end
|
end
|
||||||
2'b01: begin
|
2'b01: begin
|
||||||
bullet_H_feedback <= tank_H + TANK_H_CENTER - BULLET_SHORTER_CENTER;
|
bullet_H_feedback <= tank_H + TANK_H_CENTER - BULLET_SHORTER_CENTER;
|
||||||
bullet_V_feedback <= ( (tank_V + TANK_HEIGHT + BULLET_LONGER <= HEIGHT) ? (tank_V + TANK_HEIGHT + BULLET_LONGER) : HEIGHT);
|
bullet_V_feedback <= ( ( tank_V + TANK_HEIGHT + BULLET_LONGER <= HEIGHT ) ? ( tank_V + TANK_HEIGHT + BULLET_LONGER ) : HEIGHT );
|
||||||
end
|
end
|
||||||
2'b10: begin
|
2'b10: begin
|
||||||
bullet_H_feedback <= ( (tank_H >= BULLET_LONGER) ? (tank_H - BULLET_LONGER) : 0);
|
bullet_H_feedback <= ( ( tank_H >= BULLET_LONGER ) ? ( tank_H - BULLET_LONGER ) : 0 );
|
||||||
bullet_V_feedback <= tank_V + TANK_V_CENTER - BULLET_SHORTER_CENTER;
|
bullet_V_feedback <= tank_V + TANK_V_CENTER - BULLET_SHORTER_CENTER;
|
||||||
end
|
end
|
||||||
2'b11: begin
|
2'b11: begin
|
||||||
bullet_H_feedback <= ( (tank_H + BULLET_LONGER + TANK_WIDTH <= WIDTH) ? (tank_H + BULLET_LONGER + TANK_WIDTH) : WIDTH ) ;
|
bullet_H_feedback <= ( ( tank_H + BULLET_LONGER + TANK_WIDTH <= WIDTH ) ? ( tank_H + BULLET_LONGER + TANK_WIDTH ) : WIDTH ) ;
|
||||||
bullet_V_feedback <= tank_V + TANK_V_CENTER - BULLET_SHORTER_CENTER;
|
bullet_V_feedback <= tank_V + TANK_V_CENTER - BULLET_SHORTER_CENTER;
|
||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
else if(bullet_move_en) begin
|
else if ( bullet_move_en ) begin
|
||||||
case(bullet_direction[1:0])
|
case ( bullet_direction[ 1: 0 ] )
|
||||||
2'b00:begin
|
2'b00: begin
|
||||||
bullet_V_feedback <= bullet_V_feedback - 1;
|
bullet_V_feedback <= bullet_V_feedback - 1;
|
||||||
bullet_H_feedback <= bullet_H_feedback;
|
bullet_H_feedback <= bullet_H_feedback;
|
||||||
end
|
end
|
||||||
|
|
@ -165,57 +182,57 @@ module bullet_control(
|
||||||
bullet_H_feedback <= bullet_H_feedback;
|
bullet_H_feedback <= bullet_H_feedback;
|
||||||
bullet_V_feedback <= bullet_V_feedback;
|
bullet_V_feedback <= bullet_V_feedback;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
wire [11:0] UP_data, DOWN_data, LEFT_data, RIGHT_data;
|
wire [ 11: 0 ] UP_data, DOWN_data, LEFT_data, RIGHT_data;
|
||||||
wire [7:0] bulletAddr;
|
wire [ 7: 0 ] bulletAddr;
|
||||||
reg bullet_bound;
|
reg bullet_bound;
|
||||||
|
|
||||||
always @(*) begin
|
always @( * ) begin
|
||||||
case(bullet_direction[1:0])
|
case ( bullet_direction[ 1: 0 ] )
|
||||||
2'b00: begin
|
2'b00: begin
|
||||||
bullet_bound <= (bullet_H_feedback <= vgaH && bullet_H_feedback > vgaH - BULLET_SHORTER && bullet_V_feedback <= vgaV && bullet_V_feedback > vgaV - BULLET_LONGER) ? 1 : 0;
|
bullet_bound <= ( bullet_H_feedback <= vgaH && bullet_H_feedback > vgaH - BULLET_SHORTER && bullet_V_feedback <= vgaV && bullet_V_feedback > vgaV - BULLET_LONGER ) ? 1 : 0;
|
||||||
end
|
end
|
||||||
2'b01: begin
|
2'b01: begin
|
||||||
bullet_bound <= (bullet_H_feedback <= vgaH && bullet_H_feedback > vgaH - BULLET_SHORTER && bullet_V_feedback <= vgaV && bullet_V_feedback > vgaV - BULLET_LONGER) ? 1 : 0;
|
bullet_bound <= ( bullet_H_feedback <= vgaH && bullet_H_feedback > vgaH - BULLET_SHORTER && bullet_V_feedback <= vgaV && bullet_V_feedback > vgaV - BULLET_LONGER ) ? 1 : 0;
|
||||||
end
|
end
|
||||||
2'b10: begin
|
2'b10: begin
|
||||||
bullet_bound <= (bullet_H_feedback <= vgaH && bullet_H_feedback > vgaH - BULLET_LONGER && bullet_V_feedback > vgaV - BULLET_SHORTER) ? 1 : 0;
|
bullet_bound <= ( bullet_H_feedback <= vgaH && bullet_H_feedback > vgaH - BULLET_LONGER && bullet_V_feedback > vgaV - BULLET_SHORTER && bullet_V_feedback <= vgaV ) ? 1 : 0;
|
||||||
end
|
end
|
||||||
2'b11: begin
|
2'b11: begin
|
||||||
bullet_bound <= (bullet_H_feedback <= vgaH && bullet_H_feedback > vgaH - BULLET_LONGER && bullet_V_feedback <= vgaV && bullet_V_feedback > vgaV - BULLET_SHORTER) ? 1 : 0;
|
bullet_bound <= ( bullet_H_feedback <= vgaH && bullet_H_feedback > vgaH - BULLET_LONGER && bullet_V_feedback <= vgaV && bullet_V_feedback > vgaV - BULLET_SHORTER ) ? 1 : 0;
|
||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
reg [5:0] bullet_addr;
|
reg [ 5: 0 ] bullet_addr;
|
||||||
always @(*) begin
|
always @( * ) begin
|
||||||
case(bullet_direction[1:0])
|
case ( bullet_direction[ 1: 0 ] )
|
||||||
2'b00: begin
|
2'b00: begin
|
||||||
bullet_addr <= bullet_bound ? ( (vgaV - bullet_V_feedback) * BULLET_SHORTER + (vgaH - bullet_H_feedback) ) : 15;
|
bullet_addr <= bullet_bound ? ( ( vgaV - bullet_V_feedback ) * BULLET_SHORTER + ( vgaH - bullet_H_feedback ) ) : 15;
|
||||||
end
|
end
|
||||||
2'b01: begin
|
2'b01: begin
|
||||||
bullet_addr <= bullet_bound ? ( (vgaV - bullet_V_feedback) * BULLET_SHORTER + (vgaH - bullet_H_feedback) ) : 15;
|
bullet_addr <= bullet_bound ? ( ( vgaV - bullet_V_feedback ) * BULLET_SHORTER + ( vgaH - bullet_H_feedback ) ) : 15;
|
||||||
end
|
end
|
||||||
2'b10: begin
|
2'b10: begin
|
||||||
bullet_addr <= bullet_bound ? ( (vgaV - bullet_V_feedback) * BULLET_LONGER + (vgaH - bullet_H_feedback) ) : 15;
|
bullet_addr <= bullet_bound ? ( ( vgaV - bullet_V_feedback ) * BULLET_LONGER + ( vgaH - bullet_H_feedback ) ) : 15;
|
||||||
end
|
end
|
||||||
2'b11: begin
|
2'b11: begin
|
||||||
bullet_addr <= bullet_bound ? ( (vgaV - bullet_V_feedback) * BULLET_LONGER + (vgaH - bullet_H_feedback) ): 15;
|
bullet_addr <= bullet_bound ? ( ( vgaV - bullet_V_feedback ) * BULLET_LONGER + ( vgaH - bullet_H_feedback ) ) : 15;
|
||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
|
|
||||||
end
|
end
|
||||||
|
|
||||||
wire [11:0] outData;
|
wire [ 11: 0 ] outData;
|
||||||
|
|
||||||
bullet_left_img left(.addra(bullet_addr), .clka(clk), .douta(LEFT_data), .ena(1'b1));
|
bullet_left_img left( .addra( bullet_addr ), .clka( clk ), .douta( LEFT_data ), .ena( 1'b1 ) );
|
||||||
bullet_right_img right(.addra(bullet_addr), .clka(clk), .douta(RIGHT_data), .ena(1'b1));
|
bullet_right_img right( .addra( bullet_addr ), .clka( clk ), .douta( RIGHT_data ), .ena( 1'b1 ) );
|
||||||
bullet_up_img up(.addra(bullet_addr), .clka(clk), .douta(UP_data), .ena(1'b1));
|
bullet_up_img up( .addra( bullet_addr ), .clka( clk ), .douta( UP_data ), .ena( 1'b1 ) );
|
||||||
bullet_down_img down(.addra(bullet_addr), .clka(clk), .douta(DOWN_data), .ena(1'b1));
|
bullet_down_img down( .addra( bullet_addr ), .clka( clk ), .douta( DOWN_data ), .ena( 1'b1 ) );
|
||||||
|
|
||||||
tank_data_selector bullet_selector(.clk(clk), .UP(UP_data), .DOWN(DOWN_data), .LEFT(LEFT_data),
|
tank_data_selector bullet_selector( .clk( clk ), .UP( UP_data ), .DOWN( DOWN_data ), .LEFT( LEFT_data ),
|
||||||
.RIGHT(RIGHT_data), .Dir(bullet_dir_feedback), .tankData(outData));
|
.RIGHT( RIGHT_data ), .Dir( bullet_direction[ 1: 0 ] ), .tankData( outData ) );
|
||||||
|
|
||||||
assign bulletData = (~ready & bullet_bound) ? outData : 0;
|
assign bulletData = ( ~ready & bullet_bound ) ? outData : 0;
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,104 @@
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Company:
|
||||||
|
// Engineer:
|
||||||
|
//
|
||||||
|
// Create Date: 12/31/2020 03:55:24 PM
|
||||||
|
// Design Name:
|
||||||
|
// Module Name: cal_score
|
||||||
|
// Project Name:
|
||||||
|
// Target Devices:
|
||||||
|
// Tool Versions:
|
||||||
|
// Description:
|
||||||
|
//
|
||||||
|
// Dependencies:
|
||||||
|
//
|
||||||
|
// Revision:
|
||||||
|
// Revision 0.01 - File Created
|
||||||
|
// Additional Comments:
|
||||||
|
//
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
|
module cal_score(
|
||||||
|
input clk,
|
||||||
|
input reset_n,
|
||||||
|
input enermy1_tank_en,
|
||||||
|
input enermy2_tank_en,
|
||||||
|
input enermy3_tank_en,
|
||||||
|
input enermy4_tank_en,
|
||||||
|
input player1_scored,
|
||||||
|
input player2_scored,
|
||||||
|
output reg [ 3: 0 ] scorea1,
|
||||||
|
output reg [ 3: 0 ] scorea2,
|
||||||
|
output reg [ 3: 0 ] scoreb1,
|
||||||
|
output reg [ 3: 0 ] scoreb2,
|
||||||
|
output reg [ 3: 0 ] scorec1,
|
||||||
|
output reg [ 3: 0 ] scorec2,
|
||||||
|
output reg [ 3: 0 ] scored1,
|
||||||
|
output reg [ 3: 0 ] scored2
|
||||||
|
);
|
||||||
|
|
||||||
|
reg enermy1_tank_en_last, enermy2_tank_en_last, enermy3_tank_en_last, enermy4_tank_en_last;
|
||||||
|
initial begin
|
||||||
|
scorea1 <= 0;
|
||||||
|
scorea2 <= 0;
|
||||||
|
scoreb1 <= 0;
|
||||||
|
scoreb2 <= 0;
|
||||||
|
scorec1 <= 0;
|
||||||
|
scorec2 <= 0;
|
||||||
|
scored1 <= 0;
|
||||||
|
scored2 <= 0;
|
||||||
|
end
|
||||||
|
always @( posedge clk ) begin
|
||||||
|
if ( !reset_n ) begin
|
||||||
|
scorea1 <= 0;
|
||||||
|
scorea2 <= 0;
|
||||||
|
scoreb1 <= 0;
|
||||||
|
scoreb2 <= 0;
|
||||||
|
scorec1 <= 0;
|
||||||
|
scorec2 <= 0;
|
||||||
|
scored1 <= 0;
|
||||||
|
scored2 <= 0;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
if ( enermy1_tank_en_last && ~enermy1_tank_en ) begin
|
||||||
|
if ( player1_scored ) begin
|
||||||
|
scorea1 <= scorea1 + 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
scorea2 <= scorea2 + 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else if ( enermy2_tank_en_last && ~enermy2_tank_en ) begin
|
||||||
|
if ( player1_scored ) begin
|
||||||
|
scoreb1 <= scoreb1 + 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
scoreb2 <= scoreb2 + 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else if ( enermy3_tank_en_last && ~enermy3_tank_en ) begin
|
||||||
|
if ( player1_scored ) begin
|
||||||
|
scorec1 <= scorec1 + 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
scorec2 <= scorec2 + 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else if ( enermy4_tank_en_last && ~enermy4_tank_en ) begin
|
||||||
|
if ( player1_scored ) begin
|
||||||
|
scored1 <= scored1 + 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
scored2 <= scored2 + 1'b1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
enermy1_tank_en_last <= enermy1_tank_en;
|
||||||
|
enermy2_tank_en_last <= enermy2_tank_en;
|
||||||
|
enermy3_tank_en_last <= enermy3_tank_en;
|
||||||
|
enermy4_tank_en_last <= enermy4_tank_en;
|
||||||
|
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
|
|
@ -2,85 +2,101 @@
|
||||||
|
|
||||||
module collide_detection(
|
module collide_detection(
|
||||||
input mode,
|
input mode,
|
||||||
input [10:0] player1_tank_H,
|
input [ 10: 0 ] player1_tank_H,
|
||||||
input [10:0] player1_tank_V,
|
input [ 10: 0 ] player1_tank_V,
|
||||||
input [1:0] player1_tank_dir,
|
input [ 1: 0 ] player1_tank_dir,
|
||||||
input player1_tank_en,
|
input player1_tank_en,
|
||||||
input [10:0] player1_bullet_H,
|
input [ 10: 0 ] player1_bullet_H,
|
||||||
input [10:0] player1_bullet_V,
|
input [ 10: 0 ] player1_bullet_V,
|
||||||
input player1_bullet_en,
|
input player1_bullet_en,
|
||||||
input [1:0] player1_bullet_dir,
|
input [ 1: 0 ] player1_bullet_dir,
|
||||||
output reg [7:0] player1_collide, // [bullet4, bullet3, bullet2, bullet1, tank4, tank3, tank2, tank1]
|
output reg [ 7: 0 ] player1_collide, // [bullet4, bullet3, bullet2, bullet1, tank4, tank3, tank2, tank1]
|
||||||
|
|
||||||
input [10:0] player2_tank_H,
|
input [ 10: 0 ] player2_tank_H,
|
||||||
input [10:0] player2_tank_V,
|
input [ 10: 0 ] player2_tank_V,
|
||||||
input [1:0] player2_tank_dir,
|
input [ 1: 0 ] player2_tank_dir,
|
||||||
input player2_tank_en,
|
input player2_tank_en,
|
||||||
input [10:0] player2_bullet_H,
|
input [ 10: 0 ] player2_bullet_H,
|
||||||
input [10:0] player2_bullet_V,
|
input [ 10: 0 ] player2_bullet_V,
|
||||||
input player2_bullet_en,
|
input player2_bullet_en,
|
||||||
input [10:0] player2_bullet_dir,
|
input [ 10: 0 ] player2_bullet_dir,
|
||||||
output reg [7:0] player2_collide // Reserved for other bullets and tanks
|
output reg [ 7: 0 ] player2_collide // Reserved for other bullets and tanks
|
||||||
);
|
);
|
||||||
|
|
||||||
parameter TANK_WIDTH = 32;
|
parameter TANK_WIDTH = 32;
|
||||||
parameter TANK_HEIGHT = 32;
|
parameter TANK_HEIGHT = 32;
|
||||||
parameter BULLET_LONGER = 10;
|
parameter BULLET_LONGER = 10;
|
||||||
parameter BULLET_SHORTER = 5;
|
parameter BULLET_SHORTER = 5;
|
||||||
|
|
||||||
wire [10:0] player1_bullet_RBound, player1_bullet_DBound;
|
wire [ 10: 0 ] player1_bullet_RBound, player1_bullet_DBound;
|
||||||
wire [10:0] player2_bullet_RBound, player2_bullet_DBound;
|
wire [ 10: 0 ] player2_bullet_RBound, player2_bullet_DBound;
|
||||||
wire [10:0] player1_tank_RBound, player1_tank_DBound;
|
wire [ 10: 0 ] player1_tank_RBound, player1_tank_DBound;
|
||||||
wire [10:0] player2_tank_RBound, player2_tank_DBound;
|
wire [ 10: 0 ] player2_tank_RBound, player2_tank_DBound;
|
||||||
reg [3:0] player1_tank_collide_dir, player2_tank_collide_dir;
|
reg [ 3: 0 ] player1_tank_collide_dir, player2_tank_collide_dir;
|
||||||
|
|
||||||
assign player1_bullet_RBound = player1_bullet_H + (player1_bullet_dir == 2'b11 || 2'b10) ? BULLET_LONGER : BULLET_SHORTER;
|
assign player1_bullet_RBound = player1_bullet_H + ( player1_bullet_dir == 2'b11 || 2'b10 ) ? BULLET_LONGER : BULLET_SHORTER;
|
||||||
assign player1_bullet_DBound = player1_bullet_V + (player1_bullet_dir == 2'b00 || 2'b01) ? BULLET_LONGER : BULLET_SHORTER;
|
assign player1_bullet_DBound = player1_bullet_V + ( player1_bullet_dir == 2'b00 || 2'b01 ) ? BULLET_LONGER : BULLET_SHORTER;
|
||||||
|
|
||||||
assign player2_bullet_RBound = player2_bullet_H + (player2_bullet_dir == 2'b11 || 2'b10) ? BULLET_LONGER : BULLET_SHORTER;
|
assign player2_bullet_RBound = player2_bullet_H + ( player2_bullet_dir == 2'b11 || 2'b10 ) ? BULLET_LONGER : BULLET_SHORTER;
|
||||||
assign player2_bullet_DBound = player2_bullet_V + (player2_bullet_dir == 2'b00 || 2'b01) ? BULLET_LONGER : BULLET_SHORTER;
|
assign player2_bullet_DBound = player2_bullet_V + ( player2_bullet_dir == 2'b00 || 2'b01 ) ? BULLET_LONGER : BULLET_SHORTER;
|
||||||
|
|
||||||
assign player1_tank_RBound = player1_tank_H + TANK_WIDTH - 1;
|
assign player1_tank_RBound = player1_tank_H + TANK_WIDTH - 1;
|
||||||
assign player1_tank_DBound = player1_tank_V + TANK_HEIGHT - 1;
|
assign player1_tank_DBound = player1_tank_V + TANK_HEIGHT - 1;
|
||||||
|
|
||||||
assign player2_tank_RBound = player2_tank_H + TANK_WIDTH - 1;
|
assign player2_tank_RBound = player2_tank_H + TANK_WIDTH - 1;
|
||||||
assign player2_tank_DBound = player2_tank_V + TANK_HEIGHT - 1;
|
assign player2_tank_DBound = player2_tank_V + TANK_HEIGHT - 1;
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
player1_collide <= 0;
|
player1_collide <= 0;
|
||||||
player2_collide <= 0;
|
player2_collide <= 0;
|
||||||
|
end
|
||||||
|
|
||||||
|
always @( * ) begin
|
||||||
|
if ( player1_tank_en ) begin
|
||||||
|
if ( player2_bullet_en ) begin
|
||||||
|
if ( player1_tank_H >= player2_bullet_H && player1_tank_H <= player2_bullet_RBound &&
|
||||||
|
player1_tank_V >= player2_bullet_V && player1_tank_V <= player2_bullet_RBound ) begin
|
||||||
|
player1_collide[ 5 ] <= 1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
player1_collide[ 5 ] <= 0;
|
||||||
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
always @(*) begin
|
if ( player2_tank_en && player1_tank_RBound <= player2_tank_RBound && player1_tank_RBound >= player2_tank_H &&
|
||||||
if(player1_tank_en) begin
|
~( player1_tank_DBound < player2_tank_V || player1_tank_V > player2_tank_DBound ) ) begin
|
||||||
if (player2_bullet_en) begin
|
player1_tank_collide_dir[ 3 ] <= 1;
|
||||||
if(player1_tank_H >= player2_bullet_H && player1_tank_H <= player2_bullet_RBound &&
|
end
|
||||||
player1_tank_V >= player2_bullet_V && player1_tank_V <= player2_bullet_RBound) player1_collide[5] <= 1;
|
else begin
|
||||||
else player1_collide[5] <= 0;
|
player1_tank_collide_dir[ 3 ] <= 0;
|
||||||
end
|
end
|
||||||
|
|
||||||
if(player2_tank_en && player1_tank_RBound <= player2_tank_RBound && player1_tank_RBound >= player2_tank_H &&
|
if ( player2_tank_en && player1_tank_H <= player2_tank_RBound && player1_tank_H >= player2_tank_H &&
|
||||||
~( player1_tank_DBound < player2_tank_V || player1_tank_V > player2_tank_DBound))
|
~( player1_tank_DBound < player2_tank_V || player1_tank_V > player2_tank_DBound ) ) begin
|
||||||
player1_tank_collide_dir[3] <= 1;
|
player1_tank_collide_dir[ 2 ] <= 1;
|
||||||
else player1_tank_collide_dir[3] <= 0;
|
|
||||||
|
|
||||||
if(player2_tank_en && player1_tank_H <= player2_tank_RBound && player1_tank_H >= player2_tank_H &&
|
|
||||||
~( player1_tank_DBound < player2_tank_V || player1_tank_V > player2_tank_DBound) )
|
|
||||||
player1_tank_collide_dir[2] <= 1;
|
|
||||||
else player1_tank_collide_dir[2] <= 0;
|
|
||||||
|
|
||||||
if(player2_tank_en && player1_tank_V <= player2_tank_DBound && player1_tank_V >= player2_tank_V
|
|
||||||
&& ~(player1_tank_RBound < player2_tank_H || player1_tank_H > player2_tank_RBound) )
|
|
||||||
player1_tank_collide_dir[0] <= 1;
|
|
||||||
else player1_tank_collide_dir[0] <= 0;
|
|
||||||
|
|
||||||
if(player2_tank_en && player1_tank_DBound <= player2_tank_DBound && player1_tank_DBound >= player2_tank_V
|
|
||||||
&& ~(player1_tank_RBound < player2_tank_H || player1_tank_H > player2_tank_RBound) )
|
|
||||||
player1_tank_collide_dir[1] <= 1;
|
|
||||||
else player1_tank_collide_dir[1] <= 0;
|
|
||||||
player1_collide[1] <= player1_tank_collide_dir[player1_tank_dir];
|
|
||||||
end
|
end
|
||||||
/*
|
else begin
|
||||||
|
player1_tank_collide_dir[ 2 ] <= 0;
|
||||||
|
end
|
||||||
|
|
||||||
|
if ( player2_tank_en && player1_tank_V <= player2_tank_DBound && player1_tank_V >= player2_tank_V
|
||||||
|
&& ~( player1_tank_RBound < player2_tank_H || player1_tank_H > player2_tank_RBound ) ) begin
|
||||||
|
player1_tank_collide_dir[ 0 ] <= 1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
player1_tank_collide_dir[ 0 ] <= 0;
|
||||||
|
end
|
||||||
|
|
||||||
|
if ( player2_tank_en && player1_tank_DBound <= player2_tank_DBound && player1_tank_DBound >= player2_tank_V
|
||||||
|
&& ~( player1_tank_RBound < player2_tank_H || player1_tank_H > player2_tank_RBound ) ) begin
|
||||||
|
player1_tank_collide_dir[ 1 ] <= 1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
player1_tank_collide_dir[ 1 ] <= 0;
|
||||||
|
end
|
||||||
|
player1_collide[ 1 ] <= player1_tank_collide_dir[ player1_tank_dir ];
|
||||||
|
end
|
||||||
|
/*
|
||||||
object_collide_detection player1_2(
|
object_collide_detection player1_2(
|
||||||
.object1_H(player1_tank_H),
|
.object1_H(player1_tank_H),
|
||||||
.object1_V(player1_tank_V),
|
.object1_V(player1_tank_V),
|
||||||
|
|
@ -96,39 +112,55 @@ module collide_detection(
|
||||||
.object2_DBound(player2_tank_DBound),
|
.object2_DBound(player2_tank_DBound),
|
||||||
.object1_collide(),
|
.object1_collide(),
|
||||||
.object2_collide());
|
.object2_collide());
|
||||||
*/
|
*/
|
||||||
|
end
|
||||||
|
|
||||||
|
always @( * ) begin
|
||||||
|
if ( player2_tank_en ) begin
|
||||||
|
if ( player1_bullet_en ) begin
|
||||||
|
if ( player2_tank_H >= player1_bullet_H && player2_tank_H <= player1_bullet_RBound &&
|
||||||
|
player2_tank_V >= player1_bullet_V && player2_tank_V <= player1_bullet_RBound ) begin
|
||||||
|
player2_collide[ 4 ] <= 1;
|
||||||
end
|
end
|
||||||
|
else begin
|
||||||
always @(*) begin
|
player2_collide[ 4 ] <= 0;
|
||||||
if(player2_tank_en) begin
|
|
||||||
if (player1_bullet_en) begin
|
|
||||||
if(player2_tank_H >= player1_bullet_H && player2_tank_H <= player1_bullet_RBound &&
|
|
||||||
player2_tank_V >= player1_bullet_V && player2_tank_V <= player1_bullet_RBound) player2_collide[4] <= 1;
|
|
||||||
else player2_collide[4] <= 0;
|
|
||||||
end
|
|
||||||
|
|
||||||
if(player1_tank_en && player2_tank_RBound <= player1_tank_RBound && player2_tank_RBound >= player1_tank_H &&
|
|
||||||
~( player2_tank_DBound < player1_tank_V || player2_tank_V > player1_tank_DBound))
|
|
||||||
player2_tank_collide_dir[3] <= 1;
|
|
||||||
else player2_tank_collide_dir[3] <= 0;
|
|
||||||
|
|
||||||
if(player1_tank_en && player2_tank_H <= player1_tank_RBound && player2_tank_H >= player1_tank_H &&
|
|
||||||
~( player2_tank_DBound < player1_tank_V || player2_tank_V > player1_tank_DBound) )
|
|
||||||
player2_tank_collide_dir[2] <= 1;
|
|
||||||
else player2_tank_collide_dir[2] <= 0;
|
|
||||||
|
|
||||||
if(player1_tank_en && player2_tank_V <= player1_tank_DBound && player2_tank_V >= player1_tank_V
|
|
||||||
&& ~(player2_tank_RBound < player1_tank_H || player2_tank_H > player1_tank_RBound) )
|
|
||||||
player2_tank_collide_dir[0] <= 1;
|
|
||||||
else player2_tank_collide_dir[0] <= 0;
|
|
||||||
|
|
||||||
if(player1_tank_en && player2_tank_DBound <= player1_tank_DBound && player2_tank_DBound >= player1_tank_V
|
|
||||||
&& ~(player2_tank_RBound < player1_tank_H || player2_tank_H > player1_tank_RBound) )
|
|
||||||
player2_tank_collide_dir[1] <= 1;
|
|
||||||
else player2_tank_collide_dir[1] <= 0;
|
|
||||||
player2_collide[1] <= player2_tank_collide_dir[player2_tank_dir];
|
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
if ( player1_tank_en && player2_tank_RBound <= player1_tank_RBound && player2_tank_RBound >= player1_tank_H &&
|
||||||
|
~( player2_tank_DBound < player1_tank_V || player2_tank_V > player1_tank_DBound ) ) begin
|
||||||
|
player2_tank_collide_dir[ 3 ] <= 1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
player2_tank_collide_dir[ 3 ] <= 0;
|
||||||
|
end
|
||||||
|
|
||||||
|
if ( player1_tank_en && player2_tank_H <= player1_tank_RBound && player2_tank_H >= player1_tank_H &&
|
||||||
|
~( player2_tank_DBound < player1_tank_V || player2_tank_V > player1_tank_DBound ) ) begin
|
||||||
|
player2_tank_collide_dir[ 2 ] <= 1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
player2_tank_collide_dir[ 2 ] <= 0;
|
||||||
|
end
|
||||||
|
|
||||||
|
if ( player1_tank_en && player2_tank_V <= player1_tank_DBound && player2_tank_V >= player1_tank_V
|
||||||
|
&& ~( player2_tank_RBound < player1_tank_H || player2_tank_H > player1_tank_RBound ) ) begin
|
||||||
|
player2_tank_collide_dir[ 0 ] <= 1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
player2_tank_collide_dir[ 0 ] <= 0;
|
||||||
|
end
|
||||||
|
|
||||||
|
if ( player1_tank_en && player2_tank_DBound <= player1_tank_DBound && player2_tank_DBound >= player1_tank_V
|
||||||
|
&& ~( player2_tank_RBound < player1_tank_H || player2_tank_H > player1_tank_RBound ) ) begin
|
||||||
|
player2_tank_collide_dir[ 1 ] <= 1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
player2_tank_collide_dir[ 1 ] <= 0;
|
||||||
|
end
|
||||||
|
player2_collide[ 1 ] <= player2_tank_collide_dir[ player2_tank_dir ];
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -3,28 +3,63 @@
|
||||||
module control_signals(
|
module control_signals(
|
||||||
clk, reset_n,
|
clk, reset_n,
|
||||||
player1_bullet_H, player1_bullet_V, player2_bullet_H, player2_bullet_V,
|
player1_bullet_H, player1_bullet_V, player2_bullet_H, player2_bullet_V,
|
||||||
|
enermy1_bullet_H, enermy1_bullet_V,
|
||||||
|
enermy2_bullet_H, enermy2_bullet_V,
|
||||||
|
enermy3_bullet_H, enermy3_bullet_V,
|
||||||
|
enermy4_bullet_H, enermy4_bullet_V,
|
||||||
player1_bullet_dir, player2_bullet_dir,
|
player1_bullet_dir, player2_bullet_dir,
|
||||||
|
enermy1_bullet_dir, enermy2_bullet_dir, enermy3_bullet_dir, enermy4_bullet_dir,
|
||||||
player1_tank_H, player1_tank_V, player2_tank_H, player2_tank_V,
|
player1_tank_H, player1_tank_V, player2_tank_H, player2_tank_V,
|
||||||
// player1_tank_en, player2_tank_en,
|
enermy1_tank_H, enermy1_tank_V,
|
||||||
|
enermy2_tank_H, enermy2_tank_V,
|
||||||
|
enermy3_tank_H, enermy3_tank_V,
|
||||||
|
enermy4_tank_H, enermy4_tank_V,
|
||||||
|
// player1_tank_en, player2_tank_en,
|
||||||
player1_moving, player2_moving,
|
player1_moving, player2_moving,
|
||||||
|
enermy1_moving, enermy2_moving, enermy3_moving, enermy4_moving,
|
||||||
player1_tank_dir, player2_tank_dir,
|
player1_tank_dir, player2_tank_dir,
|
||||||
|
enermy1_tank_dir, enermy2_tank_dir, enermy3_tank_dir, enermy4_tank_dir,
|
||||||
player1_revive, player2_revive,
|
player1_revive, player2_revive,
|
||||||
|
enermy1_revive, enermy2_revive, enermy3_revive, enermy4_revive,
|
||||||
player1_tank_en_feedback, player2_tank_en_feedback,
|
player1_tank_en_feedback, player2_tank_en_feedback,
|
||||||
|
enermy1_tank_en_feedback, enermy2_tank_en_feedback, enermy3_tank_en_feedback, enermy4_tank_en_feedback,
|
||||||
player1_tank_move_en, player2_tank_move_en,
|
player1_tank_move_en, player2_tank_move_en,
|
||||||
player1_bullet_en, player2_bullet_en
|
enermy1_tank_move_en, enermy2_tank_move_en, enermy3_tank_move_en, enermy4_tank_move_en,
|
||||||
);
|
player1_bullet_en, player2_bullet_en,
|
||||||
|
enermy1_bullet_en, enermy2_bullet_en, enermy3_bullet_en, enermy4_bullet_en, player1_scored, player2_scored
|
||||||
|
// scorea1, scorea2, scoreb1, scoreb2, scorec1, scorec2, scored1, scored2
|
||||||
|
);
|
||||||
input clk, reset_n;
|
input clk, reset_n;
|
||||||
input [10:0] player1_bullet_H, player1_bullet_V, player2_bullet_H, player2_bullet_V;
|
input [ 10: 0 ] player1_bullet_H, player1_bullet_V, player2_bullet_H, player2_bullet_V;
|
||||||
input [10:0] player1_tank_H, player1_tank_V, player2_tank_H, player2_tank_V;
|
input [ 10: 0 ] enermy1_bullet_H, enermy1_bullet_V,
|
||||||
// input player1_tank_en, player2_tank_en;
|
enermy2_bullet_H, enermy2_bullet_V,
|
||||||
input [2:0] player1_bullet_dir, player2_bullet_dir;
|
enermy3_bullet_H, enermy3_bullet_V,
|
||||||
input player1_revive, player2_revive;
|
enermy4_bullet_H, enermy4_bullet_V;
|
||||||
input [1:0] player1_tank_dir, player2_tank_dir;
|
|
||||||
input player1_moving, player2_moving;
|
|
||||||
output reg player1_tank_en_feedback, player2_tank_en_feedback;
|
|
||||||
output reg player1_tank_move_en, player2_tank_move_en;
|
|
||||||
output reg player1_bullet_en, player2_bullet_en;
|
|
||||||
|
|
||||||
|
input [ 10: 0 ] player1_tank_H, player1_tank_V, player2_tank_H, player2_tank_V;
|
||||||
|
input [ 10: 0 ] enermy1_tank_H, enermy1_tank_V,
|
||||||
|
enermy2_tank_H, enermy2_tank_V,
|
||||||
|
enermy3_tank_H, enermy3_tank_V,
|
||||||
|
enermy4_tank_H, enermy4_tank_V;
|
||||||
|
// input player1_tank_en, player2_tank_en;
|
||||||
|
input [ 2: 0 ] player1_bullet_dir, player2_bullet_dir;
|
||||||
|
input [ 2: 0 ] enermy1_bullet_dir, enermy2_bullet_dir, enermy3_bullet_dir, enermy4_bullet_dir;
|
||||||
|
|
||||||
|
input player1_revive, player2_revive;
|
||||||
|
input enermy1_revive, enermy2_revive, enermy3_revive, enermy4_revive;
|
||||||
|
|
||||||
|
input [ 1: 0 ] player1_tank_dir, player2_tank_dir;
|
||||||
|
input [ 1: 0 ] enermy1_tank_dir, enermy2_tank_dir, enermy3_tank_dir, enermy4_tank_dir;
|
||||||
|
input player1_moving, player2_moving;
|
||||||
|
input enermy1_moving, enermy2_moving, enermy3_moving, enermy4_moving;
|
||||||
|
output reg player1_tank_en_feedback, player2_tank_en_feedback;
|
||||||
|
output reg enermy1_tank_en_feedback, enermy2_tank_en_feedback, enermy3_tank_en_feedback, enermy4_tank_en_feedback;
|
||||||
|
output reg player1_tank_move_en, player2_tank_move_en;
|
||||||
|
output reg enermy1_tank_move_en, enermy2_tank_move_en, enermy3_tank_move_en, enermy4_tank_move_en;
|
||||||
|
output reg player1_bullet_en, player2_bullet_en;
|
||||||
|
output reg enermy1_bullet_en, enermy2_bullet_en, enermy3_bullet_en, enermy4_bullet_en;
|
||||||
|
output reg player1_scored, player2_scored;
|
||||||
|
// output reg [ 3: 0 ] scorea1, scorea2, scoreb1, scoreb2, scorec1, scorec2, scored1, scored2;
|
||||||
parameter HEIGHT = 480;
|
parameter HEIGHT = 480;
|
||||||
parameter WIDTH = 640;
|
parameter WIDTH = 640;
|
||||||
parameter BULLET_LONGER = 10;
|
parameter BULLET_LONGER = 10;
|
||||||
|
|
@ -32,59 +67,450 @@ parameter BULLET_SHORTER = 5;
|
||||||
parameter TANK_WIDTH = 32;
|
parameter TANK_WIDTH = 32;
|
||||||
parameter TANK_HEIGHT = 32;
|
parameter TANK_HEIGHT = 32;
|
||||||
|
|
||||||
wire [7:0] player1_bullet_collide, player2_bullet_collide;
|
initial begin
|
||||||
wire [7:0] player1_tank_collide, player2_tank_collide;
|
player1_tank_en_feedback <= 1'b1;
|
||||||
reg player1_tank_destroyed, player2_tank_destroyed;
|
player2_tank_en_feedback <= 1'b1;
|
||||||
|
enermy1_tank_en_feedback <= 1'b1;
|
||||||
|
enermy2_tank_en_feedback <= 1'b1;
|
||||||
|
enermy3_tank_en_feedback <= 1'b1;
|
||||||
|
enermy4_tank_en_feedback <= 1'b1;
|
||||||
|
|
||||||
object_collide_detection bullet1_tank2(
|
player1_tank_move_en <= 1'b1;
|
||||||
player1_bullet_H, player1_bullet_V, ~player1_bullet_dir[2], player1_bullet_dir[1:0],
|
player2_tank_move_en <= 1'b1;
|
||||||
BULLET_LONGER, BULLET_SHORTER,
|
enermy1_tank_move_en <= 1'b1;
|
||||||
player2_tank_H, player2_tank_V, player2_tank_en_feedback, player2_tank_dir[1:0],
|
enermy2_tank_move_en <= 1'b1;
|
||||||
TANK_HEIGHT, TANK_WIDTH,
|
enermy3_tank_move_en <= 1'b1;
|
||||||
player1_bullet_collide[1], player2_tank_collide[4]
|
enermy4_tank_move_en <= 1'b1;
|
||||||
);
|
|
||||||
|
|
||||||
object_collide_detection tank1_tank2(
|
player1_bullet_en <= 1'b1;
|
||||||
player1_tank_H, player1_tank_V, player1_tank_en_feedback, player1_tank_dir,
|
player2_bullet_en <= 1'b1;
|
||||||
TANK_HEIGHT, TANK_WIDTH,
|
enermy1_bullet_en <= 1'b1;
|
||||||
player2_tank_H, player2_tank_V, player2_tank_en_feedback, player2_tank_dir,
|
enermy2_bullet_en <= 1'b1;
|
||||||
TANK_HEIGHT, TANK_WIDTH,
|
enermy3_bullet_en <= 1'b1;
|
||||||
player1_tank_collide[1], player2_tank_collide[0]
|
enermy4_bullet_en <= 1'b1;
|
||||||
);
|
// scorea1 <= 0;
|
||||||
|
// scorea2 <= 0;
|
||||||
|
// scoreb1 <= 0;
|
||||||
always @(*) begin: player1_bullet_enable_signal
|
// scoreb2 <= 0;
|
||||||
if(player1_bullet_dir[2]) player1_bullet_en <= 1;
|
// scorec1 <= 0;
|
||||||
else if(player1_bullet_collide[1]) player1_bullet_en <= 1;
|
// scorec2 <= 0;
|
||||||
else player1_bullet_en <= ~( (~player1_bullet_dir[2]) && (player1_bullet_V >= 0 && player1_bullet_V < HEIGHT - BULLET_LONGER &&
|
// scored1 <= 0;
|
||||||
player1_bullet_H >= 0 && player1_bullet_H < WIDTH - BULLET_SHORTER) );
|
// scored2 <= 0;
|
||||||
end
|
end
|
||||||
|
|
||||||
|
wire [ 7: 0 ] player1_bullet_collide, player2_bullet_collide;
|
||||||
|
wire [ 7: 0 ] player1_bullet_collide_last, player2_bullet_collide_last;
|
||||||
|
wire [ 7: 0 ] enermy_bullet_collide;
|
||||||
|
wire [ 7: 0 ] player1_tank_collide, player2_tank_collide;
|
||||||
|
wire [ 7: 0 ] enermy_tank_collide;
|
||||||
|
|
||||||
always @(*) begin: player2_tank_enable_signal
|
// reg player1_tank_destroyed, player2_tank_destroyed;
|
||||||
|
// object_collide_detection enermy1_mytank1(
|
||||||
|
// enermy1_bullet_H, enermy1_bullet_V, ~enermy1_bullet_dir[ 2 ], enermy1_bullet_dir[ 1: 0 ],
|
||||||
|
// BULLET_LONGER, BULLET_SHORTER,
|
||||||
|
// enermy1_tank_H, enermy1_tank_V, enermy1_tank_en_feedback, enermy1_tank_dir[ 1: 0 ],
|
||||||
|
// TANK_HEIGHT, TANK_WIDTH,
|
||||||
|
// player1_bullet_collide[ 0 ], enermy_tank_collide[ 0 ]
|
||||||
|
// );
|
||||||
|
object_collide_detection mytank1_enermy1(
|
||||||
|
player1_bullet_H, player1_bullet_V, ~player1_bullet_dir[ 2 ], player1_bullet_dir[ 1: 0 ],
|
||||||
|
BULLET_LONGER, BULLET_SHORTER,
|
||||||
|
enermy1_tank_H, enermy1_tank_V, enermy1_tank_en_feedback, enermy1_tank_dir[ 1: 0 ],
|
||||||
|
TANK_HEIGHT, TANK_WIDTH,
|
||||||
|
player1_bullet_collide[ 0 ], enermy_tank_collide[ 0 ]
|
||||||
|
);
|
||||||
|
object_collide_detection mytank1_enermy2(
|
||||||
|
player1_bullet_H, player1_bullet_V, ~player1_bullet_dir[ 2 ], player1_bullet_dir[ 1: 0 ],
|
||||||
|
BULLET_LONGER, BULLET_SHORTER,
|
||||||
|
enermy2_tank_H, enermy2_tank_V, enermy2_tank_en_feedback, enermy2_tank_dir[ 1: 0 ],
|
||||||
|
TANK_HEIGHT, TANK_WIDTH,
|
||||||
|
player1_bullet_collide[ 1 ], enermy_tank_collide[ 1 ]
|
||||||
|
);
|
||||||
|
object_collide_detection mytank1_enermy3(
|
||||||
|
player1_bullet_H, player1_bullet_V, ~player1_bullet_dir[ 2 ], player1_bullet_dir[ 1: 0 ],
|
||||||
|
BULLET_LONGER, BULLET_SHORTER,
|
||||||
|
enermy3_tank_H, enermy3_tank_V, enermy3_tank_en_feedback, enermy3_tank_dir[ 1: 0 ],
|
||||||
|
TANK_HEIGHT, TANK_WIDTH,
|
||||||
|
player1_bullet_collide[ 2 ], enermy_tank_collide[ 2 ]
|
||||||
|
);
|
||||||
|
object_collide_detection mytank1_enermy4(
|
||||||
|
player1_bullet_H, player1_bullet_V, ~player1_bullet_dir[ 2 ], player1_bullet_dir[ 1: 0 ],
|
||||||
|
BULLET_LONGER, BULLET_SHORTER,
|
||||||
|
enermy4_tank_H, enermy4_tank_V, enermy4_tank_en_feedback, enermy4_tank_dir[ 1: 0 ],
|
||||||
|
TANK_HEIGHT, TANK_WIDTH,
|
||||||
|
player1_bullet_collide[ 3 ], enermy_tank_collide[ 3 ]
|
||||||
|
);
|
||||||
|
object_collide_detection mytank2_enermy1(
|
||||||
|
player2_bullet_H, player2_bullet_V, ~player2_bullet_dir[ 2 ], player2_bullet_dir[ 1: 0 ],
|
||||||
|
BULLET_LONGER, BULLET_SHORTER,
|
||||||
|
enermy1_tank_H, enermy1_tank_V, enermy1_tank_en_feedback, enermy1_tank_dir[ 1: 0 ],
|
||||||
|
TANK_HEIGHT, TANK_WIDTH,
|
||||||
|
player2_bullet_collide[ 0 ], enermy_tank_collide[ 4 ]
|
||||||
|
);
|
||||||
|
object_collide_detection mytank2_enermy2(
|
||||||
|
player2_bullet_H, player2_bullet_V, ~player2_bullet_dir[ 2 ], player2_bullet_dir[ 1: 0 ],
|
||||||
|
BULLET_LONGER, BULLET_SHORTER,
|
||||||
|
enermy2_tank_H, enermy2_tank_V, enermy2_tank_en_feedback, enermy2_tank_dir[ 1: 0 ],
|
||||||
|
TANK_HEIGHT, TANK_WIDTH,
|
||||||
|
player2_bullet_collide[ 1 ], enermy_tank_collide[ 5 ]
|
||||||
|
);
|
||||||
|
object_collide_detection mytank2_enermy3(
|
||||||
|
player2_bullet_H, player2_bullet_V, ~player2_bullet_dir[ 2 ], player2_bullet_dir[ 1: 0 ],
|
||||||
|
BULLET_LONGER, BULLET_SHORTER,
|
||||||
|
enermy3_tank_H, enermy3_tank_V, enermy3_tank_en_feedback, enermy3_tank_dir[ 1: 0 ],
|
||||||
|
TANK_HEIGHT, TANK_WIDTH,
|
||||||
|
player2_bullet_collide[ 2 ], enermy_tank_collide[ 6 ]
|
||||||
|
);
|
||||||
|
object_collide_detection mytank2_enermy4(
|
||||||
|
player2_bullet_H, player2_bullet_V, ~player2_bullet_dir[ 2 ], player2_bullet_dir[ 1: 0 ],
|
||||||
|
BULLET_LONGER, BULLET_SHORTER,
|
||||||
|
enermy4_tank_H, enermy4_tank_V, enermy4_tank_en_feedback, enermy4_tank_dir[ 1: 0 ],
|
||||||
|
TANK_HEIGHT, TANK_WIDTH,
|
||||||
|
player2_bullet_collide[ 3 ], enermy_tank_collide[ 7 ]
|
||||||
|
);
|
||||||
|
|
||||||
if(player2_revive) player2_tank_en_feedback <= 1;
|
// object_collide_detection bullet1_tank2(
|
||||||
else if(!reset_n) player2_tank_en_feedback <= 1;
|
// player1_bullet_H, player1_bullet_V, ~player1_bullet_dir[ 2 ], player1_bullet_dir[ 1: 0 ],
|
||||||
else if(!player2_tank_en_feedback) player2_tank_en_feedback <= 0;
|
// BULLET_LONGER, BULLET_SHORTER,
|
||||||
else if(player1_bullet_collide[1]) player2_tank_en_feedback <= 0;
|
// player2_tank_H, player2_tank_V, player2_tank_en_feedback, player2_tank_dir[ 1: 0 ],
|
||||||
else player2_tank_en_feedback <= 1;
|
// TANK_HEIGHT, TANK_WIDTH,
|
||||||
|
// player1_bullet_collide[ 1 ], player2_tank_collide[ 4 ]
|
||||||
|
// );
|
||||||
|
|
||||||
|
// object_collide_detection bullet2_tank1(
|
||||||
|
// player2_bullet_H, player2_bullet_V, ~player2_bullet_dir[ 2 ], player2_bullet_dir[ 1: 0 ],
|
||||||
|
// BULLET_LONGER, BULLET_SHORTER,
|
||||||
|
// player1_tank_H, player1_tank_V, player1_tank_en_feedback, player1_tank_dir[ 1: 0 ],
|
||||||
|
// TANK_HEIGHT, TANK_WIDTH,
|
||||||
|
// player2_bullet_collide[ 1 ], player1_tank_collide[ 4 ]
|
||||||
|
// );
|
||||||
|
|
||||||
|
// object_collide_detection tank1_tank2(
|
||||||
|
// player1_tank_H, player1_tank_V, player1_tank_en_feedback, player1_tank_dir,
|
||||||
|
// TANK_HEIGHT, TANK_WIDTH,
|
||||||
|
// player2_tank_H, player2_tank_V, player2_tank_en_feedback, player2_tank_dir,
|
||||||
|
// TANK_HEIGHT, TANK_WIDTH,
|
||||||
|
// player1_tank_collide[ 1 ], player2_tank_collide[ 0 ]
|
||||||
|
// );
|
||||||
|
|
||||||
|
// always @( posedge player1_bullet_collide[ 0 ] or posedge player1_bullet_collide[ 1 ] or posedge player1_bullet_collide[ 2 ] or posedge player1_bullet_collide[ 3 ] ) begin
|
||||||
|
// if ( reset_n ) begin
|
||||||
|
// scorea1 <= 0;
|
||||||
|
// scoreb1 <= 0;
|
||||||
|
// scorec1 <= 0;
|
||||||
|
// scored1 <= 0;
|
||||||
|
// end
|
||||||
|
// else begin
|
||||||
|
// if ( player1_bullet_collide[ 0 ] ) begin
|
||||||
|
// scorea1 <= scorea1 + 1'b1;
|
||||||
|
// end
|
||||||
|
// else if ( player1_bullet_collide[ 1 ] ) begin
|
||||||
|
// scoreb1 <= scoreb1 + 1'b1;
|
||||||
|
// end
|
||||||
|
// else if ( player1_bullet_collide[ 2 ] ) begin
|
||||||
|
// scorec1 <= scorec1 + 1'b1;
|
||||||
|
// end
|
||||||
|
// else if ( player1_bullet_collide[ 3 ] ) begin
|
||||||
|
// scored1 <= scored1 + 1'b1;
|
||||||
|
// end
|
||||||
|
// end
|
||||||
|
// end
|
||||||
|
|
||||||
|
// always @( posedge player2_bullet_collide[ 0 ] or posedge player2_bullet_collide[ 1 ] or posedge player2_bullet_collide[ 2 ] or posedge player2_bullet_collide[ 3 ] ) begin
|
||||||
|
// if ( reset_n ) begin
|
||||||
|
// scorea2 <= 0;
|
||||||
|
// scoreb2 <= 0;
|
||||||
|
// scorec2 <= 0;
|
||||||
|
// scored2 <= 0;
|
||||||
|
// end
|
||||||
|
// else begin
|
||||||
|
// if ( player2_bullet_collide[ 0 ] ) begin
|
||||||
|
// scorea2 <= scorea2 + 1'b1;
|
||||||
|
// end
|
||||||
|
// else if ( player2_bullet_collide[ 1 ] ) begin
|
||||||
|
// scoreb2 <= scoreb2 + 1'b1;
|
||||||
|
// end
|
||||||
|
// else if ( player2_bullet_collide[ 2 ] ) begin
|
||||||
|
// scorec2 <= scorec2 + 1'b1;
|
||||||
|
// end
|
||||||
|
// else if ( player2_bullet_collide[ 3 ] ) begin
|
||||||
|
// scored2 <= scored2 + 1'b1;
|
||||||
|
// end
|
||||||
|
// end
|
||||||
|
// end
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
always @( * ) begin: player1_bullet_enable_signal
|
||||||
|
if ( player1_bullet_dir[ 2 ] ) begin
|
||||||
|
player1_bullet_en <= 1;
|
||||||
|
end
|
||||||
|
else if ( player1_bullet_collide[ 0 ] ) begin
|
||||||
|
player1_bullet_en <= 1;
|
||||||
|
// scorea1 <= scorea1 + 1'b1;
|
||||||
|
end
|
||||||
|
else if ( player1_bullet_collide[ 1 ] ) begin
|
||||||
|
player1_bullet_en <= 1;
|
||||||
|
// scoreb1 <= scoreb1 + 1'b1;
|
||||||
|
end
|
||||||
|
else if ( player1_bullet_collide[ 2 ] ) begin
|
||||||
|
player1_bullet_en <= 1;
|
||||||
|
// scorec1 <= scorec1 + 1'b1;
|
||||||
|
end
|
||||||
|
else if ( player1_bullet_collide[ 3 ] ) begin
|
||||||
|
player1_bullet_en <= 1;
|
||||||
|
// scored1 <= scored1 + 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
player1_bullet_en <= ~( ( ~player1_bullet_dir[ 2 ] ) && ( player1_bullet_V >= 0 && player1_bullet_V < HEIGHT - BULLET_LONGER &&
|
||||||
|
player1_bullet_H >= 0 && player1_bullet_H < WIDTH - BULLET_SHORTER ) );
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @( * ) begin: player2_bullet_enable_signal
|
||||||
|
if ( player2_bullet_dir[ 2 ] ) begin
|
||||||
|
player2_bullet_en <= 1;
|
||||||
|
end
|
||||||
|
else if ( player2_bullet_collide[ 0 ] ) begin
|
||||||
|
player2_bullet_en <= 1;
|
||||||
|
// scorea2 <= scorea2 + 1'b1;
|
||||||
|
end
|
||||||
|
else if ( player2_bullet_collide[ 1 ] ) begin
|
||||||
|
player2_bullet_en <= 1;
|
||||||
|
// scoreb2 <= scoreb2 + 1'b1;
|
||||||
|
end
|
||||||
|
else if ( player2_bullet_collide[ 2 ] ) begin
|
||||||
|
player2_bullet_en <= 1;
|
||||||
|
// scorec2 <= scorec2 + 1'b1;
|
||||||
|
end
|
||||||
|
else if ( player2_bullet_collide[ 3 ] ) begin
|
||||||
|
player2_bullet_en <= 1;
|
||||||
|
// scored2 <= scored2 + 1'b1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
player2_bullet_en <= ~( ( ~player2_bullet_dir[ 2 ] ) && ( player2_bullet_V >= 0 && player2_bullet_V < HEIGHT - BULLET_LONGER &&
|
||||||
|
player2_bullet_H >= 0 && player2_bullet_H < WIDTH - BULLET_SHORTER ) );
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
always @( posedge clk ) begin: enermy_tank_enable_signal
|
||||||
|
player1_scored <= 0;
|
||||||
|
player2_scored <= 0;
|
||||||
|
if ( !reset_n ) begin
|
||||||
|
enermy1_tank_en_feedback <= 1;
|
||||||
|
enermy2_tank_en_feedback <= 1;
|
||||||
|
enermy3_tank_en_feedback <= 1;
|
||||||
|
enermy4_tank_en_feedback <= 1;
|
||||||
|
end
|
||||||
|
if ( enermy1_revive ) begin
|
||||||
|
enermy1_tank_en_feedback <= 1;
|
||||||
|
end
|
||||||
|
else if ( enermy2_revive ) begin
|
||||||
|
enermy2_tank_en_feedback <= 1;
|
||||||
|
end
|
||||||
|
else if ( enermy3_revive ) begin
|
||||||
|
enermy3_tank_en_feedback <= 1;
|
||||||
|
end
|
||||||
|
else if ( enermy4_revive ) begin
|
||||||
|
enermy4_tank_en_feedback <= 1;
|
||||||
|
end
|
||||||
|
if ( player1_bullet_collide[ 0 ] || player2_bullet_collide[ 0 ] ) begin
|
||||||
|
enermy1_tank_en_feedback <= 0;
|
||||||
|
if ( player1_bullet_collide[ 0 ] ) begin
|
||||||
|
player1_scored <= 1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
player2_scored <= 1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else if ( player1_bullet_collide[ 1 ] || player2_bullet_collide[ 1 ] ) begin
|
||||||
|
enermy2_tank_en_feedback <= 0;
|
||||||
|
if ( player1_bullet_collide[ 1 ] ) begin
|
||||||
|
player1_scored <= 1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
player2_scored <= 1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else if ( player1_bullet_collide[ 2 ] || player2_bullet_collide[ 2 ] ) begin
|
||||||
|
enermy3_tank_en_feedback <= 0;
|
||||||
|
if ( player1_bullet_collide[ 2 ] ) begin
|
||||||
|
player1_scored <= 1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
player2_scored <= 1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
else if ( player1_bullet_collide[ 3 ] || player2_bullet_collide[ 3 ] ) begin
|
||||||
|
enermy4_tank_en_feedback <= 0;
|
||||||
|
if ( player1_bullet_collide[ 3 ] ) begin
|
||||||
|
player1_scored <= 1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
player2_scored <= 1;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
enermy1_tank_move_en <= 1;
|
||||||
|
enermy2_tank_move_en <= 1;
|
||||||
|
enermy3_tank_move_en <= 1;
|
||||||
|
enermy4_tank_move_en <= 1;
|
||||||
|
|
||||||
|
end
|
||||||
|
// always @( posedge clk ) begin: enermy1_tank_enable_signal
|
||||||
|
// player1_scored <= 0;
|
||||||
|
// player2_scored <= 0;
|
||||||
|
// if ( enermy1_revive ) begin
|
||||||
|
// enermy1_tank_en_feedback <= 1;
|
||||||
|
// end
|
||||||
|
// else if ( !reset_n ) begin
|
||||||
|
// enermy1_tank_en_feedback <= 1;
|
||||||
|
// // scorea1 <= 0;
|
||||||
|
// // scorea2 <= 0;
|
||||||
|
// end
|
||||||
|
// else if ( player1_bullet_collide[ 0 ] || player2_bullet_collide[ 0 ] ) begin
|
||||||
|
// enermy1_tank_en_feedback <= 0;
|
||||||
|
// if ( player1_bullet_collide[ 0 ] ) begin
|
||||||
|
// player1_scored <= 1;
|
||||||
|
// end
|
||||||
|
// else begin
|
||||||
|
// player2_scored <= 1;
|
||||||
|
// end
|
||||||
|
// end
|
||||||
|
// enermy1_tank_move_en <= 1;
|
||||||
|
// // if ( player2_tank_collide[ 0 ] && player2_moving ) begin
|
||||||
|
// // player2_tank_move_en <= 0;
|
||||||
|
// // end
|
||||||
|
// end
|
||||||
|
|
||||||
|
|
||||||
|
// always @( posedge clk ) begin: enermy2_tank_enable_signal
|
||||||
|
// player1_scored <= 0;
|
||||||
|
// player2_scored <= 0;
|
||||||
|
// if ( enermy2_revive ) begin
|
||||||
|
// enermy2_tank_en_feedback <= 1;
|
||||||
|
// end
|
||||||
|
// else if ( !reset_n ) begin
|
||||||
|
// enermy2_tank_en_feedback <= 1;
|
||||||
|
// // scoreb1 <= 0;
|
||||||
|
// // scoreb2 <= 0;
|
||||||
|
// end
|
||||||
|
// else if ( player1_bullet_collide[ 1 ] || player2_bullet_collide[ 1 ] ) begin
|
||||||
|
// enermy2_tank_en_feedback <= 0;
|
||||||
|
// if ( player1_bullet_collide[ 1 ] ) begin
|
||||||
|
// player1_scored <= 1;
|
||||||
|
// end
|
||||||
|
// else begin
|
||||||
|
// player2_scored <= 1;
|
||||||
|
// end
|
||||||
|
// end
|
||||||
|
// enermy2_tank_move_en <= 1;
|
||||||
|
// // if ( player2_tank_collide[ 0 ] && player2_moving ) begin
|
||||||
|
// // player2_tank_move_en <= 0;
|
||||||
|
// // end
|
||||||
|
// end
|
||||||
|
|
||||||
|
|
||||||
|
// always @( posedge clk ) begin: enermy3_tank_enable_signal
|
||||||
|
// player1_scored <= 0;
|
||||||
|
// player2_scored <= 0;
|
||||||
|
// if ( enermy3_revive ) begin
|
||||||
|
// enermy3_tank_en_feedback <= 1;
|
||||||
|
// end
|
||||||
|
// else if ( !reset_n ) begin
|
||||||
|
// enermy3_tank_en_feedback <= 1;
|
||||||
|
// // scorec1 <= 0;
|
||||||
|
// // scorec2 <= 0;
|
||||||
|
// end
|
||||||
|
// else if ( player1_bullet_collide[ 2 ] || player2_bullet_collide[ 2 ] ) begin
|
||||||
|
// enermy3_tank_en_feedback <= 0;
|
||||||
|
// if ( player1_bullet_collide[ 2 ] ) begin
|
||||||
|
// player1_scored <= 1;
|
||||||
|
// end
|
||||||
|
// else begin
|
||||||
|
// player2_scored <= 1;
|
||||||
|
// end
|
||||||
|
// end
|
||||||
|
// enermy3_tank_move_en <= 1;
|
||||||
|
// // if ( player2_tank_collide[ 0 ] && player2_moving ) begin
|
||||||
|
// // player2_tank_move_en <= 0;
|
||||||
|
// // end
|
||||||
|
// end
|
||||||
|
|
||||||
|
|
||||||
|
// always @( posedge clk ) begin: enermy4_tank_enable_signal
|
||||||
|
// player1_scored <= 0;
|
||||||
|
// player2_scored <= 0;
|
||||||
|
// if ( enermy4_revive ) begin
|
||||||
|
// enermy4_tank_en_feedback <= 1;
|
||||||
|
// end
|
||||||
|
// else if ( !reset_n ) begin
|
||||||
|
// enermy4_tank_en_feedback <= 1;
|
||||||
|
// // scored1 <= 0;
|
||||||
|
// // scored2 <= 0;
|
||||||
|
// end
|
||||||
|
// else if ( player1_bullet_collide[ 3 ] || player2_bullet_collide[ 3 ] ) begin
|
||||||
|
// enermy4_tank_en_feedback <= 0;
|
||||||
|
// if ( player1_bullet_collide[ 3 ] ) begin
|
||||||
|
// player1_scored <= 1;
|
||||||
|
// end
|
||||||
|
// else begin
|
||||||
|
// player2_scored <= 1;
|
||||||
|
// end
|
||||||
|
// end
|
||||||
|
// enermy4_tank_move_en <= 1;
|
||||||
|
// // if ( player2_tank_collide[ 0 ] && player2_moving ) begin
|
||||||
|
// // player2_tank_move_en <= 0;
|
||||||
|
// // end
|
||||||
|
// end
|
||||||
|
always @( posedge clk ) begin: player2_tank_enable_signal
|
||||||
|
|
||||||
|
if ( player2_revive ) begin
|
||||||
|
player2_tank_en_feedback <= 1;
|
||||||
|
end
|
||||||
|
else if ( !reset_n ) begin
|
||||||
|
player2_tank_en_feedback <= 1;
|
||||||
|
end
|
||||||
|
// else if ( !player2_tank_en_feedback ) begin
|
||||||
|
// player2_tank_en_feedback <= 0;
|
||||||
|
// end
|
||||||
|
else if ( player1_bullet_collide[ 4 ] ) begin
|
||||||
|
player2_tank_en_feedback <= 0;
|
||||||
|
end
|
||||||
|
// else begin
|
||||||
|
// player2_tank_en_feedback <= 1;
|
||||||
|
// end
|
||||||
|
|
||||||
// player2_tank_en_feedback <= ~player1_bullet_collide[1];
|
// player2_tank_en_feedback <= ~player1_bullet_collide[1];
|
||||||
|
|
||||||
player2_tank_move_en <= 1;
|
player2_tank_move_en <= 1;
|
||||||
if(player2_tank_collide[0] && player2_moving) player2_tank_move_en <= 0;
|
if ( player2_tank_collide[ 0 ] && player2_moving ) begin
|
||||||
|
player2_tank_move_en <= 0;
|
||||||
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
||||||
always @(*) begin: player1_tank_enable_signal
|
always @( posedge clk ) begin: player1_tank_enable_signal
|
||||||
if(player1_revive) player1_tank_en_feedback <= 1;
|
if ( player1_revive ) begin
|
||||||
else if(!reset_n) player1_tank_en_feedback <= 1;
|
player1_tank_en_feedback <= 1;
|
||||||
else if(!player1_tank_en_feedback) player1_tank_en_feedback <= 0;
|
end
|
||||||
else if(player1_tank_collide[5]) player1_tank_en_feedback <= 0;
|
else if ( !reset_n ) begin
|
||||||
else player1_tank_en_feedback <= 1;
|
player1_tank_en_feedback <= 1;
|
||||||
|
end
|
||||||
|
// else if ( !player1_tank_en_feedback ) begin
|
||||||
|
// player1_tank_en_feedback <= 0;
|
||||||
|
// end
|
||||||
|
else if ( player2_bullet_collide[ 4 ] ) begin
|
||||||
|
player1_tank_en_feedback <= 0;
|
||||||
|
end
|
||||||
|
// else begin
|
||||||
|
// player1_tank_en_feedback <= 1;
|
||||||
|
// end
|
||||||
|
|
||||||
player1_tank_move_en <= 1;
|
player1_tank_move_en <= 1;
|
||||||
if(player1_tank_collide[1] && player1_moving) player1_tank_move_en <= 0;
|
if ( player1_tank_collide[ 1 ] && player1_moving ) begin
|
||||||
|
player1_tank_move_en <= 0;
|
||||||
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -46,6 +46,7 @@ module game_logic_classic(
|
||||||
);
|
);
|
||||||
reg [ 3: 0 ] score1;
|
reg [ 3: 0 ] score1;
|
||||||
reg [ 3: 0 ] score2;
|
reg [ 3: 0 ] score2;
|
||||||
|
reg mytank1_state_last, mytank2_state_last;
|
||||||
initial begin
|
initial begin
|
||||||
gameover_classic <= 0;
|
gameover_classic <= 0;
|
||||||
|
|
||||||
|
|
@ -55,29 +56,50 @@ initial begin
|
||||||
score2 <= 0;
|
score2 <= 0;
|
||||||
score_classic <= 0;
|
score_classic <= 0;
|
||||||
end
|
end
|
||||||
always@( negedge enable_game_classic or negedge mytank1_state ) begin
|
|
||||||
if ( item_invincible == 0 ) begin
|
always @( posedge clk ) begin
|
||||||
|
if ( ~item_invincible && mytank1_state_last && ~mytank1_state ) begin
|
||||||
HP1_value <= HP1_value - 1;
|
HP1_value <= HP1_value - 1;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
HP1_value <= HP1_value;
|
HP1_value <= HP1_value;
|
||||||
end
|
end
|
||||||
if ( enable_game_classic == 1'b0 ) begin
|
if ( ~item_invincible && mytank2_state_last && ~mytank2_state ) begin
|
||||||
HP1_value <= 4;
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always@( negedge enable_game_classic or negedge mytank2_state ) begin
|
|
||||||
if ( item_invincible == 0 ) begin
|
|
||||||
HP2_value <= HP2_value - 1;
|
HP2_value <= HP2_value - 1;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
HP2_value <= HP2_value;
|
HP2_value <= HP2_value;
|
||||||
end
|
end
|
||||||
if ( enable_game_classic == 1'b0 ) begin
|
if ( enable_game_classic == 1'b0 ) begin
|
||||||
|
HP1_value <= 4;
|
||||||
HP2_value <= 4;
|
HP2_value <= 4;
|
||||||
end
|
end
|
||||||
|
mytank1_state_last <= mytank1_state;
|
||||||
|
mytank2_state_last <= mytank2_state;
|
||||||
end
|
end
|
||||||
|
// always@( negedge enable_game_classic or negedge mytank1_state ) begin
|
||||||
|
// if ( item_invincible == 0 ) begin
|
||||||
|
// HP1_value <= HP1_value - 1;
|
||||||
|
// end
|
||||||
|
// else begin
|
||||||
|
// HP1_value <= HP1_value;
|
||||||
|
// end
|
||||||
|
// if ( enable_game_classic == 1'b0 ) begin
|
||||||
|
// HP1_value <= 4;
|
||||||
|
// end
|
||||||
|
// end
|
||||||
|
|
||||||
|
// always@( negedge enable_game_classic or negedge mytank2_state ) begin
|
||||||
|
// if ( item_invincible == 0 ) begin
|
||||||
|
// HP2_value <= HP2_value - 1;
|
||||||
|
// end
|
||||||
|
// else begin
|
||||||
|
// HP2_value <= HP2_value;
|
||||||
|
// end
|
||||||
|
// if ( enable_game_classic == 1'b0 ) begin
|
||||||
|
// HP2_value <= 4;
|
||||||
|
// end
|
||||||
|
// end
|
||||||
|
|
||||||
always @( posedge clk ) begin
|
always @( posedge clk ) begin
|
||||||
if ( !enable_game_classic ) begin
|
if ( !enable_game_classic ) begin
|
||||||
|
|
|
||||||
|
|
@ -54,7 +54,9 @@ reg [ 3: 0 ] score1;
|
||||||
reg [ 3: 0 ] score2;
|
reg [ 3: 0 ] score2;
|
||||||
reg add_flag;
|
reg add_flag;
|
||||||
reg item_flag;
|
reg item_flag;
|
||||||
reg [ 1: 0 ] HP1, HP2;
|
reg [ 1: 0 ] HP1_value, HP2_value;
|
||||||
|
reg mytank1_state_last, mytank2_state_last;
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
gameover_infinity <= 0;
|
gameover_infinity <= 0;
|
||||||
cnt <= 0;
|
cnt <= 0;
|
||||||
|
|
@ -64,35 +66,55 @@ initial begin
|
||||||
score2 <= 0;
|
score2 <= 0;
|
||||||
add_flag <= 0;
|
add_flag <= 0;
|
||||||
item_flag <= 0;
|
item_flag <= 0;
|
||||||
HP1 <= 2;
|
HP1_value <= 2;
|
||||||
HP2 <= 2;
|
HP2_value <= 2;
|
||||||
end
|
end
|
||||||
|
|
||||||
|
always @( posedge clk ) begin
|
||||||
always @( negedge mytank1_state ) begin
|
if ( ~item_invincible && mytank1_state_last && ~mytank1_state ) begin
|
||||||
if ( item_invincible == 0 ) begin
|
HP1_value <= HP1_value - 1;
|
||||||
HP1 <= HP1 - 1;
|
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
HP1 <= HP1;
|
HP1_value <= HP1_value;
|
||||||
end
|
end
|
||||||
if ( enable_game_infinity == 1'b0 ) begin
|
if ( ~item_invincible && mytank2_state_last && ~mytank2_state ) begin
|
||||||
HP1 <= 2;
|
HP2_value <= HP2_value - 1;
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
always @( negedge mytank2_state ) begin
|
|
||||||
if ( item_invincible == 0 ) begin
|
|
||||||
HP2 <= HP2 - 1;
|
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
HP2 <= HP2;
|
HP2_value <= HP2_value;
|
||||||
end
|
end
|
||||||
if ( enable_game_infinity == 1'b0 ) begin
|
if ( enable_game_infinity == 1'b0 ) begin
|
||||||
HP2 <= 2;
|
HP1_value <= 2;
|
||||||
|
HP2_value <= 2;
|
||||||
end
|
end
|
||||||
|
mytank1_state_last <= mytank1_state;
|
||||||
|
mytank2_state_last <= mytank2_state;
|
||||||
end
|
end
|
||||||
|
|
||||||
|
// always @( negedge mytank1_state ) begin
|
||||||
|
// if ( item_invincible == 0 ) begin
|
||||||
|
// HP1 <= HP1 - 1;
|
||||||
|
// end
|
||||||
|
// else begin
|
||||||
|
// HP1 <= HP1;
|
||||||
|
// end
|
||||||
|
// if ( enable_game_infinity == 1'b0 ) begin
|
||||||
|
// HP1 <= 2;
|
||||||
|
// end
|
||||||
|
// end
|
||||||
|
|
||||||
|
// always @( negedge mytank2_state ) begin
|
||||||
|
// if ( item_invincible == 0 ) begin
|
||||||
|
// HP2 <= HP2 - 1;
|
||||||
|
// end
|
||||||
|
// else begin
|
||||||
|
// HP2 <= HP2;
|
||||||
|
// end
|
||||||
|
// if ( enable_game_infinity == 1'b0 ) begin
|
||||||
|
// HP2 <= 2;
|
||||||
|
// end
|
||||||
|
// end
|
||||||
|
|
||||||
|
|
||||||
always @( posedge clk ) begin
|
always @( posedge clk ) begin
|
||||||
if ( !enable_game_infinity ) begin
|
if ( !enable_game_infinity ) begin
|
||||||
|
|
@ -111,14 +133,15 @@ always @( posedge clk ) begin
|
||||||
end
|
end
|
||||||
|
|
||||||
else begin
|
else begin
|
||||||
if ( timer == 0 || btn_stop || ( | HP1 == 0 ) || ( | HP2 == 0 ) ) begin
|
if ( timer == 0 || btn_stop || ( | HP1_value == 0 ) || ( | HP2_value == 0 ) ) begin
|
||||||
timer <= 16;
|
timer <= 16;
|
||||||
gameover_infinity <= 1;
|
gameover_infinity <= 1;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
if ( score1 < scorea1 + scoreb1 + scorec1 + scored1 ) begin
|
if ( score1 < scorea1 + scoreb1 + scorec1 + scored1 ) begin
|
||||||
if ( add_flag == 0 && timer > 0 && timer < 16 ) begin
|
if ( add_flag == 0 && timer > 0 && timer < 16 ) begin
|
||||||
timer <= timer + 1;
|
timer <= timer + 4;
|
||||||
|
cnt <= 0;
|
||||||
add_flag = 1;
|
add_flag = 1;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
@ -127,7 +150,8 @@ always @( posedge clk ) begin
|
||||||
end
|
end
|
||||||
if ( score2 < scorea2 + scoreb2 + scorec2 + scored2 ) begin
|
if ( score2 < scorea2 + scoreb2 + scorec2 + scored2 ) begin
|
||||||
if ( add_flag == 0 && timer > 0 && timer < 16 ) begin
|
if ( add_flag == 0 && timer > 0 && timer < 16 ) begin
|
||||||
timer <= timer + 1;
|
timer <= timer + 4;
|
||||||
|
cnt <= 0;
|
||||||
add_flag = 1;
|
add_flag = 1;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
|
||||||
|
|
@ -22,43 +22,45 @@
|
||||||
|
|
||||||
module tank_display(
|
module tank_display(
|
||||||
input clk,
|
input clk,
|
||||||
input [1:0] tankDir,
|
input [ 1: 0 ] tankDir,
|
||||||
input tank_destroyed,
|
input tank_destroyed,
|
||||||
input [10:0] vgaH,
|
input [ 2: 0 ] mode,
|
||||||
input [10:0] vgaV, // Current VGA position
|
input tank_revive,
|
||||||
input [10:0] tankH,
|
input [ 10: 0 ] vgaH,
|
||||||
input [10:0] tankV, // Current Y of tank
|
input [ 10: 0 ] vgaV, // Current VGA position
|
||||||
output [11:0] tankData
|
input [ 10: 0 ] tankH,
|
||||||
|
input [ 10: 0 ] tankV, // Current Y of tank
|
||||||
|
output [ 11: 0 ] tankData
|
||||||
);
|
);
|
||||||
|
|
||||||
parameter TANK_HEIGHT = 32;
|
parameter TANK_HEIGHT = 32;
|
||||||
parameter TANK_WIDTH = 32;
|
parameter TANK_WIDTH = 32;
|
||||||
parameter HEIGHT = 480;
|
parameter HEIGHT = 480;
|
||||||
parameter WIDTH = 640;
|
parameter WIDTH = 640;
|
||||||
|
|
||||||
wire tank_en;
|
wire tank_en;
|
||||||
assign tank_en = (tankH + TANK_WIDTH > vgaH && tankH <= vgaH &&
|
assign tank_en = ( tankH + TANK_WIDTH > vgaH && tankH <= vgaH &&
|
||||||
tankV + TANK_HEIGHT > vgaV && tankV <= vgaV) ? 1'b1:1'b0;
|
tankV + TANK_HEIGHT > vgaV && tankV <= vgaV ) && ( mode == 1 || mode == 2 ) ? 1'b1 : 1'b0;
|
||||||
|
|
||||||
|
|
||||||
wire [9:0] tankAddr;
|
wire [ 9: 0 ] tankAddr;
|
||||||
|
|
||||||
wire [11:0] tankLeftData;
|
wire [ 11: 0 ] tankLeftData;
|
||||||
wire [11:0] tankRightData;
|
wire [ 11: 0 ] tankRightData;
|
||||||
wire [11:0] tankUpData;
|
wire [ 11: 0 ] tankUpData;
|
||||||
wire [11:0] tankDownData;
|
wire [ 11: 0 ] tankDownData;
|
||||||
wire [11:0] outData;
|
wire [ 11: 0 ] outData;
|
||||||
|
|
||||||
assign tankAddr = tank_en ? ( (vgaV - tankV) * TANK_WIDTH + (vgaH - tankH)) : 1'b0;
|
assign tankAddr = tank_en ? ( ( vgaV - tankV ) * TANK_WIDTH + ( vgaH - tankH ) ) : 1'b0;
|
||||||
|
|
||||||
tank_left_img tank_left(.addra(tankAddr), .clka(clk), .douta(tankLeftData), .ena(1'b1));
|
tank_left_img tank_left( .addra( tankAddr ), .clka( clk ), .douta( tankLeftData ), .ena( 1'b1 ) );
|
||||||
tank_right_img tank_right(.addra(tankAddr), .clka(clk), .douta(tankRightData), .ena(1'b1));
|
tank_right_img tank_right( .addra( tankAddr ), .clka( clk ), .douta( tankRightData ), .ena( 1'b1 ) );
|
||||||
tank_up_img tank_up(.addra(tankAddr), .clka(clk), .douta(tankUpData), .ena(1'b1));
|
tank_up_img tank_up( .addra( tankAddr ), .clka( clk ), .douta( tankUpData ), .ena( 1'b1 ) );
|
||||||
tank_down_img tank_down(.addra(tankAddr), .clka(clk), .douta(tankDownData), .ena(1'b1));
|
tank_down_img tank_down( .addra( tankAddr ), .clka( clk ), .douta( tankDownData ), .ena( 1'b1 ) );
|
||||||
|
|
||||||
tank_data_selector tank_select(.clk(clk), .UP(tankUpData), .DOWN(tankDownData), .LEFT(tankLeftData),
|
tank_data_selector tank_select( .clk( clk ), .UP( tankUpData ), .DOWN( tankDownData ), .LEFT( tankLeftData ),
|
||||||
.RIGHT(tankRightData), .Dir(tankDir), .tankData(outData));
|
.RIGHT( tankRightData ), .Dir( tankDir ), .tankData( outData ) );
|
||||||
|
|
||||||
assign tankData = (tank_en & ~tank_destroyed) ? outData : 0;
|
assign tankData = ( tank_en & ~tank_destroyed ) ? outData : 0;
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,124 @@
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Company:
|
||||||
|
// Engineer:
|
||||||
|
//
|
||||||
|
// Create Date: 12/31/2020 05:00:13 PM
|
||||||
|
// Design Name:
|
||||||
|
// Module Name: tank_generate
|
||||||
|
// Project Name:
|
||||||
|
// Target Devices:
|
||||||
|
// Tool Versions:
|
||||||
|
// Description:
|
||||||
|
//
|
||||||
|
// Dependencies:
|
||||||
|
//
|
||||||
|
// Revision:
|
||||||
|
// Revision 0.01 - File Created
|
||||||
|
// Additional Comments:
|
||||||
|
//
|
||||||
|
//////////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
|
||||||
|
module tank_generate(
|
||||||
|
input clk_4Hz,
|
||||||
|
input player1_tank_en,
|
||||||
|
input player2_tank_en,
|
||||||
|
input enermy1_tank_en,
|
||||||
|
input enermy2_tank_en,
|
||||||
|
input enermy3_tank_en,
|
||||||
|
input enermy4_tank_en,
|
||||||
|
output reg player1_revive,
|
||||||
|
output reg player2_revive,
|
||||||
|
output reg enermy1_revive,
|
||||||
|
output reg enermy2_revive,
|
||||||
|
output reg enermy3_revive,
|
||||||
|
output reg enermy4_revive
|
||||||
|
);
|
||||||
|
|
||||||
|
reg [ 4: 0 ] cnt_reg_player1, cnt_reg_player2;
|
||||||
|
reg [ 4: 0 ] cnt_reg_enermy1, cnt_reg_enermy2, cnt_reg_enermy3, cnt_reg_enermy4;
|
||||||
|
initial begin
|
||||||
|
cnt_reg_player1 <= 0;
|
||||||
|
cnt_reg_player2 <= 0;
|
||||||
|
cnt_reg_enermy1 <= 0;
|
||||||
|
cnt_reg_enermy2 <= 0;
|
||||||
|
cnt_reg_enermy3 <= 0;
|
||||||
|
cnt_reg_enermy4 <= 0;
|
||||||
|
player1_revive <= 0;
|
||||||
|
player2_revive <= 0;
|
||||||
|
enermy1_revive <= 0;
|
||||||
|
enermy2_revive <= 0;
|
||||||
|
enermy3_revive <= 0;
|
||||||
|
enermy4_revive <= 0;
|
||||||
|
end
|
||||||
|
|
||||||
|
always @( posedge clk_4Hz ) begin
|
||||||
|
if ( !player1_tank_en ) begin
|
||||||
|
cnt_reg_player1 <= cnt_reg_player1 + 1'b1;
|
||||||
|
end
|
||||||
|
if ( !player2_tank_en ) begin
|
||||||
|
cnt_reg_player2 <= cnt_reg_player2 + 1'b1;
|
||||||
|
end
|
||||||
|
if ( !enermy1_tank_en ) begin
|
||||||
|
cnt_reg_enermy1 <= cnt_reg_enermy1 + 1'b1;
|
||||||
|
end
|
||||||
|
if ( !enermy2_tank_en ) begin
|
||||||
|
cnt_reg_enermy2 <= cnt_reg_enermy2 + 1'b1;
|
||||||
|
end
|
||||||
|
if ( !enermy3_tank_en ) begin
|
||||||
|
cnt_reg_enermy3 <= cnt_reg_enermy3 + 1'b1;
|
||||||
|
end
|
||||||
|
if ( !enermy4_tank_en ) begin
|
||||||
|
cnt_reg_enermy4 <= cnt_reg_enermy4 + 1'b1;
|
||||||
|
end
|
||||||
|
if ( cnt_reg_player1 >= 12 && cnt_reg_player1 <= 19 ) begin
|
||||||
|
cnt_reg_player1 <= cnt_reg_player1 + 1'b1;
|
||||||
|
player1_revive <= 1'b1;
|
||||||
|
end
|
||||||
|
if ( cnt_reg_player2 >= 12 && cnt_reg_player2 <= 19 ) begin
|
||||||
|
cnt_reg_player2 <= cnt_reg_player2 + 1'b1;
|
||||||
|
player2_revive <= 1'b1;
|
||||||
|
end
|
||||||
|
if ( cnt_reg_enermy1 >= 12 && cnt_reg_enermy1 <= 19 ) begin
|
||||||
|
cnt_reg_enermy1 <= cnt_reg_enermy1 + 1'b1;
|
||||||
|
enermy1_revive <= 1'b1;
|
||||||
|
end
|
||||||
|
if ( cnt_reg_enermy2 >= 12 && cnt_reg_enermy2 <= 19 ) begin
|
||||||
|
cnt_reg_enermy2 <= cnt_reg_enermy2 + 1'b1;
|
||||||
|
enermy2_revive <= 1'b1;
|
||||||
|
end
|
||||||
|
if ( cnt_reg_enermy3 >= 12 && cnt_reg_enermy3 <= 19 ) begin
|
||||||
|
cnt_reg_enermy3 <= cnt_reg_enermy3 + 1'b1;
|
||||||
|
enermy3_revive <= 1'b1;
|
||||||
|
end
|
||||||
|
if ( cnt_reg_enermy4 >= 12 && cnt_reg_enermy4 <= 19 ) begin
|
||||||
|
cnt_reg_enermy4 <= cnt_reg_enermy4 + 1'b1;
|
||||||
|
enermy4_revive <= 1'b1;
|
||||||
|
end
|
||||||
|
if ( cnt_reg_player1 == 20 ) begin
|
||||||
|
cnt_reg_player1 <= 0;
|
||||||
|
player1_revive <= 1'b0;
|
||||||
|
end
|
||||||
|
if ( cnt_reg_player2 == 20 ) begin
|
||||||
|
cnt_reg_player2 <= 0;
|
||||||
|
player2_revive <= 1'b0;
|
||||||
|
end
|
||||||
|
if ( cnt_reg_enermy1 == 20 ) begin
|
||||||
|
cnt_reg_enermy1 <= 0;
|
||||||
|
enermy1_revive <= 1'b0;
|
||||||
|
end
|
||||||
|
if ( cnt_reg_enermy2 == 20 ) begin
|
||||||
|
cnt_reg_enermy2 <= 0;
|
||||||
|
enermy2_revive <= 1'b0;
|
||||||
|
end
|
||||||
|
if ( cnt_reg_enermy3 == 20 ) begin
|
||||||
|
cnt_reg_enermy3 <= 0;
|
||||||
|
enermy3_revive <= 1'b0;
|
||||||
|
end
|
||||||
|
if ( cnt_reg_enermy4 == 20 ) begin
|
||||||
|
cnt_reg_enermy4 <= 0;
|
||||||
|
enermy4_revive <= 1'b0;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
|
|
@ -11,13 +11,13 @@ input clk;
|
||||||
input moving;
|
input moving;
|
||||||
input reset_n;
|
input reset_n;
|
||||||
input start;
|
input start;
|
||||||
input [ 9: 0 ] init_H;
|
input [ 10: 0 ] init_H;
|
||||||
input [ 9: 0 ] init_V;
|
input [ 10: 0 ] init_V;
|
||||||
input [ 1: 0 ] tank_dir;
|
input [ 1: 0 ] tank_dir;
|
||||||
input tank_en;
|
input tank_en;
|
||||||
input tank_move_en;
|
input tank_move_en;
|
||||||
output reg [ 9: 0 ] tank_H;
|
output reg [ 10: 0 ] tank_H;
|
||||||
output reg [ 9: 0 ] tank_V;
|
output reg [ 10: 0 ] tank_V;
|
||||||
output reg [ 2: 0 ] tank_dir_feedback;
|
output reg [ 2: 0 ] tank_dir_feedback;
|
||||||
|
|
||||||
parameter HEIGHT = 480;
|
parameter HEIGHT = 480;
|
||||||
|
|
@ -86,7 +86,7 @@ always @( * ) begin: state_table
|
||||||
INITIAL:
|
INITIAL:
|
||||||
next_state = STAY;
|
next_state = STAY;
|
||||||
STAY, UP, DOWN, LEFT, RIGHT: begin
|
STAY, UP, DOWN, LEFT, RIGHT: begin
|
||||||
if ( !tank_move_en || !moving ) begin
|
if ( !tank_en || !tank_move_en || !moving ) begin
|
||||||
next_state = STAY;
|
next_state = STAY;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
|
|
|
||||||
|
|
@ -3,24 +3,38 @@
|
||||||
|
|
||||||
module vga_data_selector(
|
module vga_data_selector(
|
||||||
input clk,
|
input clk,
|
||||||
input [11:0] in1,
|
input [ 11: 0 ] in1,
|
||||||
input [11:0] in2,
|
input [ 11: 0 ] in2,
|
||||||
input [11:0] in3,
|
input [ 11: 0 ] in3,
|
||||||
input [11:0] in4,
|
input [ 11: 0 ] in4,
|
||||||
output [11:0] out
|
input [ 11: 0 ] in5,
|
||||||
|
input [ 11: 0 ] in6,
|
||||||
|
input [ 11: 0 ] in7,
|
||||||
|
input [ 11: 0 ] in8,
|
||||||
|
input [ 11: 0 ] in9,
|
||||||
|
input [ 11: 0 ] in10,
|
||||||
|
input [ 11: 0 ] in11,
|
||||||
|
input [ 11: 0 ] in12,
|
||||||
|
input [ 11: 0 ] in13,
|
||||||
|
input [ 11: 0 ] in14,
|
||||||
|
input [ 11: 0 ] in15,
|
||||||
|
input [ 11: 0 ] in16,
|
||||||
|
input [ 11: 0 ] in17,
|
||||||
|
|
||||||
|
output [ 11: 0 ] out
|
||||||
);
|
);
|
||||||
|
|
||||||
assign out[0] = in1[0] | in2[0] | in3[0] | in4[0];
|
assign out[ 0 ] = in1[ 0 ] | in2[ 0 ] | in3[ 0 ] | in4[ 0 ] | in5[ 0 ] | in6[ 0 ] | in7[ 0 ] | in8[ 0 ] | in9[ 0 ] | in10[ 0 ] | in11[ 0 ] | in12[ 0 ] | in13[ 0 ] | in14[ 0 ] | in15[ 0 ] | in16[ 0 ] | in17[ 0 ] ;
|
||||||
assign out[1] = in1[1] | in2[1] | in3[1] | in4[1];
|
assign out[ 1 ] = in1[ 1 ] | in2[ 1 ] | in3[ 1 ] | in4[ 1 ] | in5[ 1 ] | in6[ 1 ] | in7[ 1 ] | in8[ 1 ] | in9[ 1 ] | in10[ 1 ] | in11[ 1 ] | in12[ 1 ] | in13[ 1 ] | in14[ 1 ] | in15[ 1 ] | in16[ 1 ] | in17[ 1 ] ;
|
||||||
assign out[2] = in1[2] | in2[2] | in3[2] | in4[2];
|
assign out[ 2 ] = in1[ 2 ] | in2[ 2 ] | in3[ 2 ] | in4[ 2 ] | in5[ 2 ] | in6[ 2 ] | in7[ 2 ] | in8[ 2 ] | in9[ 2 ] | in10[ 2 ] | in11[ 2 ] | in12[ 2 ] | in13[ 2 ] | in14[ 2 ] | in15[ 2 ] | in16[ 2 ] | in17[ 2 ] ;
|
||||||
assign out[3] = in1[3] | in2[3] | in3[3] | in4[3];
|
assign out[ 3 ] = in1[ 3 ] | in2[ 3 ] | in3[ 3 ] | in4[ 3 ] | in5[ 3 ] | in6[ 3 ] | in7[ 3 ] | in8[ 3 ] | in9[ 3 ] | in10[ 3 ] | in11[ 3 ] | in12[ 3 ] | in13[ 3 ] | in14[ 3 ] | in15[ 3 ] | in16[ 3 ] | in17[ 3 ] ;
|
||||||
assign out[4] = in1[4] | in2[4] | in3[4] | in4[4];
|
assign out[ 4 ] = in1[ 4 ] | in2[ 4 ] | in3[ 4 ] | in4[ 4 ] | in5[ 4 ] | in6[ 4 ] | in7[ 4 ] | in8[ 4 ] | in9[ 4 ] | in10[ 4 ] | in11[ 4 ] | in12[ 4 ] | in13[ 4 ] | in14[ 4 ] | in15[ 4 ] | in16[ 4 ] | in17[ 4 ] ;
|
||||||
assign out[5] = in1[5] | in2[5] | in3[5] | in4[5];
|
assign out[ 5 ] = in1[ 5 ] | in2[ 5 ] | in3[ 5 ] | in4[ 5 ] | in5[ 5 ] | in6[ 5 ] | in7[ 5 ] | in8[ 5 ] | in9[ 5 ] | in10[ 5 ] | in11[ 5 ] | in12[ 5 ] | in13[ 5 ] | in14[ 5 ] | in15[ 5 ] | in16[ 5 ] | in17[ 5 ] ;
|
||||||
assign out[6] = in1[6] | in2[6] | in3[6] | in4[6];
|
assign out[ 6 ] = in1[ 6 ] | in2[ 6 ] | in3[ 6 ] | in4[ 6 ] | in5[ 6 ] | in6[ 6 ] | in7[ 6 ] | in8[ 6 ] | in9[ 6 ] | in10[ 6 ] | in11[ 6 ] | in12[ 6 ] | in13[ 6 ] | in14[ 6 ] | in15[ 6 ] | in16[ 6 ] | in17[ 6 ] ;
|
||||||
assign out[7] = in1[7] | in2[7] | in3[7] | in4[7];
|
assign out[ 7 ] = in1[ 7 ] | in2[ 7 ] | in3[ 7 ] | in4[ 7 ] | in5[ 7 ] | in6[ 7 ] | in7[ 7 ] | in8[ 7 ] | in9[ 7 ] | in10[ 7 ] | in11[ 7 ] | in12[ 7 ] | in13[ 7 ] | in14[ 7 ] | in15[ 7 ] | in16[ 7 ] | in17[ 7 ] ;
|
||||||
assign out[8] = in1[8] | in2[8] | in3[8] | in4[8];
|
assign out[ 8 ] = in1[ 8 ] | in2[ 8 ] | in3[ 8 ] | in4[ 8 ] | in5[ 8 ] | in6[ 8 ] | in7[ 8 ] | in8[ 8 ] | in9[ 8 ] | in10[ 8 ] | in11[ 8 ] | in12[ 8 ] | in13[ 8 ] | in14[ 8 ] | in15[ 8 ] | in16[ 8 ] | in17[ 8 ] ;
|
||||||
assign out[9] = in1[9] | in2[9] | in3[9] | in4[9];
|
assign out[ 9 ] = in1[ 9 ] | in2[ 9 ] | in3[ 9 ] | in4[ 9 ] | in5[ 9 ] | in6[ 9 ] | in7[ 9 ] | in8[ 9 ] | in9[ 9 ] | in10[ 9 ] | in11[ 9 ] | in12[ 9 ] | in13[ 9 ] | in14[ 9 ] | in15[ 9 ] | in16[ 9 ] | in17[ 9 ] ;
|
||||||
assign out[10] = in1[10] | in2[10] | in3[10] | in4[10];
|
assign out[ 10 ] = in1[ 10 ] | in2[ 10 ] | in3[ 10 ] | in4[ 10 ] | in5[ 10 ] | in6[ 10 ] | in7[ 10 ] | in8[ 10 ] | in9[ 10 ] | in10[ 10 ] | in11[ 10 ] | in12[ 10 ] | in13[ 10 ] | in14[ 10 ] | in15[ 10 ] | in16[ 10 ] | in17[ 10 ] ;
|
||||||
assign out[11] = in1[11] | in2[11] | in3[11] | in4[11];
|
assign out[ 11 ] = in1[ 11 ] | in2[ 11 ] | in3[ 11 ] | in4[ 11 ] | in5[ 10 ] | in6[ 11 ] | in7[ 11 ] | in8[ 11 ] | in9[ 11 ] | in10[ 10 ] | in11[ 11 ] | in12[ 11 ] | in13[ 11 ] | in14[ 11 ] | in15[ 10 ] | in16[ 11 ] | in17[ 11 ] ;
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue