01/02 some easy ai and some pic
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2019.2:
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* Version 8.4 (Rev. 4)
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* Feature Enhancement: Read Latency parameters exposed to IP GUI for URAM configurations
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2019.1.3:
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* Version 8.4 (Rev. 3)
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* No changes
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2019.1.2:
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* Version 8.4 (Rev. 3)
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* No changes
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2019.1.1:
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* Version 8.4 (Rev. 3)
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* No changes
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2019.1:
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* Version 8.4 (Rev. 3)
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* General: Internal device family change, no functional changes
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2018.3.1:
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* Version 8.4 (Rev. 2)
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* No changes
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2018.3:
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* Version 8.4 (Rev. 2)
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* Feature Enhancement: Read Latency Support added for URAM when selected through IP Integrator
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* Other: Power Calculations disabled for URAM primitives in IP GUI, no functional changes
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* Other: Internal device family change, no functional changes
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2018.2:
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* Version 8.4 (Rev. 1)
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* No changes
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2018.1:
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* Version 8.4 (Rev. 1)
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* No changes
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2017.4:
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* Version 8.4 (Rev. 1)
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* General: Write depth shown in IP GUI is now dependent on number of BRAMs available in a chosen device, no functional changes
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2017.3:
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* Version 8.4
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* General: Safety Circuit option is enabled by default if reset option in any one port is enabled
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2017.2:
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* Version 8.3 (Rev. 6)
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* No changes
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2017.1:
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* Version 8.3 (Rev. 6)
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* General: Internal device family change, no functional changes
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* General: When common_clock is selected clkb is internally connected to clka, but the interface remains same to support the backword compatiability. User make sure of connecting the both the clocks to same clock source when in common_clock mode
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2016.4:
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* Version 8.3 (Rev. 5)
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* General: Fixes for behavioral Model issues when built-IN ECC is enabled (to be consistent with RTL)
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2016.3:
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* Version 8.3 (Rev. 4)
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* Feature Enhancement: URAM addressing updates while calling XPM_Memory when 32-bit addressing is enabled
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* Other: Enable support for future devices
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* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
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2016.2:
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* Version 8.3 (Rev. 3)
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* updated the IP,not to set WRITE_DEPTH parameter to 8192 everytime when the mode is switched to BRAM_Controller
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* Updated the IP to support the device package changes
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2016.1:
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* Version 8.3 (Rev. 2)
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* Updated the IP to deliver only verilog behavioral model
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* Updated the IP to support UltraRAM in IP Integrator
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* Updated the IP to support the device package changes
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2015.4.2:
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* Version 8.3 (Rev. 1)
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* No changes
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2015.4.1:
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* Version 8.3 (Rev. 1)
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* No changes
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2015.4:
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* Version 8.3 (Rev. 1)
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* Updated the IP to support the device package changes
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2015.3:
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* Version 8.3
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* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
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* New ports rsta_busy and rstb_busy are added to enable the safety circuitry to minimize the occurrence of BRAM data corruption
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* Simulation models are delivered in VHDL only
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2015.2.1:
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* Version 8.2 (Rev. 5)
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* No changes
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2015.2:
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* Version 8.2 (Rev. 5)
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* No changes
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2015.1:
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* Version 8.2 (Rev. 5)
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* Delivering non encrypted behavioral models
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* Supported memory depth is increased up to 1M words
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* Added the power saving feature (RDADDRCHG) for ultrascale devices
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* Supported devices and production status are now determined automatically, to simplify support for future devices
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2014.4.1:
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* Version 8.2 (Rev. 4)
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* Updated the IP to support the device package changes
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2014.4:
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* Version 8.2 (Rev. 3)
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* Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
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* Added support for 7-series Automotive (XA) and Defense Grade (XQ) devices
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* Internal device family change, no functional changes
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2014.3:
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* Version 8.2 (Rev. 2)
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* Fixed the Memory Resource Doubling issue in Simple Dual Port RAM when aspect ratio is used
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* Fixed the GUI crash in Simple Dual Port RAM
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* Added support of all write modes in Simple Dual Port RAM when ECC is not used
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* Increased the supported depth to a maximum value of 256k
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2014.2:
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||||
* Version 8.2 (Rev. 1)
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* Updated the GUI tool tip for Byte write enable in the page-1 of block memory generator GUI
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2014.1:
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||||
* Version 8.2
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||||
* Added support of the cascaded Primitives of widths 1 and 2 for ultra-scale devices
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* Added support of the ECCPIPE register in the built-in ecc mode for ultra-scale devices
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* Added support of the dynamic power saving for ultra-scale devices
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* Improved timing efficiency in the IP Integrator by minimizing the use of output mux for the 7-series devices
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* Internal device family name change, no functional changes
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2013.4:
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* Version 8.1
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* The Primitive output registers are made "ON" by default in the stand alone mode
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* Added cascaded support for ultrascale devices to construct 64Kx1 primitive by using two 32Kx1 primitives
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* Added support for ultrascale devices
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2013.3:
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* Version 8.0 (Rev. 2)
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* Added parameter "CTRL_ECC_ALGO" for supporting ECC in IP Integrator.
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* Improved GUI speed and responsivness, no functional changes
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* Reduced synthesis and simulation warnings
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* Added support for Cadence IES and Synopsys VCS simulators
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* Changed the default option of ENABLE PORT TYPE to "USE_ENA_PIN"
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* Changed BRAM Interface DIN and DOUT to match bus interface directions.
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2013.2:
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||||
* Version 8.0 (Rev. 1)
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* No Changes
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2013.1:
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* Version 8.0
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* Native Vivado Release
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* There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1.
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(c) Copyright 2002 - 2019 Xilinx, Inc. All rights reserved.
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||||
This file contains confidential and proprietary information
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||||
of Xilinx, Inc. and is protected under U.S. and
|
||||
international copyright and other intellectual property
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||||
laws.
|
||||
|
||||
DISCLAIMER
|
||||
This disclaimer is not a license and does not grant any
|
||||
rights to the materials distributed herewith. Except as
|
||||
otherwise provided in a valid license issued to you by
|
||||
Xilinx, and to the maximum extent permitted by applicable
|
||||
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
(2) Xilinx shall not be liable (whether in contract or tort,
|
||||
including negligence, or under any other theory of
|
||||
liability) for any loss or damage of any kind or nature
|
||||
related to, arising under or in connection with these
|
||||
materials, including for any direct, or any indirect,
|
||||
special, incidental, or consequential loss or damage
|
||||
(including loss of data, profits, goodwill, or any type of
|
||||
loss or damage suffered as a result of any action brought
|
||||
by a third party) even if such damage or loss was
|
||||
reasonably foreseeable or Xilinx had been advised of the
|
||||
possibility of the same.
|
||||
|
||||
CRITICAL APPLICATIONS
|
||||
Xilinx products are not designed or intended to be fail-
|
||||
safe, or for use in any application requiring fail-safe
|
||||
performance, such as life-support or safety devices or
|
||||
systems, Class III medical devices, nuclear facilities,
|
||||
applications related to the deployment of airbags, or any
|
||||
other applications that could lead to death, personal
|
||||
injury, or severe property or environmental damage
|
||||
(individually and collectively, "Critical
|
||||
Applications"). Customer assumes the sole risk and
|
||||
liability of any use of Xilinx products in Critical
|
||||
Applications, subject only to applicable laws and
|
||||
regulations governing limitations on product liability.
|
||||
|
||||
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
PART OF THIS FILE AT ALL TIMES.
|
||||
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<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>infinity_info_180_24</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.4"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="ADDRBLOCK_RANGE.S_1.Mem0">4096</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">OTHER</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">8192</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">OTHER</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE">8192</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_18K_BRAM">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP : 4.374319 mW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">artix7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">infinity_info_180_24.mem</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">infinity_info_180_24.mif</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">4320</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">4320</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">4320</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">4320</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">artix7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">../../../pic/infinity_info_180_24.coe</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">infinity_info_180_24</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Use_ENA_Pin</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Single_Port_ROM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">WRITE_FIRST</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">WRITE_FIRST</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_A">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_B">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">4320</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a100t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">csg324</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coe_File" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Load_Init_File" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_A_Write_Rate" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,55 @@
|
||||
################################################################################
|
||||
#
|
||||
# (c) Copyright 2002 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
# Core Period Constraint. This constraint can be modified, and is
|
||||
# valid as long as it is met after place and route.
|
||||
create_clock -name "TS_CLKA" -period 20.0 [ get_ports clka ]
|
||||
set_property HD.CLK_SRC BUFGCTRL_X0Y0 [ get_ports clka ]
|
||||
################################################################################
|
||||
File diff suppressed because it is too large
Load Diff
+1765
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,150 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity blk_mem_gen_v8_4_4 is
|
||||
generic (
|
||||
C_FAMILY : string := "virtex7";
|
||||
C_XDEVICEFAMILY : string := "virtex7";
|
||||
C_ELABORATION_DIR : string := "";
|
||||
C_INTERFACE_TYPE : integer := 0;
|
||||
C_AXI_TYPE : integer := 1;
|
||||
C_AXI_SLAVE_TYPE : integer := 0;
|
||||
C_USE_BRAM_BLOCK : integer := 0;
|
||||
C_ENABLE_32BIT_ADDRESS : integer := 0;
|
||||
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
|
||||
C_HAS_AXI_ID : integer := 0;
|
||||
C_AXI_ID_WIDTH : integer := 4;
|
||||
C_MEM_TYPE : integer := 2;
|
||||
C_BYTE_SIZE : integer := 9;
|
||||
C_ALGORITHM : integer := 0;
|
||||
C_PRIM_TYPE : integer := 3;
|
||||
C_LOAD_INIT_FILE : integer := 0;
|
||||
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
|
||||
C_INIT_FILE : string := "no_mem_file_loaded";
|
||||
C_USE_DEFAULT_DATA : integer := 0;
|
||||
C_DEFAULT_DATA : string := "0";
|
||||
C_HAS_RSTA : integer := 0;
|
||||
C_RST_PRIORITY_A : string := "ce";
|
||||
C_RSTRAM_A : integer := 0;
|
||||
C_INITA_VAL : string := "0";
|
||||
C_HAS_ENA : integer := 1;
|
||||
C_HAS_REGCEA : integer := 0;
|
||||
C_USE_BYTE_WEA : integer := 0;
|
||||
C_WEA_WIDTH : integer := 1;
|
||||
C_WRITE_MODE_A : string := "WRITE_FIRST";
|
||||
C_WRITE_WIDTH_A : integer := 9;
|
||||
C_READ_WIDTH_A : integer := 9;
|
||||
C_WRITE_DEPTH_A : integer := 2048;
|
||||
C_READ_DEPTH_A : integer := 2048;
|
||||
C_ADDRA_WIDTH : integer := 11;
|
||||
C_HAS_RSTB : integer := 0;
|
||||
C_RST_PRIORITY_B : string := "ce";
|
||||
C_RSTRAM_B : integer := 0;
|
||||
C_INITB_VAL : string := "0";
|
||||
C_HAS_ENB : integer := 1;
|
||||
C_HAS_REGCEB : integer := 0;
|
||||
C_USE_BYTE_WEB : integer := 0;
|
||||
C_WEB_WIDTH : integer := 1;
|
||||
C_WRITE_MODE_B : string := "WRITE_FIRST";
|
||||
C_WRITE_WIDTH_B : integer := 9;
|
||||
C_READ_WIDTH_B : integer := 9;
|
||||
C_WRITE_DEPTH_B : integer := 2048;
|
||||
C_READ_DEPTH_B : integer := 2048;
|
||||
C_ADDRB_WIDTH : integer := 11;
|
||||
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
|
||||
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
|
||||
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
|
||||
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
|
||||
C_MUX_PIPELINE_STAGES : integer := 0;
|
||||
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
|
||||
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
|
||||
C_USE_SOFTECC : integer := 0;
|
||||
C_USE_ECC : integer := 0;
|
||||
C_EN_ECC_PIPE : integer := 0;
|
||||
C_HAS_INJECTERR : integer := 0;
|
||||
C_SIM_COLLISION_CHECK : string := "none";
|
||||
C_COMMON_CLK : integer := 0;
|
||||
C_DISABLE_WARN_BHV_COLL : integer := 0;
|
||||
C_EN_SLEEP_PIN : integer := 0;
|
||||
C_USE_URAM : integer := 0;
|
||||
C_EN_RDADDRA_CHG : integer := 0;
|
||||
C_EN_RDADDRB_CHG : integer := 0;
|
||||
C_EN_DEEPSLEEP_PIN : integer := 0;
|
||||
C_EN_SHUTDOWN_PIN : integer := 0;
|
||||
C_EN_SAFETY_CKT : integer := 0;
|
||||
C_DISABLE_WARN_BHV_RANGE : integer := 0;
|
||||
C_COUNT_36K_BRAM : string := "";
|
||||
C_COUNT_18K_BRAM : string := "";
|
||||
C_EST_POWER_SUMMARY : string := ""
|
||||
);
|
||||
port (
|
||||
clka : in std_logic := '0';
|
||||
rsta : in std_logic := '0';
|
||||
ena : in std_logic := '0';
|
||||
regcea : in std_logic := '0';
|
||||
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
|
||||
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
|
||||
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
|
||||
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
|
||||
clkb : in std_logic := '0';
|
||||
rstb : in std_logic := '0';
|
||||
enb : in std_logic := '0';
|
||||
regceb : in std_logic := '0';
|
||||
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
|
||||
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
|
||||
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
|
||||
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
|
||||
injectsbiterr : in std_logic := '0';
|
||||
injectdbiterr : in std_logic := '0';
|
||||
eccpipece : in std_logic := '0';
|
||||
sbiterr : out std_logic;
|
||||
dbiterr : out std_logic;
|
||||
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
|
||||
sleep : in std_logic := '0';
|
||||
deepsleep : in std_logic := '0';
|
||||
shutdown : in std_logic := '0';
|
||||
rsta_busy : out std_logic;
|
||||
rstb_busy : out std_logic;
|
||||
s_aclk : in std_logic := '0';
|
||||
s_aresetn : in std_logic := '0';
|
||||
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
|
||||
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
|
||||
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
|
||||
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
|
||||
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
|
||||
s_axi_awvalid : in std_logic := '0';
|
||||
s_axi_awready : out std_logic;
|
||||
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
|
||||
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
|
||||
s_axi_wlast : in std_logic := '0';
|
||||
s_axi_wvalid : in std_logic := '0';
|
||||
s_axi_wready : out std_logic;
|
||||
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
|
||||
s_axi_bresp : out std_logic_vector(1 downto 0);
|
||||
s_axi_bvalid : out std_logic;
|
||||
s_axi_bready : in std_logic := '0';
|
||||
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
|
||||
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
|
||||
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
|
||||
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
|
||||
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
|
||||
s_axi_arvalid : in std_logic := '0';
|
||||
s_axi_arready : out std_logic;
|
||||
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
|
||||
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
|
||||
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
|
||||
s_axi_rlast : out std_logic;
|
||||
s_axi_rvalid : out std_logic;
|
||||
s_axi_rready : in std_logic := '0';
|
||||
s_axi_injectsbiterr : in std_logic := '0';
|
||||
s_axi_injectdbiterr : in std_logic := '0';
|
||||
s_axi_sbiterr : out std_logic;
|
||||
s_axi_dbiterr : out std_logic;
|
||||
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
|
||||
);
|
||||
end entity blk_mem_gen_v8_4_4;
|
||||
|
||||
architecture xilinx of blk_mem_gen_v8_4_4 is
|
||||
begin
|
||||
end
|
||||
architecture xilinx;
|
||||
@@ -0,0 +1,214 @@
|
||||
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||
// IP Revision: 4
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module infinity_info_180_24 (
|
||||
clka,
|
||||
ena,
|
||||
addra,
|
||||
douta
|
||||
);
|
||||
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
|
||||
input wire clka;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
|
||||
input wire ena;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
|
||||
input wire [12 : 0] addra;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
|
||||
output wire [11 : 0] douta;
|
||||
|
||||
blk_mem_gen_v8_4_4 #(
|
||||
.C_FAMILY("artix7"),
|
||||
.C_XDEVICEFAMILY("artix7"),
|
||||
.C_ELABORATION_DIR("./"),
|
||||
.C_INTERFACE_TYPE(0),
|
||||
.C_AXI_TYPE(1),
|
||||
.C_AXI_SLAVE_TYPE(0),
|
||||
.C_USE_BRAM_BLOCK(0),
|
||||
.C_ENABLE_32BIT_ADDRESS(0),
|
||||
.C_CTRL_ECC_ALGO("NONE"),
|
||||
.C_HAS_AXI_ID(0),
|
||||
.C_AXI_ID_WIDTH(4),
|
||||
.C_MEM_TYPE(3),
|
||||
.C_BYTE_SIZE(9),
|
||||
.C_ALGORITHM(1),
|
||||
.C_PRIM_TYPE(1),
|
||||
.C_LOAD_INIT_FILE(1),
|
||||
.C_INIT_FILE_NAME("infinity_info_180_24.mif"),
|
||||
.C_INIT_FILE("infinity_info_180_24.mem"),
|
||||
.C_USE_DEFAULT_DATA(0),
|
||||
.C_DEFAULT_DATA("0"),
|
||||
.C_HAS_RSTA(0),
|
||||
.C_RST_PRIORITY_A("CE"),
|
||||
.C_RSTRAM_A(0),
|
||||
.C_INITA_VAL("0"),
|
||||
.C_HAS_ENA(1),
|
||||
.C_HAS_REGCEA(0),
|
||||
.C_USE_BYTE_WEA(0),
|
||||
.C_WEA_WIDTH(1),
|
||||
.C_WRITE_MODE_A("WRITE_FIRST"),
|
||||
.C_WRITE_WIDTH_A(12),
|
||||
.C_READ_WIDTH_A(12),
|
||||
.C_WRITE_DEPTH_A(4320),
|
||||
.C_READ_DEPTH_A(4320),
|
||||
.C_ADDRA_WIDTH(13),
|
||||
.C_HAS_RSTB(0),
|
||||
.C_RST_PRIORITY_B("CE"),
|
||||
.C_RSTRAM_B(0),
|
||||
.C_INITB_VAL("0"),
|
||||
.C_HAS_ENB(0),
|
||||
.C_HAS_REGCEB(0),
|
||||
.C_USE_BYTE_WEB(0),
|
||||
.C_WEB_WIDTH(1),
|
||||
.C_WRITE_MODE_B("WRITE_FIRST"),
|
||||
.C_WRITE_WIDTH_B(12),
|
||||
.C_READ_WIDTH_B(12),
|
||||
.C_WRITE_DEPTH_B(4320),
|
||||
.C_READ_DEPTH_B(4320),
|
||||
.C_ADDRB_WIDTH(13),
|
||||
.C_HAS_MEM_OUTPUT_REGS_A(1),
|
||||
.C_HAS_MEM_OUTPUT_REGS_B(0),
|
||||
.C_HAS_MUX_OUTPUT_REGS_A(0),
|
||||
.C_HAS_MUX_OUTPUT_REGS_B(0),
|
||||
.C_MUX_PIPELINE_STAGES(0),
|
||||
.C_HAS_SOFTECC_INPUT_REGS_A(0),
|
||||
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
|
||||
.C_USE_SOFTECC(0),
|
||||
.C_USE_ECC(0),
|
||||
.C_EN_ECC_PIPE(0),
|
||||
.C_READ_LATENCY_A(1),
|
||||
.C_READ_LATENCY_B(1),
|
||||
.C_HAS_INJECTERR(0),
|
||||
.C_SIM_COLLISION_CHECK("ALL"),
|
||||
.C_COMMON_CLK(0),
|
||||
.C_DISABLE_WARN_BHV_COLL(0),
|
||||
.C_EN_SLEEP_PIN(0),
|
||||
.C_USE_URAM(0),
|
||||
.C_EN_RDADDRA_CHG(0),
|
||||
.C_EN_RDADDRB_CHG(0),
|
||||
.C_EN_DEEPSLEEP_PIN(0),
|
||||
.C_EN_SHUTDOWN_PIN(0),
|
||||
.C_EN_SAFETY_CKT(0),
|
||||
.C_DISABLE_WARN_BHV_RANGE(0),
|
||||
.C_COUNT_36K_BRAM("2"),
|
||||
.C_COUNT_18K_BRAM("1"),
|
||||
.C_EST_POWER_SUMMARY("Estimated Power for IP : 4.374319 mW")
|
||||
) inst (
|
||||
.clka(clka),
|
||||
.rsta(1'D0),
|
||||
.ena(ena),
|
||||
.regcea(1'D0),
|
||||
.wea(1'B0),
|
||||
.addra(addra),
|
||||
.dina(12'B0),
|
||||
.douta(douta),
|
||||
.clkb(1'D0),
|
||||
.rstb(1'D0),
|
||||
.enb(1'D0),
|
||||
.regceb(1'D0),
|
||||
.web(1'B0),
|
||||
.addrb(13'B0),
|
||||
.dinb(12'B0),
|
||||
.doutb(),
|
||||
.injectsbiterr(1'D0),
|
||||
.injectdbiterr(1'D0),
|
||||
.eccpipece(1'D0),
|
||||
.sbiterr(),
|
||||
.dbiterr(),
|
||||
.rdaddrecc(),
|
||||
.sleep(1'D0),
|
||||
.deepsleep(1'D0),
|
||||
.shutdown(1'D0),
|
||||
.rsta_busy(),
|
||||
.rstb_busy(),
|
||||
.s_aclk(1'H0),
|
||||
.s_aresetn(1'D0),
|
||||
.s_axi_awid(4'B0),
|
||||
.s_axi_awaddr(32'B0),
|
||||
.s_axi_awlen(8'B0),
|
||||
.s_axi_awsize(3'B0),
|
||||
.s_axi_awburst(2'B0),
|
||||
.s_axi_awvalid(1'D0),
|
||||
.s_axi_awready(),
|
||||
.s_axi_wdata(12'B0),
|
||||
.s_axi_wstrb(1'B0),
|
||||
.s_axi_wlast(1'D0),
|
||||
.s_axi_wvalid(1'D0),
|
||||
.s_axi_wready(),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(),
|
||||
.s_axi_bvalid(),
|
||||
.s_axi_bready(1'D0),
|
||||
.s_axi_arid(4'B0),
|
||||
.s_axi_araddr(32'B0),
|
||||
.s_axi_arlen(8'B0),
|
||||
.s_axi_arsize(3'B0),
|
||||
.s_axi_arburst(2'B0),
|
||||
.s_axi_arvalid(1'D0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'D0),
|
||||
.s_axi_injectsbiterr(1'D0),
|
||||
.s_axi_injectdbiterr(1'D0),
|
||||
.s_axi_sbiterr(),
|
||||
.s_axi_dbiterr(),
|
||||
.s_axi_rdaddrecc()
|
||||
);
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,355 @@
|
||||
-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||
-- IP Revision: 4
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY blk_mem_gen_v8_4_4;
|
||||
USE blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4;
|
||||
|
||||
ENTITY infinity_info_180_24 IS
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
ena : IN STD_LOGIC;
|
||||
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
|
||||
);
|
||||
END infinity_info_180_24;
|
||||
|
||||
ARCHITECTURE infinity_info_180_24_arch OF infinity_info_180_24 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF infinity_info_180_24_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT blk_mem_gen_v8_4_4 IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_XDEVICEFAMILY : STRING;
|
||||
C_ELABORATION_DIR : STRING;
|
||||
C_INTERFACE_TYPE : INTEGER;
|
||||
C_AXI_TYPE : INTEGER;
|
||||
C_AXI_SLAVE_TYPE : INTEGER;
|
||||
C_USE_BRAM_BLOCK : INTEGER;
|
||||
C_ENABLE_32BIT_ADDRESS : INTEGER;
|
||||
C_CTRL_ECC_ALGO : STRING;
|
||||
C_HAS_AXI_ID : INTEGER;
|
||||
C_AXI_ID_WIDTH : INTEGER;
|
||||
C_MEM_TYPE : INTEGER;
|
||||
C_BYTE_SIZE : INTEGER;
|
||||
C_ALGORITHM : INTEGER;
|
||||
C_PRIM_TYPE : INTEGER;
|
||||
C_LOAD_INIT_FILE : INTEGER;
|
||||
C_INIT_FILE_NAME : STRING;
|
||||
C_INIT_FILE : STRING;
|
||||
C_USE_DEFAULT_DATA : INTEGER;
|
||||
C_DEFAULT_DATA : STRING;
|
||||
C_HAS_RSTA : INTEGER;
|
||||
C_RST_PRIORITY_A : STRING;
|
||||
C_RSTRAM_A : INTEGER;
|
||||
C_INITA_VAL : STRING;
|
||||
C_HAS_ENA : INTEGER;
|
||||
C_HAS_REGCEA : INTEGER;
|
||||
C_USE_BYTE_WEA : INTEGER;
|
||||
C_WEA_WIDTH : INTEGER;
|
||||
C_WRITE_MODE_A : STRING;
|
||||
C_WRITE_WIDTH_A : INTEGER;
|
||||
C_READ_WIDTH_A : INTEGER;
|
||||
C_WRITE_DEPTH_A : INTEGER;
|
||||
C_READ_DEPTH_A : INTEGER;
|
||||
C_ADDRA_WIDTH : INTEGER;
|
||||
C_HAS_RSTB : INTEGER;
|
||||
C_RST_PRIORITY_B : STRING;
|
||||
C_RSTRAM_B : INTEGER;
|
||||
C_INITB_VAL : STRING;
|
||||
C_HAS_ENB : INTEGER;
|
||||
C_HAS_REGCEB : INTEGER;
|
||||
C_USE_BYTE_WEB : INTEGER;
|
||||
C_WEB_WIDTH : INTEGER;
|
||||
C_WRITE_MODE_B : STRING;
|
||||
C_WRITE_WIDTH_B : INTEGER;
|
||||
C_READ_WIDTH_B : INTEGER;
|
||||
C_WRITE_DEPTH_B : INTEGER;
|
||||
C_READ_DEPTH_B : INTEGER;
|
||||
C_ADDRB_WIDTH : INTEGER;
|
||||
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
|
||||
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
|
||||
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
|
||||
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
|
||||
C_MUX_PIPELINE_STAGES : INTEGER;
|
||||
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
|
||||
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
|
||||
C_USE_SOFTECC : INTEGER;
|
||||
C_USE_ECC : INTEGER;
|
||||
C_EN_ECC_PIPE : INTEGER;
|
||||
C_READ_LATENCY_A : INTEGER;
|
||||
C_READ_LATENCY_B : INTEGER;
|
||||
C_HAS_INJECTERR : INTEGER;
|
||||
C_SIM_COLLISION_CHECK : STRING;
|
||||
C_COMMON_CLK : INTEGER;
|
||||
C_DISABLE_WARN_BHV_COLL : INTEGER;
|
||||
C_EN_SLEEP_PIN : INTEGER;
|
||||
C_USE_URAM : INTEGER;
|
||||
C_EN_RDADDRA_CHG : INTEGER;
|
||||
C_EN_RDADDRB_CHG : INTEGER;
|
||||
C_EN_DEEPSLEEP_PIN : INTEGER;
|
||||
C_EN_SHUTDOWN_PIN : INTEGER;
|
||||
C_EN_SAFETY_CKT : INTEGER;
|
||||
C_DISABLE_WARN_BHV_RANGE : INTEGER;
|
||||
C_COUNT_36K_BRAM : STRING;
|
||||
C_COUNT_18K_BRAM : STRING;
|
||||
C_EST_POWER_SUMMARY : STRING
|
||||
);
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
rsta : IN STD_LOGIC;
|
||||
ena : IN STD_LOGIC;
|
||||
regcea : IN STD_LOGIC;
|
||||
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
clkb : IN STD_LOGIC;
|
||||
rstb : IN STD_LOGIC;
|
||||
enb : IN STD_LOGIC;
|
||||
regceb : IN STD_LOGIC;
|
||||
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
injectsbiterr : IN STD_LOGIC;
|
||||
injectdbiterr : IN STD_LOGIC;
|
||||
eccpipece : IN STD_LOGIC;
|
||||
sbiterr : OUT STD_LOGIC;
|
||||
dbiterr : OUT STD_LOGIC;
|
||||
rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
sleep : IN STD_LOGIC;
|
||||
deepsleep : IN STD_LOGIC;
|
||||
shutdown : IN STD_LOGIC;
|
||||
rsta_busy : OUT STD_LOGIC;
|
||||
rstb_busy : OUT STD_LOGIC;
|
||||
s_aclk : IN STD_LOGIC;
|
||||
s_aresetn : IN STD_LOGIC;
|
||||
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_wlast : IN STD_LOGIC;
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rlast : OUT STD_LOGIC;
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
s_axi_injectsbiterr : IN STD_LOGIC;
|
||||
s_axi_injectdbiterr : IN STD_LOGIC;
|
||||
s_axi_sbiterr : OUT STD_LOGIC;
|
||||
s_axi_dbiterr : OUT STD_LOGIC;
|
||||
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT blk_mem_gen_v8_4_4;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF infinity_info_180_24_arch: ARCHITECTURE IS "blk_mem_gen_v8_4_4,Vivado 2019.2";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF infinity_info_180_24_arch : ARCHITECTURE IS "infinity_info_180_24,blk_mem_gen_v8_4_4,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF infinity_info_180_24_arch: ARCHITECTURE IS "infinity_info_180_24,blk_mem_gen_v8_4_4,{x_ipProduct=Vivado 2019.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.4,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAM" &
|
||||
"E=infinity_info_180_24.mif,C_INIT_FILE=infinity_info_180_24.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=4320,C_READ_DEPTH_A=4320,C_ADDRA_WIDTH=13,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH" &
|
||||
"_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=4320,C_READ_DEPTH_B=4320,C_ADDRB_WIDTH=13,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_READ_LATENCY_A=1,C_READ_LATENCY_B=1,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CH" &
|
||||
"G=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.374319 mW}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF clka: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
|
||||
BEGIN
|
||||
U0 : blk_mem_gen_v8_4_4
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "artix7",
|
||||
C_XDEVICEFAMILY => "artix7",
|
||||
C_ELABORATION_DIR => "./",
|
||||
C_INTERFACE_TYPE => 0,
|
||||
C_AXI_TYPE => 1,
|
||||
C_AXI_SLAVE_TYPE => 0,
|
||||
C_USE_BRAM_BLOCK => 0,
|
||||
C_ENABLE_32BIT_ADDRESS => 0,
|
||||
C_CTRL_ECC_ALGO => "NONE",
|
||||
C_HAS_AXI_ID => 0,
|
||||
C_AXI_ID_WIDTH => 4,
|
||||
C_MEM_TYPE => 3,
|
||||
C_BYTE_SIZE => 9,
|
||||
C_ALGORITHM => 1,
|
||||
C_PRIM_TYPE => 1,
|
||||
C_LOAD_INIT_FILE => 1,
|
||||
C_INIT_FILE_NAME => "infinity_info_180_24.mif",
|
||||
C_INIT_FILE => "infinity_info_180_24.mem",
|
||||
C_USE_DEFAULT_DATA => 0,
|
||||
C_DEFAULT_DATA => "0",
|
||||
C_HAS_RSTA => 0,
|
||||
C_RST_PRIORITY_A => "CE",
|
||||
C_RSTRAM_A => 0,
|
||||
C_INITA_VAL => "0",
|
||||
C_HAS_ENA => 1,
|
||||
C_HAS_REGCEA => 0,
|
||||
C_USE_BYTE_WEA => 0,
|
||||
C_WEA_WIDTH => 1,
|
||||
C_WRITE_MODE_A => "WRITE_FIRST",
|
||||
C_WRITE_WIDTH_A => 12,
|
||||
C_READ_WIDTH_A => 12,
|
||||
C_WRITE_DEPTH_A => 4320,
|
||||
C_READ_DEPTH_A => 4320,
|
||||
C_ADDRA_WIDTH => 13,
|
||||
C_HAS_RSTB => 0,
|
||||
C_RST_PRIORITY_B => "CE",
|
||||
C_RSTRAM_B => 0,
|
||||
C_INITB_VAL => "0",
|
||||
C_HAS_ENB => 0,
|
||||
C_HAS_REGCEB => 0,
|
||||
C_USE_BYTE_WEB => 0,
|
||||
C_WEB_WIDTH => 1,
|
||||
C_WRITE_MODE_B => "WRITE_FIRST",
|
||||
C_WRITE_WIDTH_B => 12,
|
||||
C_READ_WIDTH_B => 12,
|
||||
C_WRITE_DEPTH_B => 4320,
|
||||
C_READ_DEPTH_B => 4320,
|
||||
C_ADDRB_WIDTH => 13,
|
||||
C_HAS_MEM_OUTPUT_REGS_A => 1,
|
||||
C_HAS_MEM_OUTPUT_REGS_B => 0,
|
||||
C_HAS_MUX_OUTPUT_REGS_A => 0,
|
||||
C_HAS_MUX_OUTPUT_REGS_B => 0,
|
||||
C_MUX_PIPELINE_STAGES => 0,
|
||||
C_HAS_SOFTECC_INPUT_REGS_A => 0,
|
||||
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
|
||||
C_USE_SOFTECC => 0,
|
||||
C_USE_ECC => 0,
|
||||
C_EN_ECC_PIPE => 0,
|
||||
C_READ_LATENCY_A => 1,
|
||||
C_READ_LATENCY_B => 1,
|
||||
C_HAS_INJECTERR => 0,
|
||||
C_SIM_COLLISION_CHECK => "ALL",
|
||||
C_COMMON_CLK => 0,
|
||||
C_DISABLE_WARN_BHV_COLL => 0,
|
||||
C_EN_SLEEP_PIN => 0,
|
||||
C_USE_URAM => 0,
|
||||
C_EN_RDADDRA_CHG => 0,
|
||||
C_EN_RDADDRB_CHG => 0,
|
||||
C_EN_DEEPSLEEP_PIN => 0,
|
||||
C_EN_SHUTDOWN_PIN => 0,
|
||||
C_EN_SAFETY_CKT => 0,
|
||||
C_DISABLE_WARN_BHV_RANGE => 0,
|
||||
C_COUNT_36K_BRAM => "2",
|
||||
C_COUNT_18K_BRAM => "1",
|
||||
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.374319 mW"
|
||||
)
|
||||
PORT MAP (
|
||||
clka => clka,
|
||||
rsta => '0',
|
||||
ena => ena,
|
||||
regcea => '0',
|
||||
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
addra => addra,
|
||||
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
|
||||
douta => douta,
|
||||
clkb => '0',
|
||||
rstb => '0',
|
||||
enb => '0',
|
||||
regceb => '0',
|
||||
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 13)),
|
||||
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
|
||||
injectsbiterr => '0',
|
||||
injectdbiterr => '0',
|
||||
eccpipece => '0',
|
||||
sleep => '0',
|
||||
deepsleep => '0',
|
||||
shutdown => '0',
|
||||
s_aclk => '0',
|
||||
s_aresetn => '0',
|
||||
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
s_axi_awvalid => '0',
|
||||
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
|
||||
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_wlast => '0',
|
||||
s_axi_wvalid => '0',
|
||||
s_axi_bready => '0',
|
||||
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
s_axi_arvalid => '0',
|
||||
s_axi_rready => '0',
|
||||
s_axi_injectsbiterr => '0',
|
||||
s_axi_injectdbiterr => '0'
|
||||
);
|
||||
END infinity_info_180_24_arch;
|
||||
Reference in New Issue
Block a user