01/02 some easy ai and some pic
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@@ -25,17 +25,19 @@ module clock(
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input wire item_faster,
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output reg clk_2Hz,
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output reg clk_4Hz,
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output reg clk_8Hz
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output reg clk_8Hz,
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output reg clk_10ms
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);
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reg [ 27: 0 ] cnt_2Hz, cnt_4Hz, cnt_8Hz;
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reg [ 27: 0 ] cnt_2Hz, cnt_4Hz, cnt_8Hz, cnt_10ms;
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reg [ 27: 0 ] ending_4Hz;
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initial begin
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cnt_4Hz <= 0;
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cnt_2Hz <= 0;
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cnt_8Hz <= 0;
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cnt_10ms <= 0;
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end
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@@ -95,4 +97,17 @@ always @( posedge clk_100MHz ) begin
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ending_4Hz <= 12500000;
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end
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end
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always @( posedge clk_100MHz ) begin
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cnt_10ms <= cnt_10ms + 1'b1;
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if ( cnt_10ms >= 500_000 ) begin
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clk_10ms <= 1;
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end
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else begin
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clk_10ms <= 0;
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end
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if ( cnt_10ms >= 1000_000 ) begin
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cnt_10ms <= 0;
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end
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end
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endmodule
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