01/02 some easy ai and some pic
This commit is contained in:
+222
-8
@@ -36,13 +36,13 @@
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<Option Name="WTVcsLaunchSim" Val="0"/>
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<Option Name="WTRivieraLaunchSim" Val="0"/>
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<Option Name="WTActivehdlLaunchSim" Val="0"/>
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<Option Name="WTXSimExportSim" Val="22"/>
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<Option Name="WTModelSimExportSim" Val="22"/>
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<Option Name="WTQuestaExportSim" Val="22"/>
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<Option Name="WTIesExportSim" Val="22"/>
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<Option Name="WTVcsExportSim" Val="22"/>
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<Option Name="WTRivieraExportSim" Val="22"/>
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<Option Name="WTActivehdlExportSim" Val="22"/>
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<Option Name="WTXSimExportSim" Val="26"/>
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<Option Name="WTModelSimExportSim" Val="26"/>
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<Option Name="WTQuestaExportSim" Val="26"/>
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<Option Name="WTIesExportSim" Val="26"/>
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<Option Name="WTVcsExportSim" Val="26"/>
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<Option Name="WTRivieraExportSim" Val="26"/>
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<Option Name="WTActivehdlExportSim" Val="26"/>
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
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<Option Name="XSimRadix" Val="hex"/>
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<Option Name="XSimTimeUnit" Val="ns"/>
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@@ -104,6 +104,13 @@
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/Random.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/SegAndLed.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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@@ -160,6 +167,13 @@
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/game_information_display.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/game_logic_classic.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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@@ -392,6 +406,30 @@
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/pic/classic_info_180_46.coe">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/pic/infinity_info_180_24.coe">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/pic/timing_15_15.coe">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/pic/redflag_20_20.coe">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="Top"/>
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@@ -435,7 +473,7 @@
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<File Path="$PSRCDIR/utils_1/imports/impl_1/Top_routed.dcp">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PRUNDIR/impl_1/Top_routed.dcp"/>
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<Attr Name="ImportTime" Val="1609563747"/>
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<Attr Name="ImportTime" Val="1609588391"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedInSteps" Val="impl_1"/>
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@@ -664,6 +702,58 @@
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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<FileSet Name="classic_info_180_46" Type="BlockSrcs" RelSrcDir="$PSRCDIR/classic_info_180_46">
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<File Path="$PSRCDIR/sources_1/ip/classic_info_180_46/classic_info_180_46.xci">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="TopModule" Val="classic_info_180_46"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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<FileSet Name="infinity_info_180_24" Type="BlockSrcs" RelSrcDir="$PSRCDIR/infinity_info_180_24">
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<File Path="$PSRCDIR/sources_1/ip/infinity_info_180_24/infinity_info_180_24.xci">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="TopModule" Val="infinity_info_180_24"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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<FileSet Name="timing_15_15" Type="BlockSrcs" RelSrcDir="$PSRCDIR/timing_15_15">
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<File Path="$PSRCDIR/sources_1/ip/timing_15_15/timing_15_15.xci">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="TopModule" Val="timing_15_15"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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<FileSet Name="redflag_20_20" Type="BlockSrcs" RelSrcDir="$PSRCDIR/redflag_20_20">
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<File Path="$PSRCDIR/sources_1/ip/redflag_20_20/redflag_20_20.xci">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="TopModule" Val="redflag_20_20"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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</FileSets>
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<Simulators>
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<Simulator Name="XSim">
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@@ -854,6 +944,54 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="classic_info_180_46_synth_1" Type="Ft3:Synth" SrcSet="classic_info_180_46" Part="xc7a100tcsg324-1" ConstrsSet="classic_info_180_46" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/classic_info_180_46_synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
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<Desc>Vivado Synthesis Defaults</Desc>
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</StratHandle>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="infinity_info_180_24_synth_1" Type="Ft3:Synth" SrcSet="infinity_info_180_24" Part="xc7a100tcsg324-1" ConstrsSet="infinity_info_180_24" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/infinity_info_180_24_synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
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<Desc>Vivado Synthesis Defaults</Desc>
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</StratHandle>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="timing_15_15_synth_1" Type="Ft3:Synth" SrcSet="timing_15_15" Part="xc7a100tcsg324-1" ConstrsSet="timing_15_15" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/timing_15_15_synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
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<Desc>Vivado Synthesis Defaults</Desc>
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</StratHandle>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="redflag_20_20_synth_1" Type="Ft3:Synth" SrcSet="redflag_20_20" Part="xc7a100tcsg324-1" ConstrsSet="redflag_20_20" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/redflag_20_20_synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
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<Desc>Vivado Synthesis Defaults</Desc>
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</StratHandle>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/impl_1/Top_routed.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
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@@ -1144,6 +1282,82 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="classic_info_180_46_impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="classic_info_180_46" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="classic_info_180_46_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
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<Desc>Default settings for Implementation.</Desc>
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</StratHandle>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design" EnableStepBool="1"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="infinity_info_180_24_impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="infinity_info_180_24" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="infinity_info_180_24_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
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<Desc>Default settings for Implementation.</Desc>
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</StratHandle>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design" EnableStepBool="1"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="timing_15_15_impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="timing_15_15" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="timing_15_15_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
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<Desc>Default settings for Implementation.</Desc>
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</StratHandle>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design" EnableStepBool="1"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="redflag_20_20_impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="redflag_20_20" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="redflag_20_20_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
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<Desc>Default settings for Implementation.</Desc>
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</StratHandle>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design" EnableStepBool="1"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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</Runs>
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<Board/>
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<DashboardSummary Version="1" Minor="0">
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Block a user