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ChenXuzheng
2020-12-30 08:37:52 +08:00
parent 69923e24c1
commit 861fb88001
205 changed files with 2962996 additions and 71 deletions
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TankGame.srcs/sources_1/imports/ISE/Project/ScoreBoard/DisplaySync.vf
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 14.7
// \ \ Application : sch2hdl
// / / Filename : DisplaySync.vf
// /___/ /\ Timestamp : 10/28/2020 20:29:09
// \ \ / \
// \___\/\___\
//
//Command: sch2hdl -intstyle ise -family artix7 -verilog E:/ISE/Project/ScoreBoard/DisplaySync.vf -w E:/ISE/Project/ScoreBoard/DisplaySync.sch
//Design Name: DisplaySync
//Device: artix7
//Purpose:
// This verilog netlist is translated from an ECS schematic.It can be
// synthesized and simulated, but it should not be modified.
//
`timescale 100 ps / 10 ps
module INV4_HXILINX_DisplaySync (O0, O1, O2, O3, I0, I1, I2, I3);
output O0;
output O1;
output O2;
output O3;
input I0;
input I1;
input I2;
input I3;
assign O0 = !I0;
assign O1 = !I1;
assign O2 = !I2;
assign O3 = !I3;
endmodule
`timescale 100 ps / 10 ps
module D2_4E_HXILINX_DisplaySync (D0, D1, D2, D3, A0, A1, E);
output D0;
output D1;
output D2;
output D3;
input A0;
input A1;
input E;
reg D0;
reg D1;
reg D2;
reg D3;
always @ (A0 or A1 or E)
begin
if(!E)
{D3, D2, D1, D0} <= 4'b0000;
else
begin
case({A1,A0})
2'b00 : {D3,D2,D1,D0} <= 4'b0001;
2'b01 : {D3,D2,D1,D0} <= 4'b0010;
2'b10 : {D3,D2,D1,D0} <= 4'b0100;
2'b11 : {D3,D2,D1,D0} <= 4'b1000;
endcase
end
end
endmodule
`timescale 1ns / 1ps
module DisplaySync(Hexs,
LES,
point,
Scan,
AN,
HEX,
LE,
p);
input [15:0] Hexs;
input [3:0] LES;
input [3:0] point;
input [1:0] Scan;
output [3:0] AN;
output [3:0] HEX;
output LE;
output p;
wire XLXN_22;
wire XLXN_23;
wire XLXN_24;
wire XLXN_25;
wire XLXN_26;
Mux4to14b XLXI_1 (.I0(Hexs[3:0]),
.I1(Hexs[7:4]),
.I2(Hexs[11:8]),
.I3(Hexs[15:12]),
.S(Scan[1:0]),
.O(HEX[3:0]));
MUX4to1 XLXI_3 (.I0(point[0]),
.I1(point[1]),
.I2(point[2]),
.I3(point[3]),
.S(Scan[1:0]),
.O(p));
MUX4to1 XLXI_4 (.I0(LES[0]),
.I1(LES[1]),
.I2(LES[2]),
.I3(LES[3]),
.S(Scan[1:0]),
.O(LE));
(* HU_SET = "XLXI_5_0" *)
D2_4E_HXILINX_DisplaySync XLXI_5 (.A0(Scan[0]),
.A1(Scan[1]),
.E(XLXN_22),
.D0(XLXN_26),
.D1(XLXN_25),
.D2(XLXN_24),
.D3(XLXN_23));
VCC XLXI_6 (.P(XLXN_22));
(* HU_SET = "XLXI_7_1" *)
INV4_HXILINX_DisplaySync XLXI_7 (.I0(XLXN_23),
.I1(XLXN_24),
.I2(XLXN_25),
.I3(XLXN_26),
.O0(AN[3]),
.O1(AN[2]),
.O2(AN[1]),
.O3(AN[0]));
endmodule
TankGame.srcs/sources_1/imports/ISE/Project/ScoreBoard/MUX4to1.vf
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 14.7
// \ \ Application : sch2hdl
// / / Filename : MUX4to1.vf
// /___/ /\ Timestamp : 10/27/2020 16:20:57
// \ \ / \
// \___\/\___\
//
//Command: sch2hdl -intstyle ise -family artix7 -verilog E:/ISE/Project/MUX4to1/MUX4to1.vf -w E:/ISE/Project/MUX4to1/MUX4to1.sch
//Design Name: MUX4to1
//Device: artix7
//Purpose:
// This verilog netlist is translated from an ECS schematic.It can be
// synthesized and simulated, but it should not be modified.
//
`timescale 1ns / 1ps
module MUX4to1(I0,
I1,
I2,
I3,
S,
O);
input I0;
input I1;
input I2;
input I3;
input [1:0] S;
output O;
wire XLXN_6;
wire XLXN_7;
wire XLXN_15;
wire XLXN_16;
wire XLXN_17;
wire XLXN_19;
wire XLXN_37;
wire XLXN_38;
wire XLXN_39;
wire XLXN_40;
AND2 XLXI_1 (.I0(XLXN_6),
.I1(XLXN_7),
.O(XLXN_15));
AND2 XLXI_2 (.I0(S[0]),
.I1(XLXN_7),
.O(XLXN_16));
AND2 XLXI_3 (.I0(S[1]),
.I1(XLXN_6),
.O(XLXN_17));
AND2 XLXI_4 (.I0(S[1]),
.I1(S[0]),
.O(XLXN_19));
AND2 XLXI_5 (.I0(I0),
.I1(XLXN_15),
.O(XLXN_37));
AND2 XLXI_6 (.I0(I1),
.I1(XLXN_16),
.O(XLXN_38));
AND2 XLXI_7 (.I0(I2),
.I1(XLXN_17),
.O(XLXN_39));
AND2 XLXI_8 (.I0(I3),
.I1(XLXN_19),
.O(XLXN_40));
INV XLXI_9 (.I(S[1]),
.O(XLXN_7));
INV XLXI_10 (.I(S[0]),
.O(XLXN_6));
OR4 XLXI_11 (.I0(XLXN_40),
.I1(XLXN_39),
.I2(XLXN_38),
.I3(XLXN_37),
.O(O));
endmodule
TankGame.srcs/sources_1/imports/ISE/Project/ScoreBoard/Mux4to14b.vf
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 14.7
// \ \ Application : sch2hdl
// / / Filename : Mux4to14b.vf
// /___/ /\ Timestamp : 10/25/2020 22:26:59
// \ \ / \
// \___\/\___\
//
//Command: sch2hdl -intstyle ise -family artix7 -verilog E:/ISE/Project/Mux4to1b4_sch/Mux4to14b.vf -w E:/ISE/Project/Mux4to1b4_sch/Mux4to14b.sch
//Design Name: Mux4to14b
//Device: artix7
//Purpose:
// This verilog netlist is translated from an ECS schematic.It can be
// synthesized and simulated, but it should not be modified.
//
`timescale 1ns / 1ps
module Mux4to14b(I0,
I1,
I2,
I3,
S,
O);
input [3:0] I0;
input [3:0] I1;
input [3:0] I2;
input [3:0] I3;
input [1:0] S;
output [3:0] O;
wire XLXN_1;
wire XLXN_2;
wire XLXN_3;
wire XLXN_4;
wire XLXN_5;
wire XLXN_7;
wire XLXN_8;
wire XLXN_9;
wire XLXN_10;
wire XLXN_11;
wire XLXN_12;
wire XLXN_13;
wire XLXN_14;
wire XLXN_15;
wire XLXN_16;
wire XLXN_17;
wire XLXN_18;
wire XLXN_20;
wire XLXN_28;
wire XLXN_32;
wire XLXN_37;
wire XLXN_41;
AND2 XLXI_1 (.I0(I0[0]),
.I1(XLXN_28),
.O(XLXN_1));
AND2 XLXI_2 (.I0(I1[0]),
.I1(XLXN_32),
.O(XLXN_2));
AND2 XLXI_3 (.I0(I2[0]),
.I1(XLXN_37),
.O(XLXN_3));
AND2 XLXI_4 (.I0(I3[0]),
.I1(XLXN_41),
.O(XLXN_4));
AND2 XLXI_5 (.I0(I0[1]),
.I1(XLXN_28),
.O(XLXN_5));
AND2 XLXI_6 (.I0(I1[1]),
.I1(XLXN_32),
.O(XLXN_7));
AND2 XLXI_7 (.I0(I2[1]),
.I1(XLXN_37),
.O(XLXN_8));
AND2 XLXI_8 (.I0(I3[1]),
.I1(XLXN_41),
.O(XLXN_9));
AND2 XLXI_9 (.I0(I0[2]),
.I1(XLXN_28),
.O(XLXN_10));
AND2 XLXI_10 (.I0(I1[2]),
.I1(XLXN_32),
.O(XLXN_11));
AND2 XLXI_11 (.I0(I2[2]),
.I1(XLXN_37),
.O(XLXN_12));
AND2 XLXI_12 (.I0(I3[2]),
.I1(XLXN_41),
.O(XLXN_13));
AND2 XLXI_13 (.I0(I0[3]),
.I1(XLXN_28),
.O(XLXN_14));
AND2 XLXI_14 (.I0(I1[3]),
.I1(XLXN_32),
.O(XLXN_15));
AND2 XLXI_15 (.I0(I2[3]),
.I1(XLXN_37),
.O(XLXN_16));
AND2 XLXI_16 (.I0(I3[3]),
.I1(XLXN_41),
.O(XLXN_17));
OR4 XLXI_17 (.I0(XLXN_4),
.I1(XLXN_3),
.I2(XLXN_2),
.I3(XLXN_1),
.O(O[0]));
OR4 XLXI_18 (.I0(XLXN_9),
.I1(XLXN_8),
.I2(XLXN_7),
.I3(XLXN_5),
.O(O[1]));
OR4 XLXI_19 (.I0(XLXN_13),
.I1(XLXN_12),
.I2(XLXN_11),
.I3(XLXN_10),
.O(O[2]));
OR4 XLXI_20 (.I0(XLXN_17),
.I1(XLXN_16),
.I2(XLXN_15),
.I3(XLXN_14),
.O(O[3]));
AND2 XLXI_21 (.I0(XLXN_20),
.I1(XLXN_18),
.O(XLXN_28));
AND2 XLXI_22 (.I0(S[0]),
.I1(XLXN_18),
.O(XLXN_32));
AND2 XLXI_23 (.I0(S[1]),
.I1(XLXN_20),
.O(XLXN_37));
AND2 XLXI_24 (.I0(S[1]),
.I1(S[0]),
.O(XLXN_41));
INV XLXI_25 (.I(S[1]),
.O(XLXN_18));
INV XLXI_26 (.I(S[0]),
.O(XLXN_20));
endmodule
TankGame.srcs/sources_1/imports/ISE/Project/ScoreBoard/MyMC14495.vf
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 14.7
// \ \ Application : sch2hdl
// / / Filename : MyMC14495.vf
// /___/ /\ Timestamp : 10/20/2020 18:52:07
// \ \ / \
// \___\/\___\
//
//Command: sch2hdl -intstyle ise -family kintex7 -verilog E:/ISE/Project/MyMC14495/MyMC14495.vf -w E:/ISE/Project/MyMC14495/MyMC14495.sch
//Design Name: MyMC14495
//Device: kintex7
//Purpose:
// This verilog netlist is translated from an ECS schematic.It can be
// synthesized and simulated, but it should not be modified.
//
`timescale 1ns / 1ps
module MyMC14495(D0,
D1,
D2,
D3,
LE,
point,
a,
b,
c,
d,
e,
f,
g,
p);
input D0;
input D1;
input D2;
input D3;
input LE;
input point;
output a;
output b;
output c;
output d;
output e;
output f;
output g;
output p;
wire ND0;
wire ND1;
wire ND2;
wire ND3;
wire XLXN_41;
wire XLXN_42;
wire XLXN_43;
wire XLXN_44;
wire XLXN_45;
wire XLXN_46;
wire XLXN_48;
wire XLXN_49;
wire XLXN_50;
wire XLXN_51;
wire XLXN_52;
wire XLXN_54;
wire XLXN_55;
wire XLXN_56;
wire XLXN_57;
wire XLXN_59;
wire XLXN_60;
wire XLXN_61;
wire XLXN_62;
wire XLXN_63;
wire XLXN_64;
wire XLXN_69;
wire XLXN_70;
wire XLXN_72;
wire XLXN_73;
wire XLXN_74;
wire XLXN_75;
wire XLXN_78;
AND4 AND_0 (.I0(ND0),
.I1(ND1),
.I2(D2),
.I3(D3),
.O(XLXN_41));
AND4 AND_1 (.I0(D0),
.I1(D1),
.I2(D2),
.I3(ND3),
.O(XLXN_42));
AND3 AND_2 (.I0(ND1),
.I1(ND2),
.I2(ND3),
.O(XLXN_43));
AND3 AND_3 (.I0(D0),
.I1(D1),
.I2(ND3),
.O(XLXN_44));
AND3 AND_4 (.I0(D1),
.I1(ND2),
.I2(ND3),
.O(XLXN_45));
AND3 AND_5 (.I0(D0),
.I1(ND2),
.I2(ND3),
.O(XLXN_46));
AND3 AND_6 (.I0(D0),
.I1(ND1),
.I2(ND2),
.O(XLXN_48));
AND3 AND_7 (.I0(ND1),
.I1(D2),
.I2(ND3),
.O(XLXN_49));
AND2 AND8 (.I0(D0),
.I1(ND3),
.O(XLXN_50));
AND4 AND9 (.I0(ND0),
.I1(D1),
.I2(ND2),
.I3(D3),
.O(XLXN_51));
AND3 AND10 (.I0(D0),
.I1(D1),
.I2(D2),
.O(XLXN_52));
AND3 AND11 (.I0(D1),
.I1(D2),
.I2(D3),
.O(XLXN_56));
AND4 AND12 (.I0(ND0),
.I1(D1),
.I2(ND2),
.I3(ND3),
.O(XLXN_57));
AND3 AND13 (.I0(D0),
.I1(D1),
.I2(D3),
.O(XLXN_59));
AND3 AND14 (.I0(ND0),
.I1(D2),
.I2(D3),
.O(XLXN_60));
AND3 AND15 (.I0(ND0),
.I1(D1),
.I2(D2),
.O(XLXN_61));
AND4 AND16 (.I0(D0),
.I1(ND1),
.I2(D2),
.I3(ND3),
.O(XLXN_62));
AND4 AND17 (.I0(D0),
.I1(D1),
.I2(ND2),
.I3(D3),
.O(XLXN_63));
AND4 AND18 (.I0(D0),
.I1(ND1),
.I2(D2),
.I3(D3),
.O(XLXN_64));
AND4 AND19 (.I0(ND0),
.I1(ND1),
.I2(D2),
.I3(ND3),
.O(XLXN_54));
AND4 AND20 (.I0(D0),
.I1(ND2),
.I2(ND1),
.I3(ND3),
.O(XLXN_55));
INV INV0 (.I(D0),
.O(ND0));
INV INV1 (.I(D1),
.O(ND1));
INV INV2 (.I(D2),
.O(ND2));
INV INV3 (.I(D3),
.O(ND3));
OR3 XLXI_1 (.I0(XLXN_41),
.I1(XLXN_42),
.I2(XLXN_43),
.O(XLXN_69));
OR3 XLXI_2 (.I0(XLXN_48),
.I1(XLXN_49),
.I2(XLXN_50),
.O(XLXN_72));
OR3 XLXI_3 (.I0(XLXN_56),
.I1(XLXN_57),
.I2(XLXN_60),
.O(XLXN_74));
OR4 XLXI_4 (.I0(XLXN_44),
.I1(XLXN_45),
.I2(XLXN_46),
.I3(XLXN_64),
.O(XLXN_70));
OR4 XLXI_5 (.I0(XLXN_51),
.I1(XLXN_52),
.I2(XLXN_54),
.I3(XLXN_55),
.O(XLXN_73));
OR4 XLXI_6 (.I0(XLXN_59),
.I1(XLXN_60),
.I2(XLXN_61),
.I3(XLXN_62),
.O(XLXN_75));
OR4 XLXI_7 (.I0(XLXN_63),
.I1(XLXN_64),
.I2(XLXN_54),
.I3(XLXN_55),
.O(XLXN_78));
OR2 XLXI_8 (.I0(LE),
.I1(XLXN_69),
.O(g));
OR2 XLXI_9 (.I0(LE),
.I1(XLXN_70),
.O(f));
OR2 XLXI_10 (.I0(LE),
.I1(XLXN_72),
.O(e));
OR2 XLXI_11 (.I0(LE),
.I1(XLXN_73),
.O(d));
OR2 XLXI_12 (.I0(LE),
.I1(XLXN_74),
.O(c));
OR2 XLXI_13 (.I0(LE),
.I1(XLXN_75),
.O(b));
OR2 XLXI_14 (.I0(LE),
.I1(XLXN_78),
.O(a));
INV XLXI_15 (.I(point),
.O(p));
endmodule
TankGame.srcs/sources_1/imports/linux/Compressed/FPGA-TankGame/TankGame.srcs/pic/background_320_240.coe
+76802
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TankGame.srcs/sources_1/imports/linux/Compressed/TankGame/pic/coe/background_320_240.coe
+76802
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TankGame.srcs/sources_1/imports/pic/bullet_down.coe
+52
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@@ -0,0 +1,52 @@
memory_initialization_radix=2;
memory_initialization_vector=111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
010001111001,
110011011111,
001001111001,
111111111111,
111111111111,
000001001010,
100011101111,
011111011111,
111111111111,
111111111111,
000001011011,
100011111111,
011011011111,
111111111111,
111111111111,
000001001011,
100011111111,
011011011111,
111111111111,
111111111111,
000001001011,
100011111111,
011011011111,
111111111111,
111111111111,
001101101000,
100011011110,
001101100111,
111111111111,
111111111111,
001101101000,
011111011110,
001101101000,
111111111111,
111111111111,
010001100111,
011111011111,
000100100011,
111111111111,
111111111111,
111111111111,
010001010110,
111111111111,
111111111111,
;
TankGame.srcs/sources_1/imports/pic/bullet_left.coe
+52
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@@ -0,0 +1,52 @@
memory_initialization_radix=2;
memory_initialization_vector=111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
010001100111,
001101101000,
001101101000,
000001001011,
000001001011,
000001011011,
000001001010,
010001111001,
111111111111,
010001010110,
011111011111,
011111011110,
100011011110,
100011111111,
100011111111,
100011111111,
100011101111,
110011011111,
111111111111,
111111111111,
000100100011,
001101101000,
001101100111,
011011011111,
011011011111,
011011011111,
011111011111,
001001111001,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
;
TankGame.srcs/sources_1/imports/pic/bullet_right.coe
+52
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@@ -0,0 +1,52 @@
memory_initialization_radix=2;
memory_initialization_vector=111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
001001111001,
011111011111,
011011011111,
011011011111,
011011011111,
001101100111,
001101101000,
000100100011,
111111111111,
111111111111,
110011011111,
100011101111,
100011111111,
100011111111,
100011111111,
100011011110,
011111011110,
011111011111,
010001010110,
111111111111,
010001111001,
000001001010,
000001011011,
000001001011,
000001001011,
001101101000,
001101101000,
010001100111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
;
TankGame.srcs/sources_1/imports/pic/bullet_up.coe
+52
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@@ -0,0 +1,52 @@
memory_initialization_radix=2;
memory_initialization_vector=111111111111,
111111111111,
010001010110,
111111111111,
111111111111,
111111111111,
000100100011,
011111011111,
010001100111,
111111111111,
111111111111,
001101101000,
011111011110,
001101101000,
111111111111,
111111111111,
001101100111,
100011011110,
001101101000,
111111111111,
111111111111,
011011011111,
100011111111,
000001001011,
111111111111,
111111111111,
011011011111,
100011111111,
000001001011,
111111111111,
111111111111,
011011011111,
100011111111,
000001011011,
111111111111,
111111111111,
011111011111,
100011101111,
000001001010,
111111111111,
111111111111,
001001111001,
110011011111,
010001111001,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
111111111111,
;
TankGame.srcs/sources_1/imports/pic/down1.coe
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