add all source and report

README.md

@@ -1,9 +1,729 @@
-# FPGA-TankGame
 
-sz @ 12.28
 
-距离v1.0还有的bug和未完成的：
+## 一、项目背景介绍
+
+《坦克大战》（Battle City）是1985年日本南梦宫Namco游戏公司在任天堂FC平台上，推出的一款多方位平面射击游戏。游戏以坦克战斗及保卫基地为主题，属于策略型联机类。同时也是FC平台上少有的内建关卡编辑器的几个游戏之一，玩家可自己创建独特的关卡，并通过获取一些道具使坦克和基地得到强化。本游戏从此获取灵感，并基于此进行改编，是一款规则简单，内容趣味性高，可玩性强的游戏。
+
+
+
+## 二、游戏说明
+
+#### 1. 游戏基本规则
+
+1. 该游戏为双人游戏，两位玩家同属一方，分别控制一辆坦克，根据模式的不同，开展竞争或是合作，摧毁敌方坦克。
+2. 敌方坦克共有四辆，均由AI控制。
+
+3. 坦克可以在地图范围内自由移动，除非其与其他坦克发生碰撞。
+
+4. 坦克可以向当前运动方向射击，但是同一时间一辆坦克在地图内**只允许存在一发子弹**。
+
+5. 当坦克与非本方子弹产生任何接触，坦克即视作被摧毁，并在2s后复活，同时该子弹也会被摧毁。
+6. 坦克重生后，将有1s的无敌时间。
+7. 场上将会随机产生道具：加速，冻结，时间增加，生命增加，无敌，我方坦克吃到之后将会有相应效果。
+
+
+
+本游戏共有两种模式：标准模式和无尽模式，下面我们分别对这两个模式的规则和胜利条件进行简要介绍。
+
+##### (a) 经典模式
+
+场上将会有两辆我方坦克和四辆敌方坦克，两位玩家将会展开对抗，**最先摧毁14辆敌方坦克的玩家获得胜利**。每辆我方坦克拥有预先设定好的生命值，若被敌方坦克击中，生命值减一，并会在2s后重新投入战斗。**若生命值降为0，则游戏结束**，另一方获得胜利。
+
+##### (b) 无尽模式
+
+场上将会有两辆我方坦克和四辆敌方坦克，两位玩家将展开合作，共同在预先设定好的时间内**摧毁尽可能多的坦克**。每辆我方坦克拥有3点生命值，每摧毁一辆敌方坦克，我方的剩余时间将会增加（不超过预设上限），**若剩余时间降为0，则游戏结束**。此模式无胜利方。
+
+
+
+
+
+#### 2. 游戏流程及操作说明
+
+1. 游戏开始前，在主界面中利用SW[0]选择模式，0为经典模式，1为无尽模式。
+2. 在经典模式下，可以设定血量的多少：SW[1]控制血量加减，0为减，1为加，再通过设定SW[2]完成加减操作。
+3. 在无尽模式下，可以设定时间的多少，每个时间图标代表1s，具体操作与血量设定相同。
+4. 按下BTNC开始游戏。
+5. 对于玩家A，键盘WSAD分别控制上下左右，J键开火。
+6. 对于玩家B，键盘上下左右分别控制上下左右，0键开火。
+7. 游戏结束时，按下BTNU可以回到主界面
+
+
+
+#### 3. 道具说明
+
+**加速**：加快全场运动物（敌我双方坦克和子弹）的运动速度，持续9s。
+
+**冻结**：使敌方坦克停止运动，持续4s。
+
+**时间增加**：将时间增加到预设的初始值。
+
+**生命增加**：增加拾取坦克的生命值1。
+
+**无敌**：坦克免疫所有敌方子弹攻击，持续8s。
+
+
+
+#### 4. 游戏界面说明
+
+**(a) 经典模式**
+
+经典模式的游戏界面如下图所示。屏幕上方显示了当前模式（经典）以及双方坦克所摧毁的敌方坦克数。每摧毁一个敌方坦克，我们就为ta的计分板上插上一面红旗。屏幕左右两侧分别显示的是玩家1和玩家2所剩生命值，每一颗红心代表一条命。
+
+**(b) 无尽模式**
+
+无尽模式的游戏界面如下图所示。屏幕上方显示了当前模式（无尽）以及当前所剩余时间，每一个计时器代表1s。屏幕左右两侧显示的也是玩家生命值。
+
+
+
+## 三、整体结构
+
+整个项目的框架如下所示，部分细节点由于空间原因没有全部画出
+
+![image-20210114205435987](pic/image-20210114205435987.png)
+
+#### 无尽模式的游戏逻辑：
+
+![infinity](pic/infinity.png)
+
+#### 经典模式的游戏逻辑
+
+![classic](pic/classic.png)
+
+
+
+
+
+## 四、模块介绍
+
+
+
+#### 1. VGA
+
+VGA作为一种标准的显示接口得到了广泛的应用，其信号类型为模拟类型，显示卡端的接口为 15 针母插座。
+常见的彩色显示器一般都是由CRT阴极射线管阴极射线管构成，其引出线共含 5 个信号：R、G、B三基色信号三基色信号、HS行同步信号行同步信号、VS场同步信号场同步信号。每一个像素的色彩由R红红 .G绿绿. B蓝蓝三基色构成。显示屏一般通过光栅扫描的方式扫描一幅屏幕图像上的各个点，形成整个图片。
+另外，VGA 时序控制模块是本设计的重要部分，最终的输出信号行、场同步信号必须严格按照VGA 时序标准产生相应的脉冲信号，如下图所示（以640*480@60HZ为例）。
+
+![vga_pic](pic/vga_pic.png)
+
+具体细节这里不再赘述。
+
+
+
+### 2. PS/2
+
+作为一款对战类游戏，良好的键盘输入体验肯定是必不可少的。我们采用的A7提供了基于usb接口、PS/2通信协议。PS/2 通信协议是一种双向同步串行通信协议。通信的两端通过 CLOCK时钟脚时钟脚同步，并通过DATA数据脚数据脚交换数据。
+
+如下是PS/2和主机间的通信时许图。数据在该时钟的下降沿进行读取，对于 PS/2 设备，一般来说从时钟脉冲的上升沿到一个数据转变的时间至少要有5us；数据变化到下降沿的时间至少要有 5us，并且不大于 25us。
+
+![ps2](pic/ps2.png)
+
+在查阅资料后我们得知，我们得知该协议需要6个引脚。
+
+![image-20210113194117915](pic/image-20210113194117915.png)
+
+但实际上PS/2协议只需要4个针脚，也就是GND、VCC、PS2_CLK和PS2_DATA，而该协议的时序图如下:
+
+![image-20210114190153221](pic/image-20210114190153221.png)
+
+FPGA或主机接收键盘发回的数据，通过键盘的编码规则判定键盘当前的操作，扫描码有两种不同的类型：通码(make code)和断码(break code)。当一个键被按下或持续按住时,键盘会将该键的通码发送给主机;而当一个键被释放时,键盘会将该键的断码发送给主机。值得注意的是，最后一位校验位有的芯片使用的是奇校验，而有的芯片使用的是偶校验，需要我们根据不同的板子进行调整。
+
+
+
+根据这个原理，我们很快写出来了一个简单的键盘接收驱动，在烧到板子内进行验证时却怎么页也读不出来，键盘输入完全无效，USB-HID旁边的busy灯长亮。
+
+在查阅大量资料后我恍然大悟：我使用的键盘为杜伽K320，在我的电脑中被识别为了多个键盘输入，如下图所示
+
+![image-20210114190141227](pic/image-20210114190141227.png)
+
+除了PS/2外还存在着其他虚拟出的键盘输入，因此无法传输数据。
+
+为此，我们在淘宝上购买了一块原生支持PS/2协议的键盘，之后使用该键盘可以很流畅的读出我们的键盘输入，调试工作终于有救了。
+
+
+
+### 3. ROM IP核模块
+
+坦克大战中的游戏界面贴图均为静态图片，通过选择将其放置在合适的位置上。为了让玩家获得更好的游戏体验，我们从网上搜集了大量的png格式的图片，通过软件首先转化为bmp，再通过自己写的python脚本转化为coe文件。利用这些图片我们创建了游戏开始界面、敌我坦克图片、子弹图片、道具图片以及游戏结束图片，一共有29张之多。
+
+具体使用的ip核如下所示：
+
+<img src="pic/ip_pic.png" alt="ip_pic" style="zoom:75%;" />
+
+其中只有background图片使用了最近邻插值法，通过采用320*240的图片可以减少1/4的BRAM空间占用，而敌我坦克、子弹等图片使用了PS进行处理，坦克、子弹等图片的边缘均为白色。因此当读到12'b1111_1111_1111时，将其转化为background的图像信息即可，以此实现图片的有效覆盖。
+
+
+
+#### 问题分析
+
+#### (1) 资源问题
+
+我们采用的是Nexys4 DDR-A7开发板，其具体参数如下图所示
+
+![image-20210113195559225](pic/image-20210113195559225.png)
+
+在使用vivado查看资源使用率后我们发现，该板子一共有135个fast block RAM，但是一张640*480，12bits的图片居然能使用105个block RAM，也就是说我们差不多连一张背景图都放不下，因此每个图片就只需要26.5个BRAM。
+
+而在实际中，我们则将该图片再转变为640*480的图片。假如图中的5个有坐标的点为320x240网格上的点，图中除了黄色点以为的其他点都是进行线性变换后640x480网格上的像素点，现在我们可以看到P(x,y)附近的四个点都没有正好落在格点上（我们先不管其他点），而他们四个距离黄色点最近，那么我在显示的时候，就把这四个点的颜色都显示成P(x,y)的颜色。
+
+这是一种很简单很基础的插值，但是对于我们这种小图片还是很管用的，大大减少了Block Memory资源的浪费。
+
+#### (2) 边缘白框处理
+
+在图片显示出来后，还是存在很多问题，最典型的问题就是图像边框白色和游戏背景图的黑色对比过于强烈，已经极大的影响了游戏体验，我的解决方案也比较简单，就是选择在处理图片的时候，将方块周围的不需要部分全部转变为0xffffff，在转换为coe文件后，只要读取到这种颜色编码oxfff，就选择不显示ROM中的数据，而是显示游戏背景，这样就避免了刚刚提到的问题。而实现起来也比较简单，如下图所示：
+
+~~~verilog
+.in2( ( player1_tank_data == 12'hfff ) ? 12'h000 : player1_tank_data ),
+.in3( ( player1_bullet_data == 12'hfff ) ? 12'h000 : player1_bullet_data ),
+.in4( ( player2_tank_data == 12'hfff ) ? 12'h000 : player2_tank_data ),
+.in5( ( player2_bullet_data == 12'hfff ) ? 12'h000 : player2_bullet_data ),
+~~~
+
+不过另一个问题是，因为初始的bmp图片是24位的，在转换为12位coe的时候就会使得很多颜色相近的颜色编码暴力变为同一种颜色编码，这个我最初在图片中埋藏的信息就不知道被转换成什么了。这个问题目前还没有得到很好的解决，总体而言并不是很影响整体游戏体验。
+
+#### (3) 同步显示问题
+
+我发现我显示的图片整体向右偏移了一个细条，我经过反复查阅资料和参考优秀实验报告，得出这是因为：我VGA模块输出的x，y坐标，在always语句中不会立刻计算这个xy对应的ROM地址值，他会等到下一个时钟周期到来的时候才会更新，ROM地址更新后，ROM的data也不会立刻更新，而是等到再过一个时钟周期，而VGA模块接受到Data后，也是要再过一个时钟周期才能更新，这就是为什么我的模块无法预期进行。
+
+解决方案实际上是这样的：首先把根据x、y计算地址值的always模块改成always@(∗)，这样他就会退化成时序逻辑，就不存在非阻塞赋值引发的延时问题了，但ROM模块必须是时序的，不过也有办法解决。我最开始给ROM的时钟是25MHz，与VGA同步，这样就一定会造成延迟，但我可以把ROM的时钟加速到VGA时钟的整数倍如100MHz，就可以在xy改变后、下一个vga时钟前拿到合适的输出。
+
+#### (4) COE文件与BMP文件互相转换
+
+为了更好、更方便的生成coe文件，我们通过python将bmp文件转化为需要指定宽度、高度的coe格式文件，同时我们也使用c语言将coe文件转化为bmp格式文件，**上述代码我们在附录中提供**，实验结果证明我们的代码效果非常好，达到我们预期的要求！
+
+
+
+### 4. 随机数生成模块
+
+在该游戏中，有两个部分需要用到随机数产生，一个是道具初始位置的选择，我们需要随机产生[0,619]和[0,459]处的随机数，同时敌方坦克控制上也要用到00-11的随机数控制方向，因此需要一个真题产生随机数的模块。
+
+在Verilog中，实际上是预制了随机数生成的方法，也就是使用：$random ，但是这个方法无法正常通过综合，百度后我发现该随机数实际上只能在testbench中进行使用。这就比较麻烦，我因此搜索了一些通过硬件实现随机数的方法，其中最常用的是LFSR法。
+
+![lfsr](pic/lfsr.png)
+
+通过奇怪的选择实现在[0,2^n-1]之间周期很长的周期序列，但在使用中一定要注意很重要的问题：时钟选择一定要合适！时钟不能过快，否则只能得到相同的随机数。
+
+整体代码请参见附录，我们使用了15位的随机数产生，经过测试已经能很好的满足我们的需要。而针对x，y的位置只需mod max_num即可，而敌方1,2,3,4号坦克控制只需要取随机数的[7:6],[5:4],[3:2],[1:0]位即可。
+
+~~~verilog
+        rand_num[ 0 ] <= rand_num[ 14 ];
+        rand_num[ 1 ] <= rand_num[ 0 ];
+        rand_num[ 2 ] <= rand_num[ 1 ];
+        rand_num[ 3 ] <= rand_num[ 2 ];
+        rand_num[ 4 ] <= rand_num[ 3 ] ^ rand_num[ 14 ];
+        rand_num[ 5 ] <= rand_num[ 4 ] ^ rand_num[ 14 ];
+        rand_num[ 6 ] <= rand_num[ 5 ] ^ rand_num[ 14 ];
+        rand_num[ 7 ] <= rand_num[ 6 ];
+        rand_num[ 9 ] <= rand_num[ 7 ];
+        rand_num[ 8 ] <= rand_num[ 8 ] ^ rand_num[ 14 ];
+        rand_num[ 10 ] <= rand_num[ 9 ];
+        rand_num[ 11 ] <= rand_num[ 10 ];
+        rand_num[ 12 ] <= rand_num[ 11 ] ^ rand_num[ 14 ];
+        rand_num[ 13 ] <= rand_num[ 12 ];
+        rand_num[ 14 ] <= rand_num[ 13 ];
+~~~
+
+
+
+### 5. 游戏整体界面
+
+整体而言我们的游戏界面分为三部分:
+
+1. 游戏开始界面
+
+   ![img](pic/2B5415CA01BF08735B530F066AFCA2DA.jpg)
+
+   
+
+2. 游戏进行中界面
+
+   ![img](pic/B50C4FA408CC7C83005330BE642C4F73.jpg)
+
+   
+
+3. 游戏结束界面
+
+   ![img](pic/C253B1E5BAB779624248D60D55C37741-1610548821772.jpg)
+
+   
+
+整体状态由顶层的game_mode模块控制,我们提供了经典模式和无尽模式也在此进行选择,因此我们一共需要四个状态:
+
+1. 初始开始界面状态
+2. 经典模式状态
+3. 无尽模式状态
+4. 游戏介绍状态
+
+而几种模式的选择和切换也在game_mode模块中进行,通过BTN按钮进行切换,而输出模块也根据当前的mode状态来输出，其中的enable和gameover信号可以自行查阅附录中的代码。
+
+
+
+### 6. 坦克控制
+
+一个完整的坦克控制需要三个模块协同：
+
+1. 坦克使能信号控制（game_mode）
+2. 坦克移动控制 （tank_move）
+3. 坦克显示 (tank_display)
+
+在使能信号控制中，我们根据当前的mode判断是否让坦克移动，通过产生enable信号影响下面两个模块。
+
+在坦克移动控制中，我们采用有限状态机设计思路，如下图所示
+
+~~~verilog
+always @( * ) begin: signals
+    counter_en = 1'b0;
+    init = 1'b0;
+    tank_dir_feedback[ 2 ] = 1;
+    case ( current_state )
+        INITIAL: begin
+            init = 1;
+        end
+        UP: begin
+            counter_en = 1;
+            tank_dir_feedback = 3'b000;
+        end
+        DOWN: begin
+            counter_en = 1;
+            tank_dir_feedback = 3'b001;
+        end
+        LEFT: begin
+            counter_en = 1;
+            tank_dir_feedback = 3'b010;
+        end
+        RIGHT: begin
+            counter_en = 1;
+            tank_dir_feedback = 3'b011;
+        end
+    endcase
+end
+
+~~~
+
+通过控制坦克的当前状态计算坦克的坐标，另一方面计算坦克的次态将其付给先态，这样写起来也更加方便具体。
+
+值得注意的是，我们根据当前是否有item_faster即加速道具来控制坦克的移动速度，如下所示
+
+~~~verilog
+wire [ 31: 0 ] counter_num = item_faster ? 1_500_000 : 2_100_000;
+~~~
+
+之后我们进行计数，如同所示：
+
+~~~verilog
+always @( posedge clk ) begin
+    if ( !reset_n ) begin
+        counter <= 0;
+        counter_move_en <= 0;
+    end
+    else if ( counter == counter_num ) begin
+        counter <= 0;
+        counter_move_en <= 1;
+    end
+    else if ( counter_en == 0 ) begin
+        counter <= 0;
+        counter_move_en <= 0;
+    end
+    else begin
+        counter <= counter + 1;
+        counter_move_en <= 0;
+    end
+end
+~~~
+
+当计数器达到设定的counter_num时候，我们就将坦克移动一个像素，这样就达到了控制坦克移动速度的目的。
+
+而在坦克展示模块中，似乎没有那么多值得注意的点，一个简单的位置判断和状态判断即可，但要看到我们由于无敌星的展示是在坦克原有的背景上额外添加一层黄色五角星，因此同时需要item_invincible信号进行输出判断。
+
+一方面，坦克四个方向如果使用一张图片配合纯计算，实现难度较高，因此我们采用四张图片展示坦克的四种方向；另一方面，敌方坦克和我方坦克的图片并不相同，因此总的来说我们一共需要2*4=8张图片进行展示，最后使用数据选择器根据坦克的方向、敌我坦克的区分来进行选择，最后配上是否有无敌星的数据进行或运算即可以得到最终的坦克展示数据，写出来也非常的难看。
+
+~~~verilog
+assign tankData = ( ( tank_en & ~tank_destroyed ) ? ( player_enermy ? outData_enermy : outData ) : 0 ) | ( ( ( tank_revive || item_invincible ) && tank_en ) ? outData_star : 0 );
+~~~
+
+实际上这样并不算好，因为一个坦克我们使用了8个图片的资源，但是由于图片较小（32*32），我也没有对此进行足够的改进。实际上应该将敌我坦克进行区分，分别使用不同的模块展示，这样可以只使用4个图片，六个图片总的来说可以节省大约5个BRAM。
+
+
+
+### 7. 敌方坦克移动控制
+
+实际上这部分是我们整体设计中最有难度的部分，也是我们调试时间最长的部分，前前后后一共花了一整天的时间在这个模块上，最终实现的效果也只能说一般。
+
+很容易我们首先想到的是让坦克完全随机游走，即每一个时钟周期内通过产生的随机数来得到该时钟周期内坦克行走的方向，而开火键直接全部设置为1，这样虽然方便写，但是最后实现出来的效果非常非常不理想，敌方坦克就像跳舞一样不知道在干嘛，这让人也很苦恼。
+
+我们最初的目的是做一个躲子弹飞快、碰见人就发射的高级AI，但是由于都是第一次使用verilog，对其中的组合逻辑控制还不够了解，也没法使用类似c语言中的dijkstra、A-star等著名的寻路算法，但是我们采用了一种比较简单的方法，基本也能保证游戏性：
+
+1. 判断自己当前位置是否在玩家1、玩家2的子弹射线上
+   - True：根据当前位置选择正确的逃跑路线，并持续至少3个时钟周期。路线选择的方法如下：只考虑和子弹垂直方向的两个方向，如子弹在上下方向那么坦克必定左右游走，并持续至少三个时钟，如果坦克过于靠近一侧边界，那么就向另一个边界走，如果在中间则那边更容易不被子弹射中往那边走。
+   - False：根据随机数模块选择是从横/竖方向接近某一玩家的坦克
+2. 判断自己是否和玩家1、玩家2的坦克在同一水平线或同一竖直线中
+   - True：调整方向，射击
+   - False：根据随机数模块选择是从横/竖方向接近某一玩家的坦克
+3. 根据随机数模块选择是从横/竖方向接近某一玩家的坦克，但每隔三个周期随机向某个方向游走一个周期。
+4. 每个10个时钟周期随机选择目前追逐的玩家1/2，并追逐10个周期。
+
+这样虽然没有达到我们最初的目的，但也很好的满足了游戏性和随机性的需求，因为有至多1/3的周期在随机方向上进行，而其他时间都在做有效移动。
+
+但是这样会导致一个问题：坦克被卡住！
+
+因为整体的碰撞检测和敌方坦克逻辑分属两个模块，在不重构代码的基础上我们很难检测到坦克被卡住了，也有可能出现四个敌方坦克在某个角度刚好被互相卡住的情况，但一般来说出现该情况的概论较小，出现该情况也不是特别影响游戏体验，因此在时间仓促的情况下我没有进行很好的优化，在展望部分我们详细对此进行了分析。
+
+
+
+### 8. 子弹控制
+
+在子弹控制中，我们只采用了一个大模块进行控制，并没有采取子弹展示和移动逻辑分开的情况。整体实现过程也是使用了一个和坦克控制类似的状态机，如图所示：
+
+~~~verilog
+always @( * ) begin: state_table
+    case ( current_state )
+        WAIT:
+            next_state = start ? READY : WAIT;
+        READY: begin
+            if ( !tank_fire ) begin
+                next_state = READY;
+            end
+            else begin
+                case ( tank_dir )
+                    2'b00:
+                        next_state = UP;
+                    2'b01:
+                        next_state = DOWN;
+                    2'b10:
+                        next_state = LEFT;
+                    2'b11:
+                        next_state = RIGHT;
+                endcase
+            end
+        end
+        UP:
+            next_state = ready ? READY : UP;
+        DOWN:
+            next_state = ready ? READY : DOWN;
+        LEFT:
+            next_state = ready ? READY : LEFT;
+        RIGHT:
+            next_state = ready ? READY : RIGHT;
+        default:
+            next_state = READY;
+    endcase
+end
+~~~
+
+炮弹的速度控制这里不再细表，值得注意的是坦克子弹也需要四张图片来选择，最后使用数据选择器进行选择当前方向的图片。
+
+还有一点需要额外说明，针对每个数据的位置，我们记录的都是其左上角点的坐标，无论是任何方向坦克还是炮弹都是如此，因此需要进行的额外计算也比较多，但只要记住每个坐标都是左上角，很多问题都可以慢慢解决。
+
+
+
+### 9. 碰撞检测与信号控制
+
+这个模块我也踩了很多的坑，首先我在多个always里对一个变量进行赋值，但是代码始终过不去综合，最后查阅资料才发现原理只能在一个always里综合，就很自闭，最后信心满满的写完了结果出现了critical warning，一直在说我有timing loop，又是找了很久后才发现是混合使用了组合逻辑和时序逻辑，结果一个的输出影响了另一个的输入，就很让人自闭。
+
+最后我们采用了细分模块object_collide_detection设计，传入两个物体的当前坐标、当前位置和当前状态，从而给出该两个物体是否产生碰撞，但是有一个很重要的问题：该游戏涉及的物体非常的多，6个坦克与6个子弹如果都要进行该检测，结果将会非常的大。最后我们选择使用了约40个object_collide_detection来对需要的物体（坦克对坦克、坦克对子弹）进行检测，最后使用时序电路对结果进行分析处理，即时给出合理的信号，如图是一个object_collide_detection使用样例：
+
+~~~verilog
+object_collide_detection tank1_enermy1(
+                             player1_tank_H, player1_tank_V, player1_tank_en_feedback, player1_tank_dir,
+                             TANK_HEIGHT, TANK_WIDTH,
+                             enermy1_tank_H, enermy1_tank_V, enermy1_tank_en_feedback, enermy1_tank_dir,
+                             TANK_HEIGHT, TANK_WIDTH,
+                             player1_tank_collide[ 0 ], player1_tank_tmp[ 0 ]
+                         );
+~~~
+
+player信号控制例子：
+
+~~~verilog
+always @( posedge clk ) begin: player2_tank_enable_signal
+
+    if ( player2_revive || item_invincible ) begin
+        player2_tank_en_feedback <= 1;
+    end
+    else if ( !reset_n ) begin
+        player2_tank_en_feedback <= 1;
+    end
+
+    else if ( enermy1_bullet_collide[ 1 ] || enermy2_bullet_collide[ 1 ] || enermy3_bullet_collide[ 1 ] || enermy4_bullet_collide[ 1 ] ) begin
+        player2_tank_en_feedback <= 0;
+    end
+
+
+    // player2_tank_en_feedback <= ~player1_bullet_collide[1];
+
+    player2_tank_move_en <= ~( | player2_tank_collide );
+end
+
+
+always @( posedge clk ) begin: player1_tank_enable_signal
+    if ( player1_revive || item_invincible ) begin
+        player1_tank_en_feedback <= 1;
+    end
+    else if ( !reset_n ) begin
+        player1_tank_en_feedback <= 1;
+    end
+
+    else if ( enermy1_bullet_collide[ 0 ] || enermy2_bullet_collide[ 0 ] || enermy3_bullet_collide[ 0 ] || enermy4_bullet_collide[ 0 ] ) begin
+        player1_tank_en_feedback <= 0;
+    end
+
+
+    player1_tank_move_en <= ~( | player1_tank_collide );
+end
+~~~
+
+最后我们检测各个模块的高电位即可进行判断赋值。
+
+结果表明，我们设计的object_collide_detection非常的合理，跑起来效果出乎意料的好，可以很好的检测到坦克间的碰撞。
+
+
+
+### 10. 物品生成控制
+
+实际上这部分代码也比较好理解，物品生成主要有三部分组成：
+
+1. item_logic控制物品生成逻辑
+2. item_display控制物品展示
+3. item_random_generate控制物品随机位置
+
+item_logic通过控制产生的信号作用到其他两个模块，每隔一段时间如果本物品还没有坦克碰到则控制下一个物品的准备生成，而如果在物品展示时间内有坦克碰到，则将该item的输出置为1代表在该物品的生效时间内，一段时间后将其置为0代表该物品失效。
+
+而item_random和item_display比较简单，这里不再赘述。
+
+这里需要提及一下各个物品的生效方法：
+
+1. 冰冻：如果该信号存在坦克的状态时钟是ready，无法移动
+2. 生命值：收到该信号的上升沿后在控制模块中增加对应玩家的生命值
+3. 时间：收到该信号的上升沿后在控制模块中增加总的游戏剩余
+4. 无敌：收到伤害后如果有该状态HP<=HP
+5. 加速器：将时钟的counter_num调小，变相加快运动速度
+
+
+
+### 11. DispNumber模块
+
+在数逻实验中我们曾经自己通过ISE画图的方式设计过并行数码管显示模块，但是我觉得我当时画图得到的模块不是很好用，并不能满足我们的需求。针对两块板子(A7/K7)，我们分别设计了串行和并行的显示模块，因为A7的8个七段数码管只支持并行输入，而K7的七段数码管只支持串行输入，这就比较伤脑筋。
+
+因此我改进了一下实验课中实现过的Disp_num使其可以有32位的输入，整体实现过程并不算复杂，但是还是花费了一点心思，代码在附录中。
+
+![seg_a7](pic/seg_a7.jpg)
+
+A7的并行七段数码管
+
+
+
+而串行输入就更具有挑战性了，我们实际上采用了65位的移位寄存器进行左移操作，同时在寄存器的同步输入端补0，当检测到基本上全部充满0时，可以证明我们这组数据已经完全被移入七段数码管中，此时我们终止clk的输入，在一定时间后我们再重复上述的操作，因此就可以得到串行的输入。LED灯同理，采用17位移位寄存器即可，整体代码在附录中。
+
+![seg_k7](pic/seg_k7.jpg)
+
+K7的串行七段数码管
+
+
+
+
+
+## 五、资源分配和RTL
+
+1. ### 资源分配和引脚图
+
+   此次课程设计使用的板子是Artix-7，我使用的资源也非常的多，包括并行七段数码管、LED灯、VGA、USB-HID等等，综合后资源使用图如下
+
+   ![image-20210114194154906](pic/image-20210114194154906.png)
+
+引脚分配图如下
+
+![image-20210114194259553](pic/image-20210114194259553.png)
+
+逻辑图如下
+
+![image-20210114202833948](pic/image-20210114202833948.png)
+
+从上面这几张图我们可以看到，这次课程作业使用的板上资源是非常非常多的，BRAM的使用率达到了95%，一共使用197cells，总计4406nets，连输出输入口都有58个，实际上在期中报告中，我本来规划做出更多的功能，但未能完全实现主要还是受到了板子资源的制约和时间制约。
+
+
+
+
+
+## 六、物理验证
+
+本次课程设计基本上全部在Nexys4 Artix-7进行，后期移植到SWORD2.0上，我们通过在Nexys4和SWORD2.0上开展，顺便也验证工程的可移植性。
+
+以下综合、实现、生成比特流均在下述配置下进行，使用开发工具为Vivado 2019.2：
+
+**CPU Name: Intel CoreTM i5-9300H CPU @ 2.40GHz**
+
+| Property            | Value                   |
+| :------------------ | :---------------------- |
+| Base Frequency      | 2.4 GHz                 |
+| Max Turbo Frequency | 4.10 GHz                |
+| Cache               | 4 MB Intel® Smart Cache |
+| Cores Number        | 4                       |
+| Threads             | 8                       |
+| TDP                 | 45W                     |
+
+**RAM: 16GB DDR4 2666MHz with Two channel memory**
+
+**SSD: SAMSUNG MZVLB1T0HBLR-000L2**
+
+
+
+### 一、Nexys4物理验证
+
+开始界面
+
+![img](pic/532271460A0702A8E095097E2E562CE1.jpg)
+
+七段数码管显示右半部分为初始生命值，左半部分为初始时间
+
+![image-20210114201846276](pic/image-20210114201846276.png)
+
+
+
+进入游戏（经典模式）
+
+![img](pic/DEF66C6936F6A86DCBB5CB35318C150F.jpg)
+
+![img](pic/22954A272C5153FA72DBB5A97BF2CBF5.jpg)
+
+![img](pic/5D25CF3D639AFEF57BAFE94E94FDF727.jpg)
+
+此时我们看下七段数码管和LED灯的输出：
+
+![img](pic/92B3FE920089039B22A286ACF464DE3F.jpg)
+
+LED灯正确表示了剩余生命值，而第三位和第七位的七段数码管的得分也显示正常
+
+
+
+重新进入游戏（无尽模式）
+
+![img](pic/DE0F7B4D4A9A38B42DC0BAF6723C5C1F.jpg)
+
+![img](pic/C7C15025DB58E4F151CD6B65FCADDFAC.jpg)
+
+七段数码管最右边一位表示剩余时间，LED灯同时也表示剩余时间
+
+![img](pic/E8282707C22A608BC2C372CADB52E344.jpg)
+
+可以看到显示正确
+
+
+
+游戏结束界面：
+
+![img](pic/3E76777AE83C2FA9843676868AA19B0B.jpg)
+
+可以看到显示数据也是完全正确的。
+
+至此，我们简单的物理验证成功，满足了最初的设计需求。
+
+
+
+
+
+### 二、SWORD2.0物理验证
+
+开始界面
+
+![img](pic/0842B11D646670FA36C3C9561F2CDED4.jpg)
+
+经典模式
+
+![img](pic/9FD7850BEE9D35BCD8F1A918592778B5.jpg)
+
+![img](pic/88B4F91A52686042330224E756EDE976.jpg)
+
+可以看到七段数码管和LED灯均正常显示
+
+游戏结束画面：
+
+![img](pic/155144434FFB37603AC66A15B922C198.jpg)
+
+
+
+无尽模式：
+
+![img](pic/72E03706BFB99ED7B96A2718E637C5E5.jpg)
+
+![img](pic/ED2E9089766F3ED06DDEED0929A1DB9D.jpg)
+
+可以看到LED灯表示剩余时间正确，七段数码管显示正确，同时上侧的时间展示正确。
+
+游戏结束画面：
+
+![img](pic/C2A8FAE8B279770017CCF60FCDB2C56E.jpg)
+
+
+
+## 七、改进思路
+
+由于时间有限，这个游戏的水准并不是特别理想。我们也想到了很多改进的方案。
+
+**1. AI坦克的移动**
+
+我们目前的随机移动策略还是很有效的，至少能让AI坦克进行较为有效的移动并开火。但是这还是显得有些笨拙，我们可以考虑换一种更加有效的移动和开火策略以增加游戏难度。比如说，移动决策不仅要根据当前敌方位置和是否开火，还应该考虑到其余三个队友的位置。同时，我们可以让坦克进行一些预判误导，比如说先向下走很长一段路，然后突然掉头，这样子会显著增加难度。
+
+
+
+**2. 添加障碍物**
+
+经典坦克大战的地图中都是有很多障碍物的，比如草，河流，砖块，石头等。它们有着不同的特性和功能，能显著增加游戏的趣味性。我们可以在将来的改进中加入这一特性。
+
+![image-20210113220701419](pic/image-20210113220701419.png)
+
+**3. 改进图像插值算法**
+
+为了节省空间，我们将背景图缩小为320*240，等到使用的时候再使用最近邻插值变换回来。但我们希望在不影响空间占用的情况下进一步提升画质，那么我们就想到了双线性插值。
+
+设目标点$P$和其他四个点$Q_{11},Q_{12},Q_{21},Q_{22}$的颜色为$f(x,y),f(x_1,y_1),f(x_1,y_2),f(x_2,y_1),f(x_2,y_2)$
+
+对目标点在$x$轴的两个投影点进行线性Lagrange插值：
+$$
+\displaystyle {
+\begin{aligned}
+f(x,y_{1}) \approx {\frac {x_{2}-x}{x_{2}-x_{1}}}f(Q_{11})+{\frac {x-x_{1}}{x_{2}-x_{1}}}f(Q_{21}),\
+f(x,y_{2}) \approx {\frac {x_{2}-x}{x_{2}-x_{1}}}f(Q_{12})+{\frac {x-x_{1}}{x_{2}-x_{1}}}f(Q_{22}).
+\end{aligned}}
+$$
+然后再对这两个点使用线性Lagrange插值，得出：
+$$
+{\displaystyle {\begin{aligned}f(x,y) \approx {\frac {y_{2}-y}{y_{2}-y_{1}}}\left({\frac {x_{2}-x}{x_{2}-x_{1}}}f(Q_{11})+{\frac {x-x_{1}}{x_{2}-x_{1}}}f(Q_{21})\right)+{\frac {y-y_{1}}{y_{2}-y_{1}}}\left({\frac {x_{2}-x}{x_{2}-x_{1}}}f(Q_{12})+{\frac {x-x_{1}}{x_{2}-x_{1}}}f(Q_{22})\right)\end{aligned}}}
+$$
+事实上，我们在网上已经看到了相关代码和ip核，比如说，有一个实现方式是这样的。但是由于实现难度较大，也考虑到如此低分辨率下该算法对画质提升有限，我们便暂时放弃了此算法。
+
+![img](pic/20151223204326956)
+
+
+
+**4. 优化坦克碰撞逻辑**
+
+我们当前只是机械的比较坦克图片的外轮廓，这并不是很精确。我们可以考虑取更多特征点进行碰撞检测，让其与视觉效果相匹配。我们可以忽略掉坦克图片四周的白边框，同时加上伸出来的炮管的碰撞检测，比如说，将炮管头也作为一个特征点，将坦克的碰撞体积改为多边形，这样可以让碰撞和实际观测相符合。
+
+
+
+##### 5. 添加音效
+
+一个真正的坦克大战游戏怎么能少了音效。实际上，这个功能的实现应当不会很复杂。虽然Nexys4-DDR板子上并没有蜂鸣器，但是我们可以利用其提供的3.5mm接口进行音频输出。Digilent上有着音频输出的相关教程。
+
+但是，这样的输出功率很可能不够，那我们就可以使用板子上的pmod扩展一个音频输出。在Digilent官网上，我们很容易就能搜索到这类组件，并且找到很多相关教程。
+
+![img](pic/1YUAFsi2lQ4bcMW.png)
+
+​	
+
+上述改进思路我们都有进行一定思考，但是苦于板上资源限制和时间限制，并没能得到实现。
+
+
+
+## 八、总结
+
+数逻的课程设计是我们大学这段时间碰到的最困难的课程设计，其困难的主要原因在于我们对Verilog语法和对开发环境的不熟悉。硬件开发与以往使用高级语言进行软件开发的感觉完全不同，两者有着截然不同的逻辑，电路的同步性也让我们需要认真思考代码的实现方式：比如说，在Verilog中，我们难以使用if语句进行条件块的跳转，而是需要在模块中生成相关信号，基于此进行分支；在移动逻辑中，使用状态机往往能够使代码更加清晰易读。除此之外，EDA工具生成过于缓慢，也占用了我们大量的时间。这个作业从头到尾花了我们接近三周的时间，由于临近期末，ddl压力大，我们做的也就比较紧张。如果有更加充裕的时间来做这个作业，我们会做的更好。
+
+
+
+## 九、成员分工
+
++ raynor：道具逻辑模块，游戏界面设计，游戏逻辑模块，PS2驱动，数码管显示模块
++ sz：坦克逻辑模块，子弹逻辑模块，碰撞检测逻辑，VGA驱动
+
+
 
-+ 坦克在被子弹射中的时候不会消失
-+ 子弹的图案显示有问题（mem读取的问题
-+ 复活计时器

TankGame.srcs/constrs_1/new/K7.xdc

@@ -66,6 +66,9 @@ set_property PACKAGE_PIN J15 [get_ports {SW[0]}]
 set_property PACKAGE_PIN L16 [get_ports {SW[1]}]
 set_property PACKAGE_PIN M13 [get_ports {SW[2]}]
 set_property PACKAGE_PIN R15 [get_ports {SW[3]}]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {SW[3]}]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {SW[2]}]
+
 set_property IOSTANDARD LVCMOS33 [get_ports {SW[3]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {SW[2]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {SW[1]}]

TankGame.srcs/sources_1/imports/ScoreBoard/CreateNumber.v

@@ -0,0 +1,39 @@
+`timescale 1ns / 1ps 
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date:    20:12:55 10/27/2020
+// Design Name:
+// Module Name:    CreateNumber
+// Project Name:
+// Target Devices:
+// Tool versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+module CreateNumber(
+           input wire [ 2: 0 ] btn,
+           output reg [ 7: 0 ] num
+       );
+wire [ 3: 0 ] heart_add, heart_minus, time_add, time_minus;
+initial
+    num <= 8'b1111_0100;
+
+assign heart_add = num[ 3: 0 ] == 6 ? num[ 3 : 0 ] : num[ 3 : 0 ] + 1'b1;
+assign heart_minus = num[ 3: 0 ] == 0 ? num[ 3 : 0 ] : num[ 3 : 0 ] - 1'b1;
+assign time_add = num[ 7: 4 ] + 1'b1;
+assign time_minus = num[ 7: 4 ] - 1'b1;
+
+always @( posedge btn[ 1 ] )
+    num[ 3: 0 ] <= btn[ 0 ] == 1'b1 ? heart_add : heart_minus;
+always @( posedge btn[ 2 ] )
+    num[ 7: 4 ] <= btn[ 0 ] == 1'b1 ? time_add : time_minus;
+
+endmodule

TankGame.srcs/sources_1/ip/lightning_20_20/doc/blk_mem_gen_v8_4_changelog.txt

@@ -0,0 +1,207 @@
+2019.2:
+ * Version 8.4 (Rev. 4)
+ * Feature Enhancement: Read Latency parameters exposed to IP GUI for URAM configurations
+
+2019.1.3:
+ * Version 8.4 (Rev. 3)
+ * No changes
+
+2019.1.2:
+ * Version 8.4 (Rev. 3)
+ * No changes
+
+2019.1.1:
+ * Version 8.4 (Rev. 3)
+ * No changes
+
+2019.1:
+ * Version 8.4 (Rev. 3)
+ * General: Internal device family change, no functional changes
+
+2018.3.1:
+ * Version 8.4 (Rev. 2)
+ * No changes
+
+2018.3:
+ * Version 8.4 (Rev. 2)
+ * Feature Enhancement: Read Latency Support added for URAM when selected through IP Integrator
+ * Other: Power Calculations disabled for URAM primitives in IP GUI, no functional changes
+ * Other: Internal device family change, no functional changes
+
+2018.2:
+ * Version 8.4 (Rev. 1)
+ * No changes
+
+2018.1:
+ * Version 8.4 (Rev. 1)
+ * No changes
+
+2017.4:
+ * Version 8.4 (Rev. 1)
+ * General: Write depth shown in IP GUI is now dependent on number of BRAMs available in a chosen device, no functional changes
+
+2017.3:
+ * Version 8.4
+ * General: Safety Circuit option is enabled by default if reset option in any one port is enabled
+
+2017.2:
+ * Version 8.3 (Rev. 6)
+ * No changes
+
+2017.1:
+ * Version 8.3 (Rev. 6)
+ * General: Internal device family change, no functional changes
+ * General: When common_clock is selected clkb is internally connected to clka, but the interface remains same to support the backword compatiability. User make sure of connecting the both the clocks to same clock source when in common_clock mode
+
+2016.4:
+ * Version 8.3 (Rev. 5)
+ * General: Fixes for behavioral Model issues when built-IN ECC is enabled (to be consistent with RTL)
+
+2016.3:
+ * Version 8.3 (Rev. 4)
+ * Feature Enhancement: URAM addressing updates while calling XPM_Memory when 32-bit addressing is enabled
+ * Other: Enable support for future devices
+ * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
+
+2016.2:
+ * Version 8.3 (Rev. 3)
+ * updated the IP,not to set WRITE_DEPTH parameter to 8192 everytime when the mode is switched to BRAM_Controller
+ * Updated the IP to support the device package changes
+
+2016.1:
+ * Version 8.3 (Rev. 2)
+ * Updated the IP to deliver only verilog behavioral model
+ * Updated the IP to support UltraRAM in IP Integrator
+ * Updated the IP to support the device package changes
+
+2015.4.2:
+ * Version 8.3 (Rev. 1)
+ * No changes
+
+2015.4.1:
+ * Version 8.3 (Rev. 1)
+ * No changes
+
+2015.4:
+ * Version 8.3 (Rev. 1)
+ * Updated the IP to support the device package changes
+
+2015.3:
+ * Version 8.3
+ * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
+ * New ports rsta_busy and rstb_busy are added to enable the safety circuitry to minimize the occurrence of BRAM data corruption
+ * Simulation models are delivered in VHDL only
+
+2015.2.1:
+ * Version 8.2 (Rev. 5)
+ * No changes
+
+2015.2:
+ * Version 8.2 (Rev. 5)
+ * No changes
+
+2015.1:
+ * Version 8.2 (Rev. 5)
+ * Delivering non encrypted behavioral models
+ * Supported memory depth is increased up to 1M words
+ * Added the power saving feature (RDADDRCHG) for ultrascale devices
+ * Supported devices and production status are now determined automatically, to simplify support for future devices
+
+2014.4.1:
+ * Version 8.2 (Rev. 4)
+ * Updated the IP to support the device package changes
+
+2014.4:
+ * Version 8.2 (Rev. 3)
+ * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
+ * Added support for 7-series Automotive (XA) and Defense Grade (XQ) devices
+ * Internal device family change, no functional changes
+
+2014.3:
+ * Version 8.2 (Rev. 2)
+ * Fixed the Memory Resource Doubling issue in Simple Dual Port RAM when aspect ratio is used
+ * Fixed the GUI crash in Simple Dual Port RAM
+ * Added support of all write modes in Simple Dual Port RAM when ECC is not used
+ * Increased the supported depth to a maximum value of 256k
+
+2014.2:
+ * Version 8.2 (Rev. 1)
+ * Updated the GUI tool tip for Byte write enable in the page-1 of block memory generator GUI
+
+2014.1:
+ * Version 8.2
+ * Added support of the cascaded Primitives of widths 1 and 2 for ultra-scale devices
+ * Added support of the ECCPIPE register in the built-in ecc mode for ultra-scale devices
+ * Added support of the dynamic power saving for ultra-scale devices
+ * Improved timing efficiency in the IP Integrator by minimizing the use of output mux for the 7-series devices
+ * Internal device family name change, no functional changes
+
+2013.4:
+ * Version 8.1
+ * The Primitive output registers are made "ON" by default in the stand alone mode
+ * Added cascaded support for ultrascale devices to construct 64Kx1 primitive by using two 32Kx1 primitives
+ * Added support for ultrascale devices
+
+2013.3:
+ * Version 8.0 (Rev. 2)
+ * Added parameter "CTRL_ECC_ALGO" for supporting ECC in  IP Integrator.
+ * Improved GUI speed and responsivness, no functional changes
+ * Reduced synthesis and simulation warnings
+ * Added support for Cadence IES and Synopsys VCS simulators
+ * Changed the default option of ENABLE PORT TYPE to "USE_ENA_PIN"
+ * Changed BRAM Interface DIN and DOUT to match bus interface directions.
+
+2013.2:
+ * Version 8.0 (Rev. 1)
+ * No Changes
+
+2013.1:
+ * Version 8.0
+ * Native Vivado Release
+ * There have been no functional or interface changes to this IP.  The version number has changed to support unique versioning in Vivado starting with 2013.1.
+
+(c) Copyright 2002 - 2019 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.

TankGame.srcs/sources_1/ip/lightning_20_20/lightning_20_20.mif

@@ -0,0 +1,400 @@
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TankGame.srcs/sources_1/ip/lightning_20_20/lightning_20_20.xci

@@ -0,0 +1,312 @@
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a100t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">csg324</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coe_File" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Load_Init_File" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_A_Write_Rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>

TankGame.srcs/sources_1/ip/lightning_20_20/lightning_20_20_ooc.xdc

@@ -0,0 +1,55 @@
+################################################################################
+#
+# (c) Copyright 2002 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+# Core Period Constraint. This constraint can be modified, and is
+# valid as long as it is met after place and route.
+create_clock -name "TS_CLKA" -period 20.0 [ get_ports clka ]
+    set_property HD.CLK_SRC BUFGCTRL_X0Y0 [ get_ports clka ]
+################################################################################

TankGame.srcs/sources_1/ip/lightning_20_20/lightning_20_20_sim_netlist.v

@@ -0,0 +1,755 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov  6 21:40:23 MST 2019
+// Date        : Wed Jan  6 17:21:01 2021
+// Host        : cxz666 running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode funcsim
+//               e:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/lightning_20_20/lightning_20_20_sim_netlist.v
+// Design      : lightning_20_20
+// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
+//               or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device      : xc7a100tcsg324-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* CHECK_LICENSE_TYPE = "lightning_20_20,blk_mem_gen_v8_4_4,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2019.2" *) 
+(* NotValidForBitStream *)
+module lightning_20_20
+   (clka,
+    ena,
+    addra,
+    douta);
+  (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) input clka;
+  (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
+  (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [8:0]addra;
+  (* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [11:0]douta;
+
+  wire [8:0]addra;
+  wire clka;
+  wire [11:0]douta;
+  wire ena;
+  wire NLW_U0_dbiterr_UNCONNECTED;
+  wire NLW_U0_rsta_busy_UNCONNECTED;
+  wire NLW_U0_rstb_busy_UNCONNECTED;
+  wire NLW_U0_s_axi_arready_UNCONNECTED;
+  wire NLW_U0_s_axi_awready_UNCONNECTED;
+  wire NLW_U0_s_axi_bvalid_UNCONNECTED;
+  wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
+  wire NLW_U0_s_axi_rlast_UNCONNECTED;
+  wire NLW_U0_s_axi_rvalid_UNCONNECTED;
+  wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
+  wire NLW_U0_s_axi_wready_UNCONNECTED;
+  wire NLW_U0_sbiterr_UNCONNECTED;
+  wire [11:0]NLW_U0_doutb_UNCONNECTED;
+  wire [8:0]NLW_U0_rdaddrecc_UNCONNECTED;
+  wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
+  wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
+  wire [8:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
+  wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
+  wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
+  wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
+
+  (* C_ADDRA_WIDTH = "9" *) 
+  (* C_ADDRB_WIDTH = "9" *) 
+  (* C_ALGORITHM = "1" *) 
+  (* C_AXI_ID_WIDTH = "4" *) 
+  (* C_AXI_SLAVE_TYPE = "0" *) 
+  (* C_AXI_TYPE = "1" *) 
+  (* C_BYTE_SIZE = "9" *) 
+  (* C_COMMON_CLK = "0" *) 
+  (* C_COUNT_18K_BRAM = "1" *) 
+  (* C_COUNT_36K_BRAM = "0" *) 
+  (* C_CTRL_ECC_ALGO = "NONE" *) 
+  (* C_DEFAULT_DATA = "0" *) 
+  (* C_DISABLE_WARN_BHV_COLL = "0" *) 
+  (* C_DISABLE_WARN_BHV_RANGE = "0" *) 
+  (* C_ELABORATION_DIR = "./" *) 
+  (* C_ENABLE_32BIT_ADDRESS = "0" *) 
+  (* C_EN_DEEPSLEEP_PIN = "0" *) 
+  (* C_EN_ECC_PIPE = "0" *) 
+  (* C_EN_RDADDRA_CHG = "0" *) 
+  (* C_EN_RDADDRB_CHG = "0" *) 
+  (* C_EN_SAFETY_CKT = "0" *) 
+  (* C_EN_SHUTDOWN_PIN = "0" *) 
+  (* C_EN_SLEEP_PIN = "0" *) 
+  (* C_EST_POWER_SUMMARY = "Estimated Power for IP     :     2.5432 mW" *) 
+  (* C_FAMILY = "artix7" *) 
+  (* C_HAS_AXI_ID = "0" *) 
+  (* C_HAS_ENA = "1" *) 
+  (* C_HAS_ENB = "0" *) 
+  (* C_HAS_INJECTERR = "0" *) 
+  (* C_HAS_MEM_OUTPUT_REGS_A = "1" *) 
+  (* C_HAS_MEM_OUTPUT_REGS_B = "0" *) 
+  (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) 
+  (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) 
+  (* C_HAS_REGCEA = "0" *) 
+  (* C_HAS_REGCEB = "0" *) 
+  (* C_HAS_RSTA = "0" *) 
+  (* C_HAS_RSTB = "0" *) 
+  (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) 
+  (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) 
+  (* C_INITA_VAL = "0" *) 
+  (* C_INITB_VAL = "0" *) 
+  (* C_INIT_FILE = "lightning_20_20.mem" *) 
+  (* C_INIT_FILE_NAME = "lightning_20_20.mif" *) 
+  (* C_INTERFACE_TYPE = "0" *) 
+  (* C_LOAD_INIT_FILE = "1" *) 
+  (* C_MEM_TYPE = "3" *) 
+  (* C_MUX_PIPELINE_STAGES = "0" *) 
+  (* C_PRIM_TYPE = "1" *) 
+  (* C_READ_DEPTH_A = "400" *) 
+  (* C_READ_DEPTH_B = "400" *) 
+  (* C_READ_LATENCY_A = "1" *) 
+  (* C_READ_LATENCY_B = "1" *) 
+  (* C_READ_WIDTH_A = "12" *) 
+  (* C_READ_WIDTH_B = "12" *) 
+  (* C_RSTRAM_A = "0" *) 
+  (* C_RSTRAM_B = "0" *) 
+  (* C_RST_PRIORITY_A = "CE" *) 
+  (* C_RST_PRIORITY_B = "CE" *) 
+  (* C_SIM_COLLISION_CHECK = "ALL" *) 
+  (* C_USE_BRAM_BLOCK = "0" *) 
+  (* C_USE_BYTE_WEA = "0" *) 
+  (* C_USE_BYTE_WEB = "0" *) 
+  (* C_USE_DEFAULT_DATA = "0" *) 
+  (* C_USE_ECC = "0" *) 
+  (* C_USE_SOFTECC = "0" *) 
+  (* C_USE_URAM = "0" *) 
+  (* C_WEA_WIDTH = "1" *) 
+  (* C_WEB_WIDTH = "1" *) 
+  (* C_WRITE_DEPTH_A = "400" *) 
+  (* C_WRITE_DEPTH_B = "400" *) 
+  (* C_WRITE_MODE_A = "WRITE_FIRST" *) 
+  (* C_WRITE_MODE_B = "WRITE_FIRST" *) 
+  (* C_WRITE_WIDTH_A = "12" *) 
+  (* C_WRITE_WIDTH_B = "12" *) 
+  (* C_XDEVICEFAMILY = "artix7" *) 
+  (* downgradeipidentifiedwarnings = "yes" *) 
+  lightning_20_20_blk_mem_gen_v8_4_4 U0
+       (.addra(addra),
+        .addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .clka(clka),
+        .clkb(1'b0),
+        .dbiterr(NLW_U0_dbiterr_UNCONNECTED),
+        .deepsleep(1'b0),
+        .dina({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .douta(douta),
+        .doutb(NLW_U0_doutb_UNCONNECTED[11:0]),
+        .eccpipece(1'b0),
+        .ena(ena),
+        .enb(1'b0),
+        .injectdbiterr(1'b0),
+        .injectsbiterr(1'b0),
+        .rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[8:0]),
+        .regcea(1'b0),
+        .regceb(1'b0),
+        .rsta(1'b0),
+        .rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
+        .rstb(1'b0),
+        .rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
+        .s_aclk(1'b0),
+        .s_aresetn(1'b0),
+        .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .s_axi_arburst({1'b0,1'b0}),
+        .s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
+        .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
+        .s_axi_arsize({1'b0,1'b0,1'b0}),
+        .s_axi_arvalid(1'b0),
+        .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .s_axi_awburst({1'b0,1'b0}),
+        .s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
+        .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
+        .s_axi_awsize({1'b0,1'b0,1'b0}),
+        .s_axi_awvalid(1'b0),
+        .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
+        .s_axi_bready(1'b0),
+        .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
+        .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
+        .s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
+        .s_axi_injectdbiterr(1'b0),
+        .s_axi_injectsbiterr(1'b0),
+        .s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[8:0]),
+        .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
+        .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
+        .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
+        .s_axi_rready(1'b0),
+        .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
+        .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
+        .s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
+        .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .s_axi_wlast(1'b0),
+        .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
+        .s_axi_wstrb(1'b0),
+        .s_axi_wvalid(1'b0),
+        .sbiterr(NLW_U0_sbiterr_UNCONNECTED),
+        .shutdown(1'b0),
+        .sleep(1'b0),
+        .wea(1'b0),
+        .web(1'b0));
+endmodule
+
+(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *) 
+module lightning_20_20_blk_mem_gen_generic_cstr
+   (douta,
+    clka,
+    ena,
+    addra);
+  output [11:0]douta;
+  input clka;
+  input ena;
+  input [8:0]addra;
+
+  wire [8:0]addra;
+  wire clka;
+  wire [11:0]douta;
+  wire ena;
+
+  lightning_20_20_blk_mem_gen_prim_width \ramloop[0].ram.r 
+       (.addra(addra),
+        .clka(clka),
+        .douta(douta),
+        .ena(ena));
+endmodule
+
+(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *) 
+module lightning_20_20_blk_mem_gen_prim_width
+   (douta,
+    clka,
+    ena,
+    addra);
+  output [11:0]douta;
+  input clka;
+  input ena;
+  input [8:0]addra;
+
+  wire [8:0]addra;
+  wire clka;
+  wire [11:0]douta;
+  wire ena;
+
+  lightning_20_20_blk_mem_gen_prim_wrapper_init \prim_init.ram 
+       (.addra(addra),
+        .clka(clka),
+        .douta(douta),
+        .ena(ena));
+endmodule
+
+(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *) 
+module lightning_20_20_blk_mem_gen_prim_wrapper_init
+   (douta,
+    clka,
+    ena,
+    addra);
+  output [11:0]douta;
+  input clka;
+  input ena;
+  input [8:0]addra;
+
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8 ;
+  wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9 ;
+  wire [8:0]addra;
+  wire clka;
+  wire [11:0]douta;
+  wire ena;
+
+  (* box_type = "PRIMITIVE" *) 
+  RAMB18E1 #(
+    .DOA_REG(1),
+    .DOB_REG(1),
+    .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_00(256'h0506070706070507070707070707070707070707070707070707070707070707),
+    .INIT_01(256'h0707070707070707060705070506070702050506000405050004050502050506),
+    .INIT_02(256'h0707070707070707070707070707070707070707070707070707070707070707),
+    .INIT_03(256'h0301070606070307060703070301070600000305000405050105010505020507),
+    .INIT_04(256'h0707070707070707070707070707070705020507010501050004050500000305),
+    .INIT_05(256'h0707070705020507030107060004070500040505020505060707070707070707),
+    .INIT_06(256'h0004070503010706050205070707070707070707070707070707070707070707),
+    .INIT_07(256'h0507010700000505070707070707070707070707070707070205050600040505),
+    .INIT_08(256'h0703050707070707070707070707070707070707070707070707070707070707),
+    .INIT_09(256'h0707070707070707000005050507010707070707070707070707070707070707),
+    .INIT_0A(256'h0707070707070707070707070707070706070307000005050707070707070707),
+    .INIT_0B(256'h0707070707070707070707070707070705060707070707070707070707070707),
+    .INIT_0C(256'h0607030700000505070707070707070707070707070707070000050506070307),
+    .INIT_0D(256'h0502050703050706070707070707070707070707070707070707070707070707),
+    .INIT_0E(256'h0707070707070707000005050607030707070707070707070707070707070707),
+    .INIT_0F(256'h0707070707070707070707070707070706070307000005050707070707070707),
+    .INIT_10(256'h0707070707070707070707070707070705060707000005050507010707070707),
+    .INIT_11(256'h0607030700040505070707070707070707070707070707070000050506070307),
+    .INIT_12(256'h0607030700000305000407050607030707070707070707070707070707070707),
+    .INIT_13(256'h0707070707070707000405050607030707070707070707070707070707070707),
+    .INIT_14(256'h0707070707070707070707070707070706070307000405050707070707070707),
+    .INIT_15(256'h0707070707070707070707070707070707030507000003050000030502010306),
+    .INIT_16(256'h0607030700040505070707070707070707070707070707070004050506070307),
+    .INIT_17(256'h0105030600000305000003050000030503060106070707070707070707070707),
+    .INIT_18(256'h0707070707070707000405050607030707070707070707070607030702010306),
+    .INIT_19(256'h0201030606070307070707070707070706070307000405050707070707070707),
+    .INIT_1A(256'h0707070707070707070707070306010600000305000003050000030501050306),
+    .INIT_1B(256'h0607030700040705070707070707070707070707070707070004050506070307),
+    .INIT_1C(256'h0201030600000305000003050703050707070707070707070707070707070707),
+    .INIT_1D(256'h0707070707070707000407050607030707070707070707070707070707070707),
+    .INIT_1E(256'h0707070707070707070707070707070706070307000407050707070707070707),
+    .INIT_1F(256'h0707070707070707070707070707070706070307000407050000030506070307),
+    .INIT_20(256'h0406030601050106070707070707070707070707070707070004070506070307),
+    .INIT_21(256'h0707070705070107000005050507010707070707070707070707070707070707),
+    .INIT_22(256'h0707070707070707010501060406030607070707070707070707070707070707),
+    .INIT_23(256'h0707070707070707070707070707070700040505040203060707070707070707),
+    .INIT_24(256'h0707070707070707070707070707070707070707070707070305070605020507),
+    .INIT_25(256'h0201030607070707070707070707070707070707070707070402030600040505),
+    .INIT_26(256'h0707070707070707070707070506070707070707070707070607030701000705),
+    .INIT_27(256'h0707070707070707070707070201030601000705060703070707070707070707),
+    .INIT_28(256'h0707070705020707000405050100070507070707070707070707070707070707),
+    .INIT_29(256'h0105010500040505050607070707070707070707070707070707070707030707),
+    .INIT_2A(256'h0707070707070707070707070707070707070707070707070707070707070707),
+    .INIT_2B(256'h0607030707070707070707070603010702050506000405050402030607070707),
+    .INIT_2C(256'h0707070707070707070707070707070707070707040603060100070503010706),
+    .INIT_2D(256'h0100070506030107070707070707070707070707070707070707070707070707),
+    .INIT_2E(256'h0707070707070707070305070105010600000505030601060306010600000505),
+    .INIT_2F(256'h0707070707070707070707070707070707070707070707070707070707070707),
+    .INIT_30(256'h0502070701050106010501060506070707070707070707070707070707070707),
+    .INIT_31(256'h0707070707070707070707070707070707070707070707070707070707070707),
+    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
+    .INIT_A(18'h00000),
+    .INIT_B(18'h00000),
+    .INIT_FILE("NONE"),
+    .IS_CLKARDCLK_INVERTED(1'b0),
+    .IS_CLKBWRCLK_INVERTED(1'b0),
+    .IS_ENARDEN_INVERTED(1'b0),
+    .IS_ENBWREN_INVERTED(1'b0),
+    .IS_RSTRAMARSTRAM_INVERTED(1'b0),
+    .IS_RSTRAMB_INVERTED(1'b0),
+    .IS_RSTREGARSTREG_INVERTED(1'b0),
+    .IS_RSTREGB_INVERTED(1'b0),
+    .RAM_MODE("TDP"),
+    .RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
+    .READ_WIDTH_A(18),
+    .READ_WIDTH_B(18),
+    .RSTREG_PRIORITY_A("REGCE"),
+    .RSTREG_PRIORITY_B("REGCE"),
+    .SIM_COLLISION_CHECK("ALL"),
+    .SIM_DEVICE("7SERIES"),
+    .SRVAL_A(18'h00000),
+    .SRVAL_B(18'h00000),
+    .WRITE_MODE_A("WRITE_FIRST"),
+    .WRITE_MODE_B("WRITE_FIRST"),
+    .WRITE_WIDTH_A(18),
+    .WRITE_WIDTH_B(18)) 
+    \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram 
+       (.ADDRARDADDR({addra,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .ADDRBWRADDR({addra,1'b1,1'b0,1'b0,1'b0,1'b0}),
+        .CLKARDCLK(clka),
+        .CLKBWRCLK(clka),
+        .DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+        .DIPADIP({1'b0,1'b0}),
+        .DIPBDIP({1'b0,1'b0}),
+        .DOADO({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4 ,douta[5:3],\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12 ,douta[2:0]}),
+        .DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20 ,douta[11:9],\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28 ,douta[8:6]}),
+        .DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 }),
+        .DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 }),
+        .ENARDEN(ena),
+        .ENBWREN(ena),
+        .REGCEAREGCE(ena),
+        .REGCEB(ena),
+        .RSTRAMARSTRAM(1'b0),
+        .RSTRAMB(1'b0),
+        .RSTREGARSTREG(1'b0),
+        .RSTREGB(1'b0),
+        .WEA({1'b0,1'b0}),
+        .WEBWE({1'b0,1'b0,1'b0,1'b0}));
+endmodule
+
+(* ORIG_REF_NAME = "blk_mem_gen_top" *) 
+module lightning_20_20_blk_mem_gen_top
+   (douta,
+    clka,
+    ena,
+    addra);
+  output [11:0]douta;
+  input clka;
+  input ena;
+  input [8:0]addra;
+
+  wire [8:0]addra;
+  wire clka;
+  wire [11:0]douta;
+  wire ena;
+
+  lightning_20_20_blk_mem_gen_generic_cstr \valid.cstr 
+       (.addra(addra),
+        .clka(clka),
+        .douta(douta),
+        .ena(ena));
+endmodule
+
+(* C_ADDRA_WIDTH = "9" *) (* C_ADDRB_WIDTH = "9" *) (* C_ALGORITHM = "1" *) 
+(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *) 
+(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *) 
+(* C_COUNT_36K_BRAM = "0" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *) 
+(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *) 
+(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *) 
+(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *) 
+(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP     :     2.5432 mW" *) 
+(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *) 
+(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *) 
+(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) 
+(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *) 
+(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) 
+(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "lightning_20_20.mem" *) 
+(* C_INIT_FILE_NAME = "lightning_20_20.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *) 
+(* C_MEM_TYPE = "3" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *) 
+(* C_READ_DEPTH_A = "400" *) (* C_READ_DEPTH_B = "400" *) (* C_READ_LATENCY_A = "1" *) 
+(* C_READ_LATENCY_B = "1" *) (* C_READ_WIDTH_A = "12" *) (* C_READ_WIDTH_B = "12" *) 
+(* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *) 
+(* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *) 
+(* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *) 
+(* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *) 
+(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "400" *) 
+(* C_WRITE_DEPTH_B = "400" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) 
+(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *) 
+(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *) 
+module lightning_20_20_blk_mem_gen_v8_4_4
+   (clka,
+    rsta,
+    ena,
+    regcea,
+    wea,
+    addra,
+    dina,
+    douta,
+    clkb,
+    rstb,
+    enb,
+    regceb,
+    web,
+    addrb,
+    dinb,
+    doutb,
+    injectsbiterr,
+    injectdbiterr,
+    eccpipece,
+    sbiterr,
+    dbiterr,
+    rdaddrecc,
+    sleep,
+    deepsleep,
+    shutdown,
+    rsta_busy,
+    rstb_busy,
+    s_aclk,
+    s_aresetn,
+    s_axi_awid,
+    s_axi_awaddr,
+    s_axi_awlen,
+    s_axi_awsize,
+    s_axi_awburst,
+    s_axi_awvalid,
+    s_axi_awready,
+    s_axi_wdata,
+    s_axi_wstrb,
+    s_axi_wlast,
+    s_axi_wvalid,
+    s_axi_wready,
+    s_axi_bid,
+    s_axi_bresp,
+    s_axi_bvalid,
+    s_axi_bready,
+    s_axi_arid,
+    s_axi_araddr,
+    s_axi_arlen,
+    s_axi_arsize,
+    s_axi_arburst,
+    s_axi_arvalid,
+    s_axi_arready,
+    s_axi_rid,
+    s_axi_rdata,
+    s_axi_rresp,
+    s_axi_rlast,
+    s_axi_rvalid,
+    s_axi_rready,
+    s_axi_injectsbiterr,
+    s_axi_injectdbiterr,
+    s_axi_sbiterr,
+    s_axi_dbiterr,
+    s_axi_rdaddrecc);
+  input clka;
+  input rsta;
+  input ena;
+  input regcea;
+  input [0:0]wea;
+  input [8:0]addra;
+  input [11:0]dina;
+  output [11:0]douta;
+  input clkb;
+  input rstb;
+  input enb;
+  input regceb;
+  input [0:0]web;
+  input [8:0]addrb;
+  input [11:0]dinb;
+  output [11:0]doutb;
+  input injectsbiterr;
+  input injectdbiterr;
+  input eccpipece;
+  output sbiterr;
+  output dbiterr;
+  output [8:0]rdaddrecc;
+  input sleep;
+  input deepsleep;
+  input shutdown;
+  output rsta_busy;
+  output rstb_busy;
+  input s_aclk;
+  input s_aresetn;
+  input [3:0]s_axi_awid;
+  input [31:0]s_axi_awaddr;
+  input [7:0]s_axi_awlen;
+  input [2:0]s_axi_awsize;
+  input [1:0]s_axi_awburst;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [11:0]s_axi_wdata;
+  input [0:0]s_axi_wstrb;
+  input s_axi_wlast;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [3:0]s_axi_bid;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [3:0]s_axi_arid;
+  input [31:0]s_axi_araddr;
+  input [7:0]s_axi_arlen;
+  input [2:0]s_axi_arsize;
+  input [1:0]s_axi_arburst;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [3:0]s_axi_rid;
+  output [11:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rlast;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  input s_axi_injectsbiterr;
+  input s_axi_injectdbiterr;
+  output s_axi_sbiterr;
+  output s_axi_dbiterr;
+  output [8:0]s_axi_rdaddrecc;
+
+  wire \<const0> ;
+  wire [8:0]addra;
+  wire clka;
+  wire [11:0]douta;
+  wire ena;
+
+  assign dbiterr = \<const0> ;
+  assign doutb[11] = \<const0> ;
+  assign doutb[10] = \<const0> ;
+  assign doutb[9] = \<const0> ;
+  assign doutb[8] = \<const0> ;
+  assign doutb[7] = \<const0> ;
+  assign doutb[6] = \<const0> ;
+  assign doutb[5] = \<const0> ;
+  assign doutb[4] = \<const0> ;
+  assign doutb[3] = \<const0> ;
+  assign doutb[2] = \<const0> ;
+  assign doutb[1] = \<const0> ;
+  assign doutb[0] = \<const0> ;
+  assign rdaddrecc[8] = \<const0> ;
+  assign rdaddrecc[7] = \<const0> ;
+  assign rdaddrecc[6] = \<const0> ;
+  assign rdaddrecc[5] = \<const0> ;
+  assign rdaddrecc[4] = \<const0> ;
+  assign rdaddrecc[3] = \<const0> ;
+  assign rdaddrecc[2] = \<const0> ;
+  assign rdaddrecc[1] = \<const0> ;
+  assign rdaddrecc[0] = \<const0> ;
+  assign rsta_busy = \<const0> ;
+  assign rstb_busy = \<const0> ;
+  assign s_axi_arready = \<const0> ;
+  assign s_axi_awready = \<const0> ;
+  assign s_axi_bid[3] = \<const0> ;
+  assign s_axi_bid[2] = \<const0> ;
+  assign s_axi_bid[1] = \<const0> ;
+  assign s_axi_bid[0] = \<const0> ;
+  assign s_axi_bresp[1] = \<const0> ;
+  assign s_axi_bresp[0] = \<const0> ;
+  assign s_axi_bvalid = \<const0> ;
+  assign s_axi_dbiterr = \<const0> ;
+  assign s_axi_rdaddrecc[8] = \<const0> ;
+  assign s_axi_rdaddrecc[7] = \<const0> ;
+  assign s_axi_rdaddrecc[6] = \<const0> ;
+  assign s_axi_rdaddrecc[5] = \<const0> ;
+  assign s_axi_rdaddrecc[4] = \<const0> ;
+  assign s_axi_rdaddrecc[3] = \<const0> ;
+  assign s_axi_rdaddrecc[2] = \<const0> ;
+  assign s_axi_rdaddrecc[1] = \<const0> ;
+  assign s_axi_rdaddrecc[0] = \<const0> ;
+  assign s_axi_rdata[11] = \<const0> ;
+  assign s_axi_rdata[10] = \<const0> ;
+  assign s_axi_rdata[9] = \<const0> ;
+  assign s_axi_rdata[8] = \<const0> ;
+  assign s_axi_rdata[7] = \<const0> ;
+  assign s_axi_rdata[6] = \<const0> ;
+  assign s_axi_rdata[5] = \<const0> ;
+  assign s_axi_rdata[4] = \<const0> ;
+  assign s_axi_rdata[3] = \<const0> ;
+  assign s_axi_rdata[2] = \<const0> ;
+  assign s_axi_rdata[1] = \<const0> ;
+  assign s_axi_rdata[0] = \<const0> ;
+  assign s_axi_rid[3] = \<const0> ;
+  assign s_axi_rid[2] = \<const0> ;
+  assign s_axi_rid[1] = \<const0> ;
+  assign s_axi_rid[0] = \<const0> ;
+  assign s_axi_rlast = \<const0> ;
+  assign s_axi_rresp[1] = \<const0> ;
+  assign s_axi_rresp[0] = \<const0> ;
+  assign s_axi_rvalid = \<const0> ;
+  assign s_axi_sbiterr = \<const0> ;
+  assign s_axi_wready = \<const0> ;
+  assign sbiterr = \<const0> ;
+  GND GND
+       (.G(\<const0> ));
+  lightning_20_20_blk_mem_gen_v8_4_4_synth inst_blk_mem_gen
+       (.addra(addra),
+        .clka(clka),
+        .douta(douta),
+        .ena(ena));
+endmodule
+
+(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *) 
+module lightning_20_20_blk_mem_gen_v8_4_4_synth
+   (douta,
+    clka,
+    ena,
+    addra);
+  output [11:0]douta;
+  input clka;
+  input ena;
+  input [8:0]addra;
+
+  wire [8:0]addra;
+  wire clka;
+  wire [11:0]douta;
+  wire ena;
+
+  lightning_20_20_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen 
+       (.addra(addra),
+        .clka(clka),
+        .douta(douta),
+        .ena(ena));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

TankGame.srcs/sources_1/ip/lightning_20_20/lightning_20_20_sim_netlist.vhdl

@@ -0,0 +1,883 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov  6 21:40:23 MST 2019
+-- Date        : Wed Jan  6 17:21:01 2021
+-- Host        : cxz666 running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode funcsim
+--               e:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/lightning_20_20/lightning_20_20_sim_netlist.vhdl
+-- Design      : lightning_20_20
+-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+--               synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device      : xc7a100tcsg324-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity lightning_20_20_blk_mem_gen_prim_wrapper_init is
+  port (
+    douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
+    clka : in STD_LOGIC;
+    ena : in STD_LOGIC;
+    addra : in STD_LOGIC_VECTOR ( 8 downto 0 )
+  );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of lightning_20_20_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
+end lightning_20_20_blk_mem_gen_prim_wrapper_init;
+
+architecture STRUCTURE of lightning_20_20_blk_mem_gen_prim_wrapper_init is
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8\ : STD_LOGIC;
+  signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9\ : STD_LOGIC;
+  attribute box_type : string;
+  attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
+begin
+\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
+    generic map(
+      DOA_REG => 1,
+      DOB_REG => 1,
+      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_00 => X"0506070706070507070707070707070707070707070707070707070707070707",
+      INIT_01 => X"0707070707070707060705070506070702050506000405050004050502050506",
+      INIT_02 => X"0707070707070707070707070707070707070707070707070707070707070707",
+      INIT_03 => X"0301070606070307060703070301070600000305000405050105010505020507",
+      INIT_04 => X"0707070707070707070707070707070705020507010501050004050500000305",
+      INIT_05 => X"0707070705020507030107060004070500040505020505060707070707070707",
+      INIT_06 => X"0004070503010706050205070707070707070707070707070707070707070707",
+      INIT_07 => X"0507010700000505070707070707070707070707070707070205050600040505",
+      INIT_08 => X"0703050707070707070707070707070707070707070707070707070707070707",
+      INIT_09 => X"0707070707070707000005050507010707070707070707070707070707070707",
+      INIT_0A => X"0707070707070707070707070707070706070307000005050707070707070707",
+      INIT_0B => X"0707070707070707070707070707070705060707070707070707070707070707",
+      INIT_0C => X"0607030700000505070707070707070707070707070707070000050506070307",
+      INIT_0D => X"0502050703050706070707070707070707070707070707070707070707070707",
+      INIT_0E => X"0707070707070707000005050607030707070707070707070707070707070707",
+      INIT_0F => X"0707070707070707070707070707070706070307000005050707070707070707",
+      INIT_10 => X"0707070707070707070707070707070705060707000005050507010707070707",
+      INIT_11 => X"0607030700040505070707070707070707070707070707070000050506070307",
+      INIT_12 => X"0607030700000305000407050607030707070707070707070707070707070707",
+      INIT_13 => X"0707070707070707000405050607030707070707070707070707070707070707",
+      INIT_14 => X"0707070707070707070707070707070706070307000405050707070707070707",
+      INIT_15 => X"0707070707070707070707070707070707030507000003050000030502010306",
+      INIT_16 => X"0607030700040505070707070707070707070707070707070004050506070307",
+      INIT_17 => X"0105030600000305000003050000030503060106070707070707070707070707",
+      INIT_18 => X"0707070707070707000405050607030707070707070707070607030702010306",
+      INIT_19 => X"0201030606070307070707070707070706070307000405050707070707070707",
+      INIT_1A => X"0707070707070707070707070306010600000305000003050000030501050306",
+      INIT_1B => X"0607030700040705070707070707070707070707070707070004050506070307",
+      INIT_1C => X"0201030600000305000003050703050707070707070707070707070707070707",
+      INIT_1D => X"0707070707070707000407050607030707070707070707070707070707070707",
+      INIT_1E => X"0707070707070707070707070707070706070307000407050707070707070707",
+      INIT_1F => X"0707070707070707070707070707070706070307000407050000030506070307",
+      INIT_20 => X"0406030601050106070707070707070707070707070707070004070506070307",
+      INIT_21 => X"0707070705070107000005050507010707070707070707070707070707070707",
+      INIT_22 => X"0707070707070707010501060406030607070707070707070707070707070707",
+      INIT_23 => X"0707070707070707070707070707070700040505040203060707070707070707",
+      INIT_24 => X"0707070707070707070707070707070707070707070707070305070605020507",
+      INIT_25 => X"0201030607070707070707070707070707070707070707070402030600040505",
+      INIT_26 => X"0707070707070707070707070506070707070707070707070607030701000705",
+      INIT_27 => X"0707070707070707070707070201030601000705060703070707070707070707",
+      INIT_28 => X"0707070705020707000405050100070507070707070707070707070707070707",
+      INIT_29 => X"0105010500040505050607070707070707070707070707070707070707030707",
+      INIT_2A => X"0707070707070707070707070707070707070707070707070707070707070707",
+      INIT_2B => X"0607030707070707070707070603010702050506000405050402030607070707",
+      INIT_2C => X"0707070707070707070707070707070707070707040603060100070503010706",
+      INIT_2D => X"0100070506030107070707070707070707070707070707070707070707070707",
+      INIT_2E => X"0707070707070707070305070105010600000505030601060306010600000505",
+      INIT_2F => X"0707070707070707070707070707070707070707070707070707070707070707",
+      INIT_30 => X"0502070701050106010501060506070707070707070707070707070707070707",
+      INIT_31 => X"0707070707070707070707070707070707070707070707070707070707070707",
+      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
+      INIT_A => X"00000",
+      INIT_B => X"00000",
+      INIT_FILE => "NONE",
+      IS_CLKARDCLK_INVERTED => '0',
+      IS_CLKBWRCLK_INVERTED => '0',
+      IS_ENARDEN_INVERTED => '0',
+      IS_ENBWREN_INVERTED => '0',
+      IS_RSTRAMARSTRAM_INVERTED => '0',
+      IS_RSTRAMB_INVERTED => '0',
+      IS_RSTREGARSTREG_INVERTED => '0',
+      IS_RSTREGB_INVERTED => '0',
+      RAM_MODE => "TDP",
+      RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
+      READ_WIDTH_A => 18,
+      READ_WIDTH_B => 18,
+      RSTREG_PRIORITY_A => "REGCE",
+      RSTREG_PRIORITY_B => "REGCE",
+      SIM_COLLISION_CHECK => "ALL",
+      SIM_DEVICE => "7SERIES",
+      SRVAL_A => X"00000",
+      SRVAL_B => X"00000",
+      WRITE_MODE_A => "WRITE_FIRST",
+      WRITE_MODE_B => "WRITE_FIRST",
+      WRITE_WIDTH_A => 18,
+      WRITE_WIDTH_B => 18
+    )
+        port map (
+      ADDRARDADDR(13 downto 5) => addra(8 downto 0),
+      ADDRARDADDR(4 downto 0) => B"00000",
+      ADDRBWRADDR(13 downto 5) => addra(8 downto 0),
+      ADDRBWRADDR(4 downto 0) => B"10000",
+      CLKARDCLK => clka,
+      CLKBWRCLK => clka,
+      DIADI(15 downto 0) => B"0000000000000000",
+      DIBDI(15 downto 0) => B"0000000000000000",
+      DIPADIP(1 downto 0) => B"00",
+      DIPBDIP(1 downto 0) => B"00",
+      DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0\,
+      DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1\,
+      DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2\,
+      DOADO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3\,
+      DOADO(11) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4\,
+      DOADO(10 downto 8) => douta(5 downto 3),
+      DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8\,
+      DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9\,
+      DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10\,
+      DOADO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11\,
+      DOADO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12\,
+      DOADO(2 downto 0) => douta(2 downto 0),
+      DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16\,
+      DOBDO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17\,
+      DOBDO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18\,
+      DOBDO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19\,
+      DOBDO(11) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20\,
+      DOBDO(10 downto 8) => douta(11 downto 9),
+      DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24\,
+      DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25\,
+      DOBDO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26\,
+      DOBDO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27\,
+      DOBDO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28\,
+      DOBDO(2 downto 0) => douta(8 downto 6),
+      DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\,
+      DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\,
+      DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\,
+      DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\,
+      ENARDEN => ena,
+      ENBWREN => ena,
+      REGCEAREGCE => ena,
+      REGCEB => ena,
+      RSTRAMARSTRAM => '0',
+      RSTRAMB => '0',
+      RSTREGARSTREG => '0',
+      RSTREGB => '0',
+      WEA(1 downto 0) => B"00",
+      WEBWE(3 downto 0) => B"0000"
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity lightning_20_20_blk_mem_gen_prim_width is
+  port (
+    douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
+    clka : in STD_LOGIC;
+    ena : in STD_LOGIC;
+    addra : in STD_LOGIC_VECTOR ( 8 downto 0 )
+  );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of lightning_20_20_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
+end lightning_20_20_blk_mem_gen_prim_width;
+
+architecture STRUCTURE of lightning_20_20_blk_mem_gen_prim_width is
+begin
+\prim_init.ram\: entity work.lightning_20_20_blk_mem_gen_prim_wrapper_init
+     port map (
+      addra(8 downto 0) => addra(8 downto 0),
+      clka => clka,
+      douta(11 downto 0) => douta(11 downto 0),
+      ena => ena
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity lightning_20_20_blk_mem_gen_generic_cstr is
+  port (
+    douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
+    clka : in STD_LOGIC;
+    ena : in STD_LOGIC;
+    addra : in STD_LOGIC_VECTOR ( 8 downto 0 )
+  );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of lightning_20_20_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
+end lightning_20_20_blk_mem_gen_generic_cstr;
+
+architecture STRUCTURE of lightning_20_20_blk_mem_gen_generic_cstr is
+begin
+\ramloop[0].ram.r\: entity work.lightning_20_20_blk_mem_gen_prim_width
+     port map (
+      addra(8 downto 0) => addra(8 downto 0),
+      clka => clka,
+      douta(11 downto 0) => douta(11 downto 0),
+      ena => ena
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity lightning_20_20_blk_mem_gen_top is
+  port (
+    douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
+    clka : in STD_LOGIC;
+    ena : in STD_LOGIC;
+    addra : in STD_LOGIC_VECTOR ( 8 downto 0 )
+  );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of lightning_20_20_blk_mem_gen_top : entity is "blk_mem_gen_top";
+end lightning_20_20_blk_mem_gen_top;
+
+architecture STRUCTURE of lightning_20_20_blk_mem_gen_top is
+begin
+\valid.cstr\: entity work.lightning_20_20_blk_mem_gen_generic_cstr
+     port map (
+      addra(8 downto 0) => addra(8 downto 0),
+      clka => clka,
+      douta(11 downto 0) => douta(11 downto 0),
+      ena => ena
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity lightning_20_20_blk_mem_gen_v8_4_4_synth is
+  port (
+    douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
+    clka : in STD_LOGIC;
+    ena : in STD_LOGIC;
+    addra : in STD_LOGIC_VECTOR ( 8 downto 0 )
+  );
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of lightning_20_20_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
+end lightning_20_20_blk_mem_gen_v8_4_4_synth;
+
+architecture STRUCTURE of lightning_20_20_blk_mem_gen_v8_4_4_synth is
+begin
+\gnbram.gnativebmg.native_blk_mem_gen\: entity work.lightning_20_20_blk_mem_gen_top
+     port map (
+      addra(8 downto 0) => addra(8 downto 0),
+      clka => clka,
+      douta(11 downto 0) => douta(11 downto 0),
+      ena => ena
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity lightning_20_20_blk_mem_gen_v8_4_4 is
+  port (
+    clka : in STD_LOGIC;
+    rsta : in STD_LOGIC;
+    ena : in STD_LOGIC;
+    regcea : in STD_LOGIC;
+    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
+    addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
+    clkb : in STD_LOGIC;
+    rstb : in STD_LOGIC;
+    enb : in STD_LOGIC;
+    regceb : in STD_LOGIC;
+    web : in STD_LOGIC_VECTOR ( 0 to 0 );
+    addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
+    injectsbiterr : in STD_LOGIC;
+    injectdbiterr : in STD_LOGIC;
+    eccpipece : in STD_LOGIC;
+    sbiterr : out STD_LOGIC;
+    dbiterr : out STD_LOGIC;
+    rdaddrecc : out STD_LOGIC_VECTOR ( 8 downto 0 );
+    sleep : in STD_LOGIC;
+    deepsleep : in STD_LOGIC;
+    shutdown : in STD_LOGIC;
+    rsta_busy : out STD_LOGIC;
+    rstb_busy : out STD_LOGIC;
+    s_aclk : in STD_LOGIC;
+    s_aresetn : in STD_LOGIC;
+    s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
+    s_axi_wlast : in STD_LOGIC;
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_wready : out STD_LOGIC;
+    s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_arready : out STD_LOGIC;
+    s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rlast : out STD_LOGIC;
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    s_axi_injectsbiterr : in STD_LOGIC;
+    s_axi_injectdbiterr : in STD_LOGIC;
+    s_axi_sbiterr : out STD_LOGIC;
+    s_axi_dbiterr : out STD_LOGIC;
+    s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 8 downto 0 )
+  );
+  attribute C_ADDRA_WIDTH : integer;
+  attribute C_ADDRA_WIDTH of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 9;
+  attribute C_ADDRB_WIDTH : integer;
+  attribute C_ADDRB_WIDTH of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 9;
+  attribute C_ALGORITHM : integer;
+  attribute C_ALGORITHM of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 1;
+  attribute C_AXI_ID_WIDTH : integer;
+  attribute C_AXI_ID_WIDTH of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 4;
+  attribute C_AXI_SLAVE_TYPE : integer;
+  attribute C_AXI_SLAVE_TYPE of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_AXI_TYPE : integer;
+  attribute C_AXI_TYPE of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 1;
+  attribute C_BYTE_SIZE : integer;
+  attribute C_BYTE_SIZE of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 9;
+  attribute C_COMMON_CLK : integer;
+  attribute C_COMMON_CLK of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_COUNT_18K_BRAM : string;
+  attribute C_COUNT_18K_BRAM of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "1";
+  attribute C_COUNT_36K_BRAM : string;
+  attribute C_COUNT_36K_BRAM of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "0";
+  attribute C_CTRL_ECC_ALGO : string;
+  attribute C_CTRL_ECC_ALGO of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "NONE";
+  attribute C_DEFAULT_DATA : string;
+  attribute C_DEFAULT_DATA of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "0";
+  attribute C_DISABLE_WARN_BHV_COLL : integer;
+  attribute C_DISABLE_WARN_BHV_COLL of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_DISABLE_WARN_BHV_RANGE : integer;
+  attribute C_DISABLE_WARN_BHV_RANGE of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_ELABORATION_DIR : string;
+  attribute C_ELABORATION_DIR of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "./";
+  attribute C_ENABLE_32BIT_ADDRESS : integer;
+  attribute C_ENABLE_32BIT_ADDRESS of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_EN_DEEPSLEEP_PIN : integer;
+  attribute C_EN_DEEPSLEEP_PIN of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_EN_ECC_PIPE : integer;
+  attribute C_EN_ECC_PIPE of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_EN_RDADDRA_CHG : integer;
+  attribute C_EN_RDADDRA_CHG of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_EN_RDADDRB_CHG : integer;
+  attribute C_EN_RDADDRB_CHG of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_EN_SAFETY_CKT : integer;
+  attribute C_EN_SAFETY_CKT of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_EN_SHUTDOWN_PIN : integer;
+  attribute C_EN_SHUTDOWN_PIN of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_EN_SLEEP_PIN : integer;
+  attribute C_EN_SLEEP_PIN of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_EST_POWER_SUMMARY : string;
+  attribute C_EST_POWER_SUMMARY of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "Estimated Power for IP     :     2.5432 mW";
+  attribute C_FAMILY : string;
+  attribute C_FAMILY of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "artix7";
+  attribute C_HAS_AXI_ID : integer;
+  attribute C_HAS_AXI_ID of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_HAS_ENA : integer;
+  attribute C_HAS_ENA of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 1;
+  attribute C_HAS_ENB : integer;
+  attribute C_HAS_ENB of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_HAS_INJECTERR : integer;
+  attribute C_HAS_INJECTERR of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
+  attribute C_HAS_MEM_OUTPUT_REGS_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 1;
+  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
+  attribute C_HAS_MEM_OUTPUT_REGS_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
+  attribute C_HAS_MUX_OUTPUT_REGS_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
+  attribute C_HAS_MUX_OUTPUT_REGS_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_HAS_REGCEA : integer;
+  attribute C_HAS_REGCEA of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_HAS_REGCEB : integer;
+  attribute C_HAS_REGCEB of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_HAS_RSTA : integer;
+  attribute C_HAS_RSTA of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_HAS_RSTB : integer;
+  attribute C_HAS_RSTB of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
+  attribute C_HAS_SOFTECC_INPUT_REGS_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
+  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_INITA_VAL : string;
+  attribute C_INITA_VAL of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "0";
+  attribute C_INITB_VAL : string;
+  attribute C_INITB_VAL of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "0";
+  attribute C_INIT_FILE : string;
+  attribute C_INIT_FILE of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "lightning_20_20.mem";
+  attribute C_INIT_FILE_NAME : string;
+  attribute C_INIT_FILE_NAME of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "lightning_20_20.mif";
+  attribute C_INTERFACE_TYPE : integer;
+  attribute C_INTERFACE_TYPE of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_LOAD_INIT_FILE : integer;
+  attribute C_LOAD_INIT_FILE of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 1;
+  attribute C_MEM_TYPE : integer;
+  attribute C_MEM_TYPE of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 3;
+  attribute C_MUX_PIPELINE_STAGES : integer;
+  attribute C_MUX_PIPELINE_STAGES of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_PRIM_TYPE : integer;
+  attribute C_PRIM_TYPE of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 1;
+  attribute C_READ_DEPTH_A : integer;
+  attribute C_READ_DEPTH_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 400;
+  attribute C_READ_DEPTH_B : integer;
+  attribute C_READ_DEPTH_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 400;
+  attribute C_READ_LATENCY_A : integer;
+  attribute C_READ_LATENCY_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 1;
+  attribute C_READ_LATENCY_B : integer;
+  attribute C_READ_LATENCY_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 1;
+  attribute C_READ_WIDTH_A : integer;
+  attribute C_READ_WIDTH_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 12;
+  attribute C_READ_WIDTH_B : integer;
+  attribute C_READ_WIDTH_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 12;
+  attribute C_RSTRAM_A : integer;
+  attribute C_RSTRAM_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_RSTRAM_B : integer;
+  attribute C_RSTRAM_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_RST_PRIORITY_A : string;
+  attribute C_RST_PRIORITY_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "CE";
+  attribute C_RST_PRIORITY_B : string;
+  attribute C_RST_PRIORITY_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "CE";
+  attribute C_SIM_COLLISION_CHECK : string;
+  attribute C_SIM_COLLISION_CHECK of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "ALL";
+  attribute C_USE_BRAM_BLOCK : integer;
+  attribute C_USE_BRAM_BLOCK of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_USE_BYTE_WEA : integer;
+  attribute C_USE_BYTE_WEA of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_USE_BYTE_WEB : integer;
+  attribute C_USE_BYTE_WEB of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_USE_DEFAULT_DATA : integer;
+  attribute C_USE_DEFAULT_DATA of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_USE_ECC : integer;
+  attribute C_USE_ECC of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_USE_SOFTECC : integer;
+  attribute C_USE_SOFTECC of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_USE_URAM : integer;
+  attribute C_USE_URAM of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
+  attribute C_WEA_WIDTH : integer;
+  attribute C_WEA_WIDTH of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 1;
+  attribute C_WEB_WIDTH : integer;
+  attribute C_WEB_WIDTH of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 1;
+  attribute C_WRITE_DEPTH_A : integer;
+  attribute C_WRITE_DEPTH_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 400;
+  attribute C_WRITE_DEPTH_B : integer;
+  attribute C_WRITE_DEPTH_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 400;
+  attribute C_WRITE_MODE_A : string;
+  attribute C_WRITE_MODE_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "WRITE_FIRST";
+  attribute C_WRITE_MODE_B : string;
+  attribute C_WRITE_MODE_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "WRITE_FIRST";
+  attribute C_WRITE_WIDTH_A : integer;
+  attribute C_WRITE_WIDTH_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 12;
+  attribute C_WRITE_WIDTH_B : integer;
+  attribute C_WRITE_WIDTH_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 12;
+  attribute C_XDEVICEFAMILY : string;
+  attribute C_XDEVICEFAMILY of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "artix7";
+  attribute ORIG_REF_NAME : string;
+  attribute ORIG_REF_NAME of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
+  attribute downgradeipidentifiedwarnings : string;
+  attribute downgradeipidentifiedwarnings of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "yes";
+end lightning_20_20_blk_mem_gen_v8_4_4;
+
+architecture STRUCTURE of lightning_20_20_blk_mem_gen_v8_4_4 is
+  signal \<const0>\ : STD_LOGIC;
+begin
+  dbiterr <= \<const0>\;
+  doutb(11) <= \<const0>\;
+  doutb(10) <= \<const0>\;
+  doutb(9) <= \<const0>\;
+  doutb(8) <= \<const0>\;
+  doutb(7) <= \<const0>\;
+  doutb(6) <= \<const0>\;
+  doutb(5) <= \<const0>\;
+  doutb(4) <= \<const0>\;
+  doutb(3) <= \<const0>\;
+  doutb(2) <= \<const0>\;
+  doutb(1) <= \<const0>\;
+  doutb(0) <= \<const0>\;
+  rdaddrecc(8) <= \<const0>\;
+  rdaddrecc(7) <= \<const0>\;
+  rdaddrecc(6) <= \<const0>\;
+  rdaddrecc(5) <= \<const0>\;
+  rdaddrecc(4) <= \<const0>\;
+  rdaddrecc(3) <= \<const0>\;
+  rdaddrecc(2) <= \<const0>\;
+  rdaddrecc(1) <= \<const0>\;
+  rdaddrecc(0) <= \<const0>\;
+  rsta_busy <= \<const0>\;
+  rstb_busy <= \<const0>\;
+  s_axi_arready <= \<const0>\;
+  s_axi_awready <= \<const0>\;
+  s_axi_bid(3) <= \<const0>\;
+  s_axi_bid(2) <= \<const0>\;
+  s_axi_bid(1) <= \<const0>\;
+  s_axi_bid(0) <= \<const0>\;
+  s_axi_bresp(1) <= \<const0>\;
+  s_axi_bresp(0) <= \<const0>\;
+  s_axi_bvalid <= \<const0>\;
+  s_axi_dbiterr <= \<const0>\;
+  s_axi_rdaddrecc(8) <= \<const0>\;
+  s_axi_rdaddrecc(7) <= \<const0>\;
+  s_axi_rdaddrecc(6) <= \<const0>\;
+  s_axi_rdaddrecc(5) <= \<const0>\;
+  s_axi_rdaddrecc(4) <= \<const0>\;
+  s_axi_rdaddrecc(3) <= \<const0>\;
+  s_axi_rdaddrecc(2) <= \<const0>\;
+  s_axi_rdaddrecc(1) <= \<const0>\;
+  s_axi_rdaddrecc(0) <= \<const0>\;
+  s_axi_rdata(11) <= \<const0>\;
+  s_axi_rdata(10) <= \<const0>\;
+  s_axi_rdata(9) <= \<const0>\;
+  s_axi_rdata(8) <= \<const0>\;
+  s_axi_rdata(7) <= \<const0>\;
+  s_axi_rdata(6) <= \<const0>\;
+  s_axi_rdata(5) <= \<const0>\;
+  s_axi_rdata(4) <= \<const0>\;
+  s_axi_rdata(3) <= \<const0>\;
+  s_axi_rdata(2) <= \<const0>\;
+  s_axi_rdata(1) <= \<const0>\;
+  s_axi_rdata(0) <= \<const0>\;
+  s_axi_rid(3) <= \<const0>\;
+  s_axi_rid(2) <= \<const0>\;
+  s_axi_rid(1) <= \<const0>\;
+  s_axi_rid(0) <= \<const0>\;
+  s_axi_rlast <= \<const0>\;
+  s_axi_rresp(1) <= \<const0>\;
+  s_axi_rresp(0) <= \<const0>\;
+  s_axi_rvalid <= \<const0>\;
+  s_axi_sbiterr <= \<const0>\;
+  s_axi_wready <= \<const0>\;
+  sbiterr <= \<const0>\;
+GND: unisim.vcomponents.GND
+     port map (
+      G => \<const0>\
+    );
+inst_blk_mem_gen: entity work.lightning_20_20_blk_mem_gen_v8_4_4_synth
+     port map (
+      addra(8 downto 0) => addra(8 downto 0),
+      clka => clka,
+      douta(11 downto 0) => douta(11 downto 0),
+      ena => ena
+    );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity lightning_20_20 is
+  port (
+    clka : in STD_LOGIC;
+    ena : in STD_LOGIC;
+    addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
+  );
+  attribute NotValidForBitStream : boolean;
+  attribute NotValidForBitStream of lightning_20_20 : entity is true;
+  attribute CHECK_LICENSE_TYPE : string;
+  attribute CHECK_LICENSE_TYPE of lightning_20_20 : entity is "lightning_20_20,blk_mem_gen_v8_4_4,{}";
+  attribute downgradeipidentifiedwarnings : string;
+  attribute downgradeipidentifiedwarnings of lightning_20_20 : entity is "yes";
+  attribute x_core_info : string;
+  attribute x_core_info of lightning_20_20 : entity is "blk_mem_gen_v8_4_4,Vivado 2019.2";
+end lightning_20_20;
+
+architecture STRUCTURE of lightning_20_20 is
+  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
+  signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
+  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
+  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
+  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
+  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
+  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
+  attribute C_ADDRA_WIDTH : integer;
+  attribute C_ADDRA_WIDTH of U0 : label is 9;
+  attribute C_ADDRB_WIDTH : integer;
+  attribute C_ADDRB_WIDTH of U0 : label is 9;
+  attribute C_ALGORITHM : integer;
+  attribute C_ALGORITHM of U0 : label is 1;
+  attribute C_AXI_ID_WIDTH : integer;
+  attribute C_AXI_ID_WIDTH of U0 : label is 4;
+  attribute C_AXI_SLAVE_TYPE : integer;
+  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
+  attribute C_AXI_TYPE : integer;
+  attribute C_AXI_TYPE of U0 : label is 1;
+  attribute C_BYTE_SIZE : integer;
+  attribute C_BYTE_SIZE of U0 : label is 9;
+  attribute C_COMMON_CLK : integer;
+  attribute C_COMMON_CLK of U0 : label is 0;
+  attribute C_COUNT_18K_BRAM : string;
+  attribute C_COUNT_18K_BRAM of U0 : label is "1";
+  attribute C_COUNT_36K_BRAM : string;
+  attribute C_COUNT_36K_BRAM of U0 : label is "0";
+  attribute C_CTRL_ECC_ALGO : string;
+  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
+  attribute C_DEFAULT_DATA : string;
+  attribute C_DEFAULT_DATA of U0 : label is "0";
+  attribute C_DISABLE_WARN_BHV_COLL : integer;
+  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
+  attribute C_DISABLE_WARN_BHV_RANGE : integer;
+  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
+  attribute C_ELABORATION_DIR : string;
+  attribute C_ELABORATION_DIR of U0 : label is "./";
+  attribute C_ENABLE_32BIT_ADDRESS : integer;
+  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
+  attribute C_EN_DEEPSLEEP_PIN : integer;
+  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
+  attribute C_EN_ECC_PIPE : integer;
+  attribute C_EN_ECC_PIPE of U0 : label is 0;
+  attribute C_EN_RDADDRA_CHG : integer;
+  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
+  attribute C_EN_RDADDRB_CHG : integer;
+  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
+  attribute C_EN_SAFETY_CKT : integer;
+  attribute C_EN_SAFETY_CKT of U0 : label is 0;
+  attribute C_EN_SHUTDOWN_PIN : integer;
+  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
+  attribute C_EN_SLEEP_PIN : integer;
+  attribute C_EN_SLEEP_PIN of U0 : label is 0;
+  attribute C_EST_POWER_SUMMARY : string;
+  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     2.5432 mW";
+  attribute C_FAMILY : string;
+  attribute C_FAMILY of U0 : label is "artix7";
+  attribute C_HAS_AXI_ID : integer;
+  attribute C_HAS_AXI_ID of U0 : label is 0;
+  attribute C_HAS_ENA : integer;
+  attribute C_HAS_ENA of U0 : label is 1;
+  attribute C_HAS_ENB : integer;
+  attribute C_HAS_ENB of U0 : label is 0;
+  attribute C_HAS_INJECTERR : integer;
+  attribute C_HAS_INJECTERR of U0 : label is 0;
+  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
+  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
+  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
+  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
+  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
+  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
+  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
+  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
+  attribute C_HAS_REGCEA : integer;
+  attribute C_HAS_REGCEA of U0 : label is 0;
+  attribute C_HAS_REGCEB : integer;
+  attribute C_HAS_REGCEB of U0 : label is 0;
+  attribute C_HAS_RSTA : integer;
+  attribute C_HAS_RSTA of U0 : label is 0;
+  attribute C_HAS_RSTB : integer;
+  attribute C_HAS_RSTB of U0 : label is 0;
+  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
+  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
+  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
+  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
+  attribute C_INITA_VAL : string;
+  attribute C_INITA_VAL of U0 : label is "0";
+  attribute C_INITB_VAL : string;
+  attribute C_INITB_VAL of U0 : label is "0";
+  attribute C_INIT_FILE : string;
+  attribute C_INIT_FILE of U0 : label is "lightning_20_20.mem";
+  attribute C_INIT_FILE_NAME : string;
+  attribute C_INIT_FILE_NAME of U0 : label is "lightning_20_20.mif";
+  attribute C_INTERFACE_TYPE : integer;
+  attribute C_INTERFACE_TYPE of U0 : label is 0;
+  attribute C_LOAD_INIT_FILE : integer;
+  attribute C_LOAD_INIT_FILE of U0 : label is 1;
+  attribute C_MEM_TYPE : integer;
+  attribute C_MEM_TYPE of U0 : label is 3;
+  attribute C_MUX_PIPELINE_STAGES : integer;
+  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
+  attribute C_PRIM_TYPE : integer;
+  attribute C_PRIM_TYPE of U0 : label is 1;
+  attribute C_READ_DEPTH_A : integer;
+  attribute C_READ_DEPTH_A of U0 : label is 400;
+  attribute C_READ_DEPTH_B : integer;
+  attribute C_READ_DEPTH_B of U0 : label is 400;
+  attribute C_READ_LATENCY_A : integer;
+  attribute C_READ_LATENCY_A of U0 : label is 1;
+  attribute C_READ_LATENCY_B : integer;
+  attribute C_READ_LATENCY_B of U0 : label is 1;
+  attribute C_READ_WIDTH_A : integer;
+  attribute C_READ_WIDTH_A of U0 : label is 12;
+  attribute C_READ_WIDTH_B : integer;
+  attribute C_READ_WIDTH_B of U0 : label is 12;
+  attribute C_RSTRAM_A : integer;
+  attribute C_RSTRAM_A of U0 : label is 0;
+  attribute C_RSTRAM_B : integer;
+  attribute C_RSTRAM_B of U0 : label is 0;
+  attribute C_RST_PRIORITY_A : string;
+  attribute C_RST_PRIORITY_A of U0 : label is "CE";
+  attribute C_RST_PRIORITY_B : string;
+  attribute C_RST_PRIORITY_B of U0 : label is "CE";
+  attribute C_SIM_COLLISION_CHECK : string;
+  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
+  attribute C_USE_BRAM_BLOCK : integer;
+  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
+  attribute C_USE_BYTE_WEA : integer;
+  attribute C_USE_BYTE_WEA of U0 : label is 0;
+  attribute C_USE_BYTE_WEB : integer;
+  attribute C_USE_BYTE_WEB of U0 : label is 0;
+  attribute C_USE_DEFAULT_DATA : integer;
+  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
+  attribute C_USE_ECC : integer;
+  attribute C_USE_ECC of U0 : label is 0;
+  attribute C_USE_SOFTECC : integer;
+  attribute C_USE_SOFTECC of U0 : label is 0;
+  attribute C_USE_URAM : integer;
+  attribute C_USE_URAM of U0 : label is 0;
+  attribute C_WEA_WIDTH : integer;
+  attribute C_WEA_WIDTH of U0 : label is 1;
+  attribute C_WEB_WIDTH : integer;
+  attribute C_WEB_WIDTH of U0 : label is 1;
+  attribute C_WRITE_DEPTH_A : integer;
+  attribute C_WRITE_DEPTH_A of U0 : label is 400;
+  attribute C_WRITE_DEPTH_B : integer;
+  attribute C_WRITE_DEPTH_B of U0 : label is 400;
+  attribute C_WRITE_MODE_A : string;
+  attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
+  attribute C_WRITE_MODE_B : string;
+  attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
+  attribute C_WRITE_WIDTH_A : integer;
+  attribute C_WRITE_WIDTH_A of U0 : label is 12;
+  attribute C_WRITE_WIDTH_B : integer;
+  attribute C_WRITE_WIDTH_B of U0 : label is 12;
+  attribute C_XDEVICEFAMILY : string;
+  attribute C_XDEVICEFAMILY of U0 : label is "artix7";
+  attribute downgradeipidentifiedwarnings of U0 : label is "yes";
+  attribute x_interface_info : string;
+  attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
+  attribute x_interface_parameter : string;
+  attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
+  attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
+  attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
+  attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
+begin
+U0: entity work.lightning_20_20_blk_mem_gen_v8_4_4
+     port map (
+      addra(8 downto 0) => addra(8 downto 0),
+      addrb(8 downto 0) => B"000000000",
+      clka => clka,
+      clkb => '0',
+      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
+      deepsleep => '0',
+      dina(11 downto 0) => B"000000000000",
+      dinb(11 downto 0) => B"000000000000",
+      douta(11 downto 0) => douta(11 downto 0),
+      doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
+      eccpipece => '0',
+      ena => ena,
+      enb => '0',
+      injectdbiterr => '0',
+      injectsbiterr => '0',
+      rdaddrecc(8 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(8 downto 0),
+      regcea => '0',
+      regceb => '0',
+      rsta => '0',
+      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
+      rstb => '0',
+      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
+      s_aclk => '0',
+      s_aresetn => '0',
+      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
+      s_axi_arburst(1 downto 0) => B"00",
+      s_axi_arid(3 downto 0) => B"0000",
+      s_axi_arlen(7 downto 0) => B"00000000",
+      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
+      s_axi_arsize(2 downto 0) => B"000",
+      s_axi_arvalid => '0',
+      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
+      s_axi_awburst(1 downto 0) => B"00",
+      s_axi_awid(3 downto 0) => B"0000",
+      s_axi_awlen(7 downto 0) => B"00000000",
+      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
+      s_axi_awsize(2 downto 0) => B"000",
+      s_axi_awvalid => '0',
+      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
+      s_axi_bready => '0',
+      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
+      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
+      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
+      s_axi_injectdbiterr => '0',
+      s_axi_injectsbiterr => '0',
+      s_axi_rdaddrecc(8 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(8 downto 0),
+      s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
+      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
+      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
+      s_axi_rready => '0',
+      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
+      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
+      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
+      s_axi_wdata(11 downto 0) => B"000000000000",
+      s_axi_wlast => '0',
+      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
+      s_axi_wstrb(0) => '0',
+      s_axi_wvalid => '0',
+      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
+      shutdown => '0',
+      sleep => '0',
+      wea(0) => '0',
+      web(0) => '0'
+    );
+end STRUCTURE;

TankGame.srcs/sources_1/ip/lightning_20_20/misc/blk_mem_gen_v8_4.vhd

@@ -0,0 +1,150 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity blk_mem_gen_v8_4_4 is
+  generic (
+    C_FAMILY                     : string := "virtex7";
+    C_XDEVICEFAMILY              : string := "virtex7";
+    C_ELABORATION_DIR            : string := "";
+    C_INTERFACE_TYPE             : integer := 0;
+    C_AXI_TYPE                   : integer := 1;
+    C_AXI_SLAVE_TYPE             : integer := 0;
+    C_USE_BRAM_BLOCK             : integer := 0;
+    C_ENABLE_32BIT_ADDRESS       : integer := 0;
+    C_CTRL_ECC_ALGO              : string := "ECCHSIAO32-7";
+    C_HAS_AXI_ID                 : integer := 0;
+    C_AXI_ID_WIDTH               : integer := 4;
+    C_MEM_TYPE                   : integer := 2;
+    C_BYTE_SIZE                  : integer := 9;
+    C_ALGORITHM                  : integer := 0;
+    C_PRIM_TYPE                  : integer := 3;
+    C_LOAD_INIT_FILE             : integer := 0;
+    C_INIT_FILE_NAME             : string := "no_coe_file_loaded";
+    C_INIT_FILE                  : string := "no_mem_file_loaded";
+    C_USE_DEFAULT_DATA           : integer := 0;
+    C_DEFAULT_DATA               : string := "0";
+    C_HAS_RSTA                   : integer := 0;
+    C_RST_PRIORITY_A             : string := "ce";
+    C_RSTRAM_A                   : integer := 0;
+    C_INITA_VAL                  : string := "0";
+    C_HAS_ENA                    : integer := 1;
+    C_HAS_REGCEA                 : integer := 0;
+    C_USE_BYTE_WEA               : integer := 0;
+    C_WEA_WIDTH                  : integer := 1;
+    C_WRITE_MODE_A               : string := "WRITE_FIRST";
+    C_WRITE_WIDTH_A              : integer := 9;
+    C_READ_WIDTH_A               : integer := 9;
+    C_WRITE_DEPTH_A              : integer := 2048;
+    C_READ_DEPTH_A               : integer := 2048;
+    C_ADDRA_WIDTH                : integer := 11;
+    C_HAS_RSTB                   : integer := 0;
+    C_RST_PRIORITY_B             : string := "ce";
+    C_RSTRAM_B                   : integer := 0;
+    C_INITB_VAL                  : string := "0";
+    C_HAS_ENB                    : integer := 1;
+    C_HAS_REGCEB                 : integer := 0;
+    C_USE_BYTE_WEB               : integer := 0;
+    C_WEB_WIDTH                  : integer := 1;
+    C_WRITE_MODE_B               : string := "WRITE_FIRST";
+    C_WRITE_WIDTH_B              : integer := 9;
+    C_READ_WIDTH_B               : integer := 9;
+    C_WRITE_DEPTH_B              : integer := 2048;
+    C_READ_DEPTH_B               : integer := 2048;
+    C_ADDRB_WIDTH                : integer := 11;
+    C_HAS_MEM_OUTPUT_REGS_A      : integer := 0;
+    C_HAS_MEM_OUTPUT_REGS_B      : integer := 0;
+    C_HAS_MUX_OUTPUT_REGS_A      : integer := 0;
+    C_HAS_MUX_OUTPUT_REGS_B      : integer := 0;
+    C_MUX_PIPELINE_STAGES        : integer := 0;
+    C_HAS_SOFTECC_INPUT_REGS_A   : integer := 0;
+    C_HAS_SOFTECC_OUTPUT_REGS_B  : integer := 0;
+    C_USE_SOFTECC                : integer := 0;
+    C_USE_ECC                    : integer := 0;
+    C_EN_ECC_PIPE                : integer := 0;
+    C_HAS_INJECTERR              : integer := 0;
+    C_SIM_COLLISION_CHECK        : string := "none";
+    C_COMMON_CLK                 : integer := 0;
+    C_DISABLE_WARN_BHV_COLL      : integer := 0;
+    C_EN_SLEEP_PIN               : integer := 0;
+    C_USE_URAM                   : integer := 0;
+    C_EN_RDADDRA_CHG             : integer := 0;
+    C_EN_RDADDRB_CHG             : integer := 0;
+    C_EN_DEEPSLEEP_PIN           : integer := 0;
+    C_EN_SHUTDOWN_PIN            : integer := 0;
+    C_EN_SAFETY_CKT              : integer := 0;
+    C_DISABLE_WARN_BHV_RANGE     : integer := 0;
+    C_COUNT_36K_BRAM             : string  := "";
+    C_COUNT_18K_BRAM             : string  := "";
+    C_EST_POWER_SUMMARY          : string  := ""
+  );
+  port (
+    clka                         : in std_logic := '0';
+    rsta                         : in std_logic := '0';
+    ena                          : in std_logic := '0';
+    regcea                       : in std_logic := '0';
+    wea                          : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
+    addra                        : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
+    dina                         : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
+    douta                        : out std_logic_vector(c_read_width_a - 1 downto 0);
+    clkb                         : in std_logic := '0';
+    rstb                         : in std_logic := '0';
+    enb                          : in std_logic := '0';
+    regceb                       : in std_logic := '0';
+    web                          : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
+    addrb                        : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
+    dinb                         : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
+    doutb                        : out std_logic_vector(c_read_width_b - 1 downto 0);
+    injectsbiterr                : in std_logic := '0';
+    injectdbiterr                : in std_logic := '0';
+    eccpipece                    : in std_logic := '0';
+    sbiterr                      : out std_logic;
+    dbiterr                      : out std_logic;
+    rdaddrecc                    : out std_logic_vector(c_addrb_width - 1 downto 0);
+    sleep                        : in std_logic := '0';
+    deepsleep                    : in std_logic := '0';
+    shutdown                     : in std_logic := '0';
+    rsta_busy                    : out std_logic;
+    rstb_busy                    : out std_logic;
+    s_aclk                       : in std_logic := '0';
+    s_aresetn                    : in std_logic := '0';
+    s_axi_awid                   : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
+    s_axi_awaddr                 : in std_logic_vector(31 downto 0) := (others => '0');
+    s_axi_awlen                  : in std_logic_vector(7 downto 0) := (others => '0');
+    s_axi_awsize                 : in std_logic_vector(2 downto 0) := (others => '0');
+    s_axi_awburst                : in std_logic_vector(1 downto 0) := (others => '0');
+    s_axi_awvalid                : in std_logic := '0';
+    s_axi_awready                : out std_logic;
+    s_axi_wdata                  : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
+    s_axi_wstrb                  : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
+    s_axi_wlast                  : in std_logic := '0';
+    s_axi_wvalid                 : in std_logic := '0';
+    s_axi_wready                 : out std_logic;
+    s_axi_bid                    : out std_logic_vector(c_axi_id_width - 1 downto 0);
+    s_axi_bresp                  : out std_logic_vector(1 downto 0);
+    s_axi_bvalid                 : out std_logic;
+    s_axi_bready                 : in std_logic := '0';
+    s_axi_arid                   : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
+    s_axi_araddr                 : in std_logic_vector(31 downto 0) := (others => '0');
+    s_axi_arlen                  : in std_logic_vector(8 - 1 downto 0) := (others => '0');
+    s_axi_arsize                 : in std_logic_vector(2 downto 0) := (others => '0');
+    s_axi_arburst                : in std_logic_vector(1 downto 0) := (others => '0');
+    s_axi_arvalid                : in std_logic := '0';
+    s_axi_arready                : out std_logic;
+    s_axi_rid                    : out std_logic_vector(c_axi_id_width - 1 downto 0);
+    s_axi_rdata                  : out std_logic_vector(c_write_width_b - 1 downto 0);
+    s_axi_rresp                  : out std_logic_vector(2 - 1 downto 0);
+    s_axi_rlast                  : out std_logic;
+    s_axi_rvalid                 : out std_logic;
+    s_axi_rready                 : in std_logic := '0';
+    s_axi_injectsbiterr          : in std_logic := '0';
+    s_axi_injectdbiterr          : in std_logic := '0';
+    s_axi_sbiterr                : out std_logic;
+    s_axi_dbiterr                : out std_logic;
+    s_axi_rdaddrecc              : out std_logic_vector(c_addrb_width - 1 downto 0)
+  );
+end entity blk_mem_gen_v8_4_4;
+
+architecture xilinx of blk_mem_gen_v8_4_4 is
+  begin
+  end 
+architecture xilinx;

TankGame.srcs/sources_1/ip/lightning_20_20/sim/lightning_20_20.v

@@ -0,0 +1,214 @@
+// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+// IP Revision: 4
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module lightning_20_20 (
+  clka,
+  ena,
+  addra,
+  douta
+);
+
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
+input wire clka;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
+input wire ena;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
+input wire [8 : 0] addra;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
+output wire [11 : 0] douta;
+
+  blk_mem_gen_v8_4_4 #(
+    .C_FAMILY("artix7"),
+    .C_XDEVICEFAMILY("artix7"),
+    .C_ELABORATION_DIR("./"),
+    .C_INTERFACE_TYPE(0),
+    .C_AXI_TYPE(1),
+    .C_AXI_SLAVE_TYPE(0),
+    .C_USE_BRAM_BLOCK(0),
+    .C_ENABLE_32BIT_ADDRESS(0),
+    .C_CTRL_ECC_ALGO("NONE"),
+    .C_HAS_AXI_ID(0),
+    .C_AXI_ID_WIDTH(4),
+    .C_MEM_TYPE(3),
+    .C_BYTE_SIZE(9),
+    .C_ALGORITHM(1),
+    .C_PRIM_TYPE(1),
+    .C_LOAD_INIT_FILE(1),
+    .C_INIT_FILE_NAME("lightning_20_20.mif"),
+    .C_INIT_FILE("lightning_20_20.mem"),
+    .C_USE_DEFAULT_DATA(0),
+    .C_DEFAULT_DATA("0"),
+    .C_HAS_RSTA(0),
+    .C_RST_PRIORITY_A("CE"),
+    .C_RSTRAM_A(0),
+    .C_INITA_VAL("0"),
+    .C_HAS_ENA(1),
+    .C_HAS_REGCEA(0),
+    .C_USE_BYTE_WEA(0),
+    .C_WEA_WIDTH(1),
+    .C_WRITE_MODE_A("WRITE_FIRST"),
+    .C_WRITE_WIDTH_A(12),
+    .C_READ_WIDTH_A(12),
+    .C_WRITE_DEPTH_A(400),
+    .C_READ_DEPTH_A(400),
+    .C_ADDRA_WIDTH(9),
+    .C_HAS_RSTB(0),
+    .C_RST_PRIORITY_B("CE"),
+    .C_RSTRAM_B(0),
+    .C_INITB_VAL("0"),
+    .C_HAS_ENB(0),
+    .C_HAS_REGCEB(0),
+    .C_USE_BYTE_WEB(0),
+    .C_WEB_WIDTH(1),
+    .C_WRITE_MODE_B("WRITE_FIRST"),
+    .C_WRITE_WIDTH_B(12),
+    .C_READ_WIDTH_B(12),
+    .C_WRITE_DEPTH_B(400),
+    .C_READ_DEPTH_B(400),
+    .C_ADDRB_WIDTH(9),
+    .C_HAS_MEM_OUTPUT_REGS_A(1),
+    .C_HAS_MEM_OUTPUT_REGS_B(0),
+    .C_HAS_MUX_OUTPUT_REGS_A(0),
+    .C_HAS_MUX_OUTPUT_REGS_B(0),
+    .C_MUX_PIPELINE_STAGES(0),
+    .C_HAS_SOFTECC_INPUT_REGS_A(0),
+    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
+    .C_USE_SOFTECC(0),
+    .C_USE_ECC(0),
+    .C_EN_ECC_PIPE(0),
+    .C_READ_LATENCY_A(1),
+    .C_READ_LATENCY_B(1),
+    .C_HAS_INJECTERR(0),
+    .C_SIM_COLLISION_CHECK("ALL"),
+    .C_COMMON_CLK(0),
+    .C_DISABLE_WARN_BHV_COLL(0),
+    .C_EN_SLEEP_PIN(0),
+    .C_USE_URAM(0),
+    .C_EN_RDADDRA_CHG(0),
+    .C_EN_RDADDRB_CHG(0),
+    .C_EN_DEEPSLEEP_PIN(0),
+    .C_EN_SHUTDOWN_PIN(0),
+    .C_EN_SAFETY_CKT(0),
+    .C_DISABLE_WARN_BHV_RANGE(0),
+    .C_COUNT_36K_BRAM("0"),
+    .C_COUNT_18K_BRAM("1"),
+    .C_EST_POWER_SUMMARY("Estimated Power for IP     :     2.5432 mW")
+  ) inst (
+    .clka(clka),
+    .rsta(1'D0),
+    .ena(ena),
+    .regcea(1'D0),
+    .wea(1'B0),
+    .addra(addra),
+    .dina(12'B0),
+    .douta(douta),
+    .clkb(1'D0),
+    .rstb(1'D0),
+    .enb(1'D0),
+    .regceb(1'D0),
+    .web(1'B0),
+    .addrb(9'B0),
+    .dinb(12'B0),
+    .doutb(),
+    .injectsbiterr(1'D0),
+    .injectdbiterr(1'D0),
+    .eccpipece(1'D0),
+    .sbiterr(),
+    .dbiterr(),
+    .rdaddrecc(),
+    .sleep(1'D0),
+    .deepsleep(1'D0),
+    .shutdown(1'D0),
+    .rsta_busy(),
+    .rstb_busy(),
+    .s_aclk(1'H0),
+    .s_aresetn(1'D0),
+    .s_axi_awid(4'B0),
+    .s_axi_awaddr(32'B0),
+    .s_axi_awlen(8'B0),
+    .s_axi_awsize(3'B0),
+    .s_axi_awburst(2'B0),
+    .s_axi_awvalid(1'D0),
+    .s_axi_awready(),
+    .s_axi_wdata(12'B0),
+    .s_axi_wstrb(1'B0),
+    .s_axi_wlast(1'D0),
+    .s_axi_wvalid(1'D0),
+    .s_axi_wready(),
+    .s_axi_bid(),
+    .s_axi_bresp(),
+    .s_axi_bvalid(),
+    .s_axi_bready(1'D0),
+    .s_axi_arid(4'B0),
+    .s_axi_araddr(32'B0),
+    .s_axi_arlen(8'B0),
+    .s_axi_arsize(3'B0),
+    .s_axi_arburst(2'B0),
+    .s_axi_arvalid(1'D0),
+    .s_axi_arready(),
+    .s_axi_rid(),
+    .s_axi_rdata(),
+    .s_axi_rresp(),
+    .s_axi_rlast(),
+    .s_axi_rvalid(),
+    .s_axi_rready(1'D0),
+    .s_axi_injectsbiterr(1'D0),
+    .s_axi_injectdbiterr(1'D0),
+    .s_axi_sbiterr(),
+    .s_axi_dbiterr(),
+    .s_axi_rdaddrecc()
+  );
+endmodule

TankGame.srcs/sources_1/ip/lightning_20_20/synth/lightning_20_20.vhd

@@ -0,0 +1,355 @@
+-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+-- IP Revision: 4
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY blk_mem_gen_v8_4_4;
+USE blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4;
+
+ENTITY lightning_20_20 IS
+  PORT (
+    clka : IN STD_LOGIC;
+    ena : IN STD_LOGIC;
+    addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
+  );
+END lightning_20_20;
+
+ARCHITECTURE lightning_20_20_arch OF lightning_20_20 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF lightning_20_20_arch: ARCHITECTURE IS "yes";
+  COMPONENT blk_mem_gen_v8_4_4 IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_XDEVICEFAMILY : STRING;
+      C_ELABORATION_DIR : STRING;
+      C_INTERFACE_TYPE : INTEGER;
+      C_AXI_TYPE : INTEGER;
+      C_AXI_SLAVE_TYPE : INTEGER;
+      C_USE_BRAM_BLOCK : INTEGER;
+      C_ENABLE_32BIT_ADDRESS : INTEGER;
+      C_CTRL_ECC_ALGO : STRING;
+      C_HAS_AXI_ID : INTEGER;
+      C_AXI_ID_WIDTH : INTEGER;
+      C_MEM_TYPE : INTEGER;
+      C_BYTE_SIZE : INTEGER;
+      C_ALGORITHM : INTEGER;
+      C_PRIM_TYPE : INTEGER;
+      C_LOAD_INIT_FILE : INTEGER;
+      C_INIT_FILE_NAME : STRING;
+      C_INIT_FILE : STRING;
+      C_USE_DEFAULT_DATA : INTEGER;
+      C_DEFAULT_DATA : STRING;
+      C_HAS_RSTA : INTEGER;
+      C_RST_PRIORITY_A : STRING;
+      C_RSTRAM_A : INTEGER;
+      C_INITA_VAL : STRING;
+      C_HAS_ENA : INTEGER;
+      C_HAS_REGCEA : INTEGER;
+      C_USE_BYTE_WEA : INTEGER;
+      C_WEA_WIDTH : INTEGER;
+      C_WRITE_MODE_A : STRING;
+      C_WRITE_WIDTH_A : INTEGER;
+      C_READ_WIDTH_A : INTEGER;
+      C_WRITE_DEPTH_A : INTEGER;
+      C_READ_DEPTH_A : INTEGER;
+      C_ADDRA_WIDTH : INTEGER;
+      C_HAS_RSTB : INTEGER;
+      C_RST_PRIORITY_B : STRING;
+      C_RSTRAM_B : INTEGER;
+      C_INITB_VAL : STRING;
+      C_HAS_ENB : INTEGER;
+      C_HAS_REGCEB : INTEGER;
+      C_USE_BYTE_WEB : INTEGER;
+      C_WEB_WIDTH : INTEGER;
+      C_WRITE_MODE_B : STRING;
+      C_WRITE_WIDTH_B : INTEGER;
+      C_READ_WIDTH_B : INTEGER;
+      C_WRITE_DEPTH_B : INTEGER;
+      C_READ_DEPTH_B : INTEGER;
+      C_ADDRB_WIDTH : INTEGER;
+      C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
+      C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
+      C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
+      C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
+      C_MUX_PIPELINE_STAGES : INTEGER;
+      C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
+      C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
+      C_USE_SOFTECC : INTEGER;
+      C_USE_ECC : INTEGER;
+      C_EN_ECC_PIPE : INTEGER;
+      C_READ_LATENCY_A : INTEGER;
+      C_READ_LATENCY_B : INTEGER;
+      C_HAS_INJECTERR : INTEGER;
+      C_SIM_COLLISION_CHECK : STRING;
+      C_COMMON_CLK : INTEGER;
+      C_DISABLE_WARN_BHV_COLL : INTEGER;
+      C_EN_SLEEP_PIN : INTEGER;
+      C_USE_URAM : INTEGER;
+      C_EN_RDADDRA_CHG : INTEGER;
+      C_EN_RDADDRB_CHG : INTEGER;
+      C_EN_DEEPSLEEP_PIN : INTEGER;
+      C_EN_SHUTDOWN_PIN : INTEGER;
+      C_EN_SAFETY_CKT : INTEGER;
+      C_DISABLE_WARN_BHV_RANGE : INTEGER;
+      C_COUNT_36K_BRAM : STRING;
+      C_COUNT_18K_BRAM : STRING;
+      C_EST_POWER_SUMMARY : STRING
+    );
+    PORT (
+      clka : IN STD_LOGIC;
+      rsta : IN STD_LOGIC;
+      ena : IN STD_LOGIC;
+      regcea : IN STD_LOGIC;
+      wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+      douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+      clkb : IN STD_LOGIC;
+      rstb : IN STD_LOGIC;
+      enb : IN STD_LOGIC;
+      regceb : IN STD_LOGIC;
+      web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+      doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+      injectsbiterr : IN STD_LOGIC;
+      injectdbiterr : IN STD_LOGIC;
+      eccpipece : IN STD_LOGIC;
+      sbiterr : OUT STD_LOGIC;
+      dbiterr : OUT STD_LOGIC;
+      rdaddrecc : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
+      sleep : IN STD_LOGIC;
+      deepsleep : IN STD_LOGIC;
+      shutdown : IN STD_LOGIC;
+      rsta_busy : OUT STD_LOGIC;
+      rstb_busy : OUT STD_LOGIC;
+      s_aclk : IN STD_LOGIC;
+      s_aresetn : IN STD_LOGIC;
+      s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_awvalid : IN STD_LOGIC;
+      s_axi_awready : OUT STD_LOGIC;
+      s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+      s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axi_wlast : IN STD_LOGIC;
+      s_axi_wvalid : IN STD_LOGIC;
+      s_axi_wready : OUT STD_LOGIC;
+      s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_bvalid : OUT STD_LOGIC;
+      s_axi_bready : IN STD_LOGIC;
+      s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_arvalid : IN STD_LOGIC;
+      s_axi_arready : OUT STD_LOGIC;
+      s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_rlast : OUT STD_LOGIC;
+      s_axi_rvalid : OUT STD_LOGIC;
+      s_axi_rready : IN STD_LOGIC;
+      s_axi_injectsbiterr : IN STD_LOGIC;
+      s_axi_injectdbiterr : IN STD_LOGIC;
+      s_axi_sbiterr : OUT STD_LOGIC;
+      s_axi_dbiterr : OUT STD_LOGIC;
+      s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
+    );
+  END COMPONENT blk_mem_gen_v8_4_4;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF lightning_20_20_arch: ARCHITECTURE IS "blk_mem_gen_v8_4_4,Vivado 2019.2";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF lightning_20_20_arch : ARCHITECTURE IS "lightning_20_20,blk_mem_gen_v8_4_4,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF lightning_20_20_arch: ARCHITECTURE IS "lightning_20_20,blk_mem_gen_v8_4_4,{x_ipProduct=Vivado 2019.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.4,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=lig" & 
+"htning_20_20.mif,C_INIT_FILE=lightning_20_20.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=400,C_READ_DEPTH_A=400,C_ADDRA_WIDTH=9,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH" & 
+"_B=12,C_WRITE_DEPTH_B=400,C_READ_DEPTH_B=400,C_ADDRB_WIDTH=9,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_READ_LATENCY_A=1,C_READ_LATENCY_B=1,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PI" & 
+"N=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP     _     2.5432 mW}";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
+  ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clka: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
+  ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
+BEGIN
+  U0 : blk_mem_gen_v8_4_4
+    GENERIC MAP (
+      C_FAMILY => "artix7",
+      C_XDEVICEFAMILY => "artix7",
+      C_ELABORATION_DIR => "./",
+      C_INTERFACE_TYPE => 0,
+      C_AXI_TYPE => 1,
+      C_AXI_SLAVE_TYPE => 0,
+      C_USE_BRAM_BLOCK => 0,
+      C_ENABLE_32BIT_ADDRESS => 0,
+      C_CTRL_ECC_ALGO => "NONE",
+      C_HAS_AXI_ID => 0,
+      C_AXI_ID_WIDTH => 4,
+      C_MEM_TYPE => 3,
+      C_BYTE_SIZE => 9,
+      C_ALGORITHM => 1,
+      C_PRIM_TYPE => 1,
+      C_LOAD_INIT_FILE => 1,
+      C_INIT_FILE_NAME => "lightning_20_20.mif",
+      C_INIT_FILE => "lightning_20_20.mem",
+      C_USE_DEFAULT_DATA => 0,
+      C_DEFAULT_DATA => "0",
+      C_HAS_RSTA => 0,
+      C_RST_PRIORITY_A => "CE",
+      C_RSTRAM_A => 0,
+      C_INITA_VAL => "0",
+      C_HAS_ENA => 1,
+      C_HAS_REGCEA => 0,
+      C_USE_BYTE_WEA => 0,
+      C_WEA_WIDTH => 1,
+      C_WRITE_MODE_A => "WRITE_FIRST",
+      C_WRITE_WIDTH_A => 12,
+      C_READ_WIDTH_A => 12,
+      C_WRITE_DEPTH_A => 400,
+      C_READ_DEPTH_A => 400,
+      C_ADDRA_WIDTH => 9,
+      C_HAS_RSTB => 0,
+      C_RST_PRIORITY_B => "CE",
+      C_RSTRAM_B => 0,
+      C_INITB_VAL => "0",
+      C_HAS_ENB => 0,
+      C_HAS_REGCEB => 0,
+      C_USE_BYTE_WEB => 0,
+      C_WEB_WIDTH => 1,
+      C_WRITE_MODE_B => "WRITE_FIRST",
+      C_WRITE_WIDTH_B => 12,
+      C_READ_WIDTH_B => 12,
+      C_WRITE_DEPTH_B => 400,
+      C_READ_DEPTH_B => 400,
+      C_ADDRB_WIDTH => 9,
+      C_HAS_MEM_OUTPUT_REGS_A => 1,
+      C_HAS_MEM_OUTPUT_REGS_B => 0,
+      C_HAS_MUX_OUTPUT_REGS_A => 0,
+      C_HAS_MUX_OUTPUT_REGS_B => 0,
+      C_MUX_PIPELINE_STAGES => 0,
+      C_HAS_SOFTECC_INPUT_REGS_A => 0,
+      C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
+      C_USE_SOFTECC => 0,
+      C_USE_ECC => 0,
+      C_EN_ECC_PIPE => 0,
+      C_READ_LATENCY_A => 1,
+      C_READ_LATENCY_B => 1,
+      C_HAS_INJECTERR => 0,
+      C_SIM_COLLISION_CHECK => "ALL",
+      C_COMMON_CLK => 0,
+      C_DISABLE_WARN_BHV_COLL => 0,
+      C_EN_SLEEP_PIN => 0,
+      C_USE_URAM => 0,
+      C_EN_RDADDRA_CHG => 0,
+      C_EN_RDADDRB_CHG => 0,
+      C_EN_DEEPSLEEP_PIN => 0,
+      C_EN_SHUTDOWN_PIN => 0,
+      C_EN_SAFETY_CKT => 0,
+      C_DISABLE_WARN_BHV_RANGE => 0,
+      C_COUNT_36K_BRAM => "0",
+      C_COUNT_18K_BRAM => "1",
+      C_EST_POWER_SUMMARY => "Estimated Power for IP     :     2.5432 mW"
+    )
+    PORT MAP (
+      clka => clka,
+      rsta => '0',
+      ena => ena,
+      regcea => '0',
+      wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      addra => addra,
+      dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
+      douta => douta,
+      clkb => '0',
+      rstb => '0',
+      enb => '0',
+      regceb => '0',
+      web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
+      dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
+      injectsbiterr => '0',
+      injectdbiterr => '0',
+      eccpipece => '0',
+      sleep => '0',
+      deepsleep => '0',
+      shutdown => '0',
+      s_aclk => '0',
+      s_aresetn => '0',
+      s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
+      s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
+      s_axi_awvalid => '0',
+      s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
+      s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axi_wlast => '0',
+      s_axi_wvalid => '0',
+      s_axi_bready => '0',
+      s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
+      s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
+      s_axi_arvalid => '0',
+      s_axi_rready => '0',
+      s_axi_injectsbiterr => '0',
+      s_axi_injectdbiterr => '0'
+    );
+END lightning_20_20_arch;

TankGame.srcs/sources_1/new/Top.v

@@ -103,11 +103,11 @@ wire enermy1_revive, enermy2_revive, enermy3_revive, enermy4_revive;
 wire player1_scored, player2_scored;
 wire [ 1: 0 ] winner;
 wire timeup;
+wire [ 7: 0 ] initial_num;
 assign reset_n = ~BTNC;
 
 clock MyClock(
           .clk_100MHz( clk ),
-          .item_faster( item_faster ),
           .clk_2Hz( clk_2Hz ),
           .clk_4Hz( clk_4Hz ),
           .clk_8Hz( clk_8Hz ),
@@ -121,13 +121,16 @@ KeyBoard_PS2 My_Ps2(
                  .out( KeyBoard_Output )
              );
 clk_wiz_0 clk_vga( .clk_in1( clk ), .reset( 1'b0 ), .clk_25m( clk_VGA ) , .locked() );
-
+CreateNumber u_CreateNumber(
+                 .btn( SW[ 3: 1 ] ),
+                 .num( initial_num )
+             );
 
 game_mode u_game_mode(
               .clk( clk ),
               .btn_confirm( BTNC ),
               .btn_mode_sel( SW[ 0 ] ),
-              .btn_return( BTNU ),                                                                                                                                                                                                                                                                    //the under button is used for return to the game
+              .btn_return( BTNU ),                                                                                                                                                                                                                                                                                               //the under button is used for return to the game
               .gameover_classic( gameover_classic ),
               .gameover_infinity( gameover_infinity ),
               .enable_shell1( enable_enermy1_bullet ),
@@ -162,6 +165,7 @@ game_logic_classic u_game_logic_classic(
                        .btn_return( BTNU ),
                        .btn_stop( BTND ),
                        .enable_game_classic( enable_game_classic ),
+                       .initial_num( initial_num[ 3: 0 ] ),
                        .mytank1_state( player1_tank_en ),
                        .mytank2_state( player2_tank_en ),
                        .scorea1( scorea1 ),
@@ -187,6 +191,7 @@ game_logic_infinity u_game_logic_infinity(
                         .btn_return( BTNU ),
                         .btn_stop( BTND ),
                         .enable_game_infinity( enable_game_infinity ),
+                        .initial_num( initial_num[ 7: 4 ] ),
                         .mytank1_state( player1_tank_en ),
                         .mytank2_state( player2_tank_en ),
                         .scorea1( scorea1 ),
@@ -237,21 +242,21 @@ vga_data_background u_data_background(
 vga_data_selector u_vga_data_selector(
                       .clk( clk ),
                       .in1( backgroundData ),
-                      .in2( player1_tank_data ),
+                      .in2( ( player1_tank_data == 12'hfff ) ? 12'h000 : player1_tank_data ),
-                      .in3( player1_bullet_data ),
+                      .in3( ( player1_bullet_data == 12'hfff ) ? 12'h000 : player1_bullet_data ),
-                      .in4( player2_tank_data ),
+                      .in4( ( player2_tank_data == 12'hfff ) ? 12'h000 : player2_tank_data ),
-                      .in5( player2_bullet_data ),
+                      .in5( ( player2_bullet_data == 12'hfff ) ? 12'h000 : player2_bullet_data ),
-                      .in6( enermy1_tank_data ),
+                      .in6( ( enermy1_tank_data == 12'hfff ) ? 12'h000 : enermy1_tank_data ),
-                      .in7( enermy2_tank_data ),
+                      .in7( ( enermy2_tank_data == 12'hfff ) ? 12'h000 : enermy2_tank_data ),
-                      .in8( enermy3_tank_data ),
+                      .in8( ( enermy3_tank_data == 12'hfff ) ? 12'h000 : enermy3_tank_data ),
-                      .in9( enermy4_tank_data ),
+                      .in9( ( enermy4_tank_data == 12'hfff ) ? 12'h000 : enermy4_tank_data ),
-                      .in10( enermy1_bullet_data ),
+                      .in10( ( enermy1_bullet_data == 12'hfff ) ? 12'h000 : enermy1_bullet_data ),
-                      .in11( enermy2_bullet_data ),
+                      .in11( ( enermy2_bullet_data == 12'hfff ) ? 12'h000 : enermy2_bullet_data ),
-                      .in12( enermy3_bullet_data ),
+                      .in12( ( enermy3_bullet_data == 12'hfff ) ? 12'h000 : enermy3_bullet_data ),
-                      .in13( enermy4_bullet_data ),
+                      .in13( ( enermy4_bullet_data == 12'hfff ) ? 12'h000 : enermy4_bullet_data ),
                       .in14( game_information_data ),
                       .in15( heart_gametips_data ),
-                      .in16( item_data ),
+                      .in16( ( item_data == 12'hfff ) ? 12'h000 : item_data ),
                       .in17(),
                       .out( VGAData )
                   );
@@ -297,6 +302,7 @@ tank_display enermy1_tank_display(
                  .vgaV( vgaV ),
                  .tankH( enermy1_tank_H ),
                  .tankV( enermy1_tank_V ),
+                 .item_invincible( 0 ),
                  .tankData( enermy1_tank_data )
              );
 
@@ -311,6 +317,7 @@ tank_display enermy2_tank_display(
                  .vgaV( vgaV ),
                  .tankH( enermy2_tank_H ),
                  .tankV( enermy2_tank_V ),
+                 .item_invincible( 0 ),
                  .tankData( enermy2_tank_data )
              );
 tank_display enermy3_tank_display(
@@ -324,6 +331,7 @@ tank_display enermy3_tank_display(
                  .vgaV( vgaV ),
                  .tankH( enermy3_tank_H ),
                  .tankV( enermy3_tank_V ),
+                 .item_invincible( 0 ),
                  .tankData( enermy3_tank_data )
              );
 tank_display enermy4_tank_display(
@@ -337,47 +345,48 @@ tank_display enermy4_tank_display(
                  .vgaV( vgaV ),
                  .tankH( enermy4_tank_H ),
                  .tankV( enermy4_tank_V ),
+                 .item_invincible( 0 ),
                  .tankData( enermy4_tank_data )
              );
 
 tank_move player1_tank_move(
               clk, reset_n, 1,
               150, 150,
-              player1_tank_dir, player1_tank_en, player1_tank_move_en, 1'b0, player1_moving, item_frozen,
+              player1_tank_dir, player1_tank_en, player1_tank_move_en, 1'b0, player1_moving, item_frozen, item_faster,
               player1_tank_H, player1_tank_V, player1_tank_moving_direction
           );
 
 tank_move player2_tank_move(
               clk, reset_n, 1,
               350, 350,
-              player2_tank_dir, player2_tank_en, player2_tank_move_en, 1'b0, player2_moving, item_frozen,
+              player2_tank_dir, player2_tank_en, player2_tank_move_en, 1'b0, player2_moving, item_frozen, item_faster,
               player2_tank_H, player2_tank_V, player2_tank_moving_direction
           );
 
 tank_move enermy1_tank_move(
               clk, reset_n, 1,
               0, 0,
-              enermy1_tank_dir, enermy1_tank_en, enermy1_tank_move_en, 1'b1, enermy1_moving, item_frozen,
+              enermy1_tank_dir, enermy1_tank_en, enermy1_tank_move_en, 1'b1, enermy1_moving, item_frozen, item_faster,
               enermy1_tank_H, enermy1_tank_V, enermy1_tank_moving_direction
           );
 
 tank_move enermy2_tank_move(
               clk, reset_n, 1,
               540, 0,
-              enermy2_tank_dir, enermy2_tank_en, enermy2_tank_move_en, 1'b1, enermy2_moving, item_frozen,
+              enermy2_tank_dir, enermy2_tank_en, enermy2_tank_move_en, 1'b1, enermy2_moving, item_frozen, item_faster,
               enermy2_tank_H, enermy2_tank_V, enermy2_tank_moving_direction
           );
 tank_move enermy3_tank_move(
               clk, reset_n, 1,
               0, 350,
-              enermy3_tank_dir, enermy3_tank_en, enermy3_tank_move_en, 1'b1, enermy3_moving, item_frozen,
+              enermy3_tank_dir, enermy3_tank_en, enermy3_tank_move_en, 1'b1, enermy3_moving, item_frozen, item_faster,
               enermy3_tank_H, enermy3_tank_V, enermy3_tank_moving_direction
           );
 
 tank_move enermy4_tank_move(
               clk, reset_n, 1,
               540, 350,
-              enermy4_tank_dir, enermy4_tank_en, enermy4_tank_move_en, 1'b1, enermy4_moving, item_frozen,
+              enermy4_tank_dir, enermy4_tank_en, enermy4_tank_move_en, 1'b1, enermy4_moving, item_frozen, item_faster,
               enermy4_tank_H, enermy4_tank_V, enermy4_tank_moving_direction
           );
 
@@ -493,6 +502,7 @@ enermy_control enermy4_control(
 
 control_signals u_control_signals(
                     clk, reset_n,
+                    item_invincible,
                     player1_bullet_H, player1_bullet_V, player2_bullet_H, player2_bullet_V,
                     enermy1_bullet_H, enermy1_bullet_V,
                     enermy2_bullet_H, enermy2_bullet_V,
@@ -533,10 +543,10 @@ bullet_control bullet_player1(
                    .tank_dir( player1_tank_dir ),
                    .tank_fire( player1_fire ),
                    .player_enermy( 1'b0 ),
-
+                   .item_faster( item_faster ),
                    .vgaV( vgaV ),
                    .vgaH( vgaH ),
-                   .start( 1 ),
+                   .start( enable_game_classic | enable_game_infinity ),
                    .ready( player1_bullet_en ),
                    .bulletData( player1_bullet_data ),
                    .bullet_H_feedback( player1_bullet_H ),
@@ -553,10 +563,10 @@ bullet_control bullet_player2(
                    .tank_dir( player2_tank_dir ),
                    .tank_fire( player2_fire ),
                    .player_enermy( 1'b0 ),
-
+                   .item_faster( item_faster ),
                    .vgaV( vgaV ),
                    .vgaH( vgaH ),
-                   .start( 1 ),
+                   .start( enable_game_classic | enable_game_infinity ),
                    .ready( player2_bullet_en ),
                    .bulletData( player2_bullet_data ),
                    .bullet_H_feedback( player2_bullet_H ),
@@ -573,10 +583,10 @@ bullet_control bullet_enermy1(
                    .tank_dir( enermy1_tank_dir ),
                    .tank_fire( enermy1_fire ),
                    .player_enermy( 1'b1 ),
-
+                   .item_faster( item_faster ),
                    .vgaV( vgaV ),
                    .vgaH( vgaH ),
-                   .start( 1 ),
+                   .start( enable_game_classic | enable_game_infinity ),
                    .ready( enermy1_bullet_en ),
                    .bulletData( enermy1_bullet_data ),
                    .bullet_H_feedback( enermy1_bullet_H ),
@@ -593,10 +603,10 @@ bullet_control bullet_enermy2(
                    .tank_dir( enermy2_tank_dir ),
                    .tank_fire( enermy2_fire ),
                    .player_enermy( 1'b1 ),
-
+                   .item_faster( item_faster ),
                    .vgaV( vgaV ),
                    .vgaH( vgaH ),
-                   .start( 1 ),
+                   .start( enable_game_classic | enable_game_infinity ),
                    .ready( enermy2_bullet_en ),
                    .bulletData( enermy2_bullet_data ),
                    .bullet_H_feedback( enermy2_bullet_H ),
@@ -613,10 +623,10 @@ bullet_control bullet_enermy3(
                    .tank_dir( enermy3_tank_dir ),
                    .tank_fire( enermy3_fire ),
                    .player_enermy( 1'b1 ),
-
+                   .item_faster( item_faster ),
                    .vgaV( vgaV ),
                    .vgaH( vgaH ),
-                   .start( 1 ),
+                   .start( enable_game_classic | enable_game_infinity ),
                    .ready( enermy3_bullet_en ),
                    .bulletData( enermy3_bullet_data ),
                    .bullet_H_feedback( enermy3_bullet_H ),
@@ -633,10 +643,10 @@ bullet_control bullet_enermy4(
                    .tank_dir( enermy4_tank_dir ),
                    .tank_fire( enermy4_fire ),
                    .player_enermy( 1'b1 ),
-
+                   .item_faster( item_faster ),
                    .vgaV( vgaV ),
                    .vgaH( vgaH ),
-                   .start( 1 ),
+                   .start( enable_game_classic | enable_game_infinity ),
                    .ready( enermy4_bullet_en ),
                    .bulletData( enermy4_bullet_data ),
                    .bullet_H_feedback( enermy4_bullet_H ),
@@ -668,6 +678,8 @@ game_information_display u_game_information_display(
 vga_data_heart_gametips u_vga_data_heart_gametips(
                             .clk( clk ),
                             .mode( mode ),
+                            .initial_num( initial_num ),
+                            .choose_mode( SW[ 0 ] ),
                             .vgaH( vgaH ),
                             .vgaV( vgaV ),
                             .winner( winner ),
@@ -681,7 +693,7 @@ vga_data_heart_gametips u_vga_data_heart_gametips(
                             .score_classic( score_classic ),
                             .vgaData( heart_gametips_data )
                         );
-assign item_faster = 0;
+
 
 item_logic u_item_logic(
                .clk( clk ),
@@ -704,6 +716,7 @@ item_logic u_item_logic(
                .item_addHP( item_addHP ),
                .item_addtime( item_addtime ),
                .item_frozen( item_frozen ),
+               .item_faster( item_faster ),
                .which_player( which_player ),
                .VGA_data_reward( item_data )
            );
@@ -715,7 +728,7 @@ wire [ 31: 0 ] num ;
 // assign num = { 3'b000, player1_tank_collide[7], 3'b000, player1_tank_collide[6], 3'b000, player1_tank_collide[5], 3'b000, player1_tank_collide[4],
 //               player1_bullet_H[7:0], player1_bullet_V[7:0] };
 
-assign num = { 3'b000, player1_moving, 3'b000, player1_tank_dir[ 1 ], 3'b000, player1_tank_dir[ 0 ], 4'b0000, 3'b000, player1_moving, 3'b000, player1_tank_en, 3'b000, player2_tank_en, 3'b000, player1_tank_move_en };
+assign num = { 3'b0, initial_num[ 7 ], 3'b0, initial_num[ 6 ], 3'b0, initial_num[ 5 ], 3'b0, initial_num[ 4 ], 3'b0, initial_num[ 3 ], 3'b0, initial_num[ 2 ], 3'b0, initial_num[ 1 ], 3'b0, initial_num[ 0 ] };
 // Disp_Num my_Disp_Num(
 //              .clk( clk ),
 //              .RST( 1'b0 ),
@@ -734,7 +747,7 @@ SegAndLed u_SegAndLed(
               .score_classic( score_classic ),
               .score_infinity( score_infinity ),
               .timer( timer ),
-              .default_num( num ),                                                                                                                                                                                                                                        //when mode ==00(before begin mode) then output num ,you can also use it as debug
+              .default_num( num ),                                                                                                                                                                                                                                                                   //when mode ==00(before begin mode) then output num ,you can also use it as debug
               .enable_game_classic( enable_game_classic ),
               .enable_game_infinity( enable_game_infinity ),
               .player1_tank_en( player1_tank_en ),

TankGame.srcs/sources_1/new/bullet_control.v

@@ -11,12 +11,12 @@ module bullet_control(
            input tank_en,
            input [ 1: 0 ] tank_dir,
            input tank_fire,
-           input player_enermy,               //player is 0 and enermy is 1
+           input player_enermy,                   //player is 0 and enermy is 1
 
            input [ 10: 0 ] vgaH,
            input [ 10: 0 ] vgaV,
            input ready,
-
+           input item_faster,
            output [ 11: 0 ] bulletData,
            output reg [ 10: 0 ] bullet_H_feedback,
            output reg [ 10: 0 ] bullet_V_feedback,
@@ -123,7 +123,7 @@ end
 
 reg bullet_move_en;
 wire [ 31: 0 ] bullet_speed;
-assign bullet_speed = player_enermy ? 1_000_000 : 1_000_000;
+assign bullet_speed = item_faster ? 600_000 : 1_000_000;
 always @( posedge clk ) begin: counter_logic
     if ( !reset_n ) begin
         counter <= 0;

TankGame.srcs/sources_1/new/clock.v

@@ -22,7 +22,6 @@
 
 module clock(
            input wire clk_100MHz,
-           input wire item_faster,
            output reg clk_2Hz,
            output reg clk_4Hz,
            output reg clk_8Hz,
@@ -90,12 +89,9 @@ always @( posedge clk_100MHz ) begin
 end
 
 always @( posedge clk_100MHz ) begin
-    if ( item_faster == 1'b1 ) begin
+
-        ending_4Hz <= 6250000;
+    ending_4Hz <= 12500000;
-    end
+
-    else begin
-        ending_4Hz <= 12500000;
-    end
 end
 
 always @( posedge clk_100MHz ) begin

TankGame.srcs/sources_1/new/control_signals.v

@@ -2,6 +2,7 @@
 
 module control_signals(
            clk, reset_n,
+           item_invincible,
            player1_bullet_H, player1_bullet_V, player2_bullet_H, player2_bullet_V,
            enermy1_bullet_H, enermy1_bullet_V,
            enermy2_bullet_H, enermy2_bullet_V,
@@ -30,6 +31,7 @@ module control_signals(
            //    scorea1, scorea2, scoreb1, scoreb2, scorec1, scorec2, scored1, scored2
        );
 input clk, reset_n;
+input item_invincible;
 input [ 10: 0 ] player1_bullet_H, player1_bullet_V, player2_bullet_H, player2_bullet_V;
 input [ 10: 0 ] enermy1_bullet_H, enermy1_bullet_V,
       enermy2_bullet_H, enermy2_bullet_V,
@@ -789,7 +791,7 @@ end
 // end
 always @( posedge clk ) begin: player2_tank_enable_signal
 
-    if ( player2_revive ) begin
+    if ( player2_revive || item_invincible ) begin
         player2_tank_en_feedback <= 1;
     end
     else if ( !reset_n ) begin
@@ -808,7 +810,7 @@ end
 
 
 always @( posedge clk ) begin: player1_tank_enable_signal
-    if ( player1_revive ) begin
+    if ( player1_revive || item_invincible ) begin
         player1_tank_en_feedback <= 1;
     end
     else if ( !reset_n ) begin

TankGame.srcs/sources_1/new/enermy_control.v

@@ -24,7 +24,7 @@ module enermy_control(
            input clk_8Hz,
            input clk_2Hz,
            input clk_10ms,
-           input [ 1: 0 ] flag,                           //00 01 10 11 four tanks
+           input [ 1: 0 ] flag,                                     //00 01 10 11 four tanks
            input [ 10: 0 ] player1_H,
            input [ 10: 0 ] player1_V,
            input [ 10: 0 ] player2_H,
@@ -73,15 +73,16 @@ wire [ 10: 0 ] chase_tank_V = rand ? player1_V : player2_V;
 
 reg Continue;
 reg [ 2: 0 ] Continue_num;
-
+reg enermy_fire_tmp;
 assign enermy_moving = enermy_tank_en;
 
 initial begin
     enermy_fire <= 1'b0;
-    counter_num <= flag;
+    counter_num <= 0;
-    rand <= flag[ 0 ];
+    rand <= 0;
     Continue <= 0;
     Continue_num <= 0;
+    enermy_fire_tmp <= 0;
 end
 
 Random u_Random(
@@ -198,7 +199,7 @@ always @( posedge clk_2Hz ) begin
 
     end
     else begin
-        enermy_fire <= 1'b0;
+        enermy_fire_tmp <= 1'b0;
         if ( rand ) begin
             if ( enermy_V + TANK_HEIGHT / 2 <= chase_tank_V ) begin
                 enermy_dir_feedback_tmp <= 2'b01;
@@ -207,7 +208,7 @@ always @( posedge clk_2Hz ) begin
                 enermy_dir_feedback_tmp <= 2'b00;
             end
             else begin
-                enermy_fire <= 1'b1;
+                enermy_fire_tmp <= 1'b1;
                 if ( enermy_H < chase_tank_H ) begin
                     enermy_dir_feedback_tmp <= 2'b11;
                 end
@@ -224,7 +225,7 @@ always @( posedge clk_2Hz ) begin
                 enermy_dir_feedback_tmp <= 2'b10;
             end
             else begin
-                enermy_fire <= 1'b1;
+                enermy_fire_tmp <= 1'b1;
                 if ( enermy_V < chase_tank_V ) begin
                     enermy_dir_feedback_tmp <= 2'b01;
                 end
@@ -247,10 +248,11 @@ always @( posedge clk_2Hz ) begin
         rand <= rand_num[ 0 ] ;
     end
     Continue_num <= Continue_num + 1'b1;
-    if ( Continue_num == 4 ) begin
+    if ( Continue_num == 2 ) begin
         Continue_num <= 0;
         Continue <= 0;
     end
+    enermy_fire <= enermy_fire_tmp;
 
 end
 

TankGame.srcs/sources_1/new/game_information_display.v

@@ -24,6 +24,7 @@ module game_information_display(
            input clk,
            input enable_game_classic,
            input enable_game_infinity,
+
            input [ 7: 0 ] score_classic,
            input [ 4: 0 ] timer,
            input [ 10: 0 ] vgaH,
@@ -95,10 +96,10 @@ infinity_info_180_24 u_infinity_info_180_24(
 always @( posedge clk ) begin
     if ( enable_game_classic ) begin
         vga_en3 <= 1;
-        if ( vgaH >= 320 && vgaH < 480 && vgaV >= 1 && vgaV < 21 && ( vgaH - 320 ) < score_classic[ 3: 0 ] * 20 ) begin
+        if ( vgaH >= 320 && vgaH < 640 && vgaV >= 1 && vgaV < 21 && ( vgaH - 320 ) < score_classic[ 3: 0 ] * 20 ) begin
             addr_redflag <= ( vgaH - 320 ) % 20 + ( vgaV - 1 ) * 20;
         end
-        else if ( vgaH >= 320 && vgaH < 480 && vgaV >= 24 && vgaV < 44 && ( vgaH - 320 ) < score_classic[ 7: 4 ] * 20 ) begin
+        else if ( vgaH >= 320 && vgaH < 640 && vgaV >= 24 && vgaV < 44 && ( vgaH - 320 ) < score_classic[ 7: 4 ] * 20 ) begin
             addr_redflag <= ( vgaH - 320 ) % 20 + ( vgaV - 24 ) * 20;
         end
         else begin

TankGame.srcs/sources_1/new/game_logic_classic.v

@@ -28,6 +28,7 @@ module game_logic_classic(
            input enable_game_classic,
            input mytank1_state,
            input mytank2_state,
+           input [ 3: 0 ] initial_num,
            input [ 3: 0 ] scorea1,
            input [ 3: 0 ] scorea2,
            input [ 3: 0 ] scoreb1,
@@ -44,7 +45,7 @@ module game_logic_classic(
 
            output reg gameover_classic,
            output wire [ 15: 0 ] led_classic,
-           output reg [ 7: 0 ] score_classic,              //[7:4] is player2 ,[3:0] is player1
+           output reg [ 7: 0 ] score_classic,                     //[7:4] is player2 ,[3:0] is player1
            output reg [ 1: 0 ] winner
        );
 reg [ 3: 0 ] score1;
@@ -75,8 +76,8 @@ always @( posedge clk ) begin
         HP2_value <= HP2_value;
     end
     if ( enable_game_classic == 1'b0 ) begin
-        HP1_value <= 4;
+        HP1_value <= initial_num;
-        HP2_value <= 4;
+        HP2_value <= initial_num;
     end
     if ( item_addHP && ~item_addHP_last ) begin
         if ( which_player == 0 ) begin
@@ -135,9 +136,9 @@ always @( posedge clk ) begin
         score2 <= scorea2 + scoreb2 + scorec2 + scored2;
         score_classic[ 7: 4 ] <= score2[ 3: 0 ];
         score_classic[ 3: 0 ] <= score1[ 3: 0 ];
-        if ( HP1_value == 0 || HP2_value == 0 || score1 >= 8 || score2 >= 8 ) begin
+        if ( HP1_value == 0 || HP2_value == 0 || score1 >= 14 || score2 >= 14 ) begin
             gameover_classic <= 1;
-            if ( HP2_value == 0 || score1 >= 8 ) begin
+            if ( HP2_value == 0 || score1 >= 14 ) begin
                 winner <= 2'b10;
             end
             else begin

TankGame.srcs/sources_1/new/game_logic_infinity.v

@@ -27,6 +27,7 @@ module game_logic_infinity(
            input enable_game_infinity,
            input mytank1_state,
            input mytank2_state,
+           input [ 3: 0 ] initial_num,
            input [ 3: 0 ] scorea1,
            input [ 3: 0 ] scorea2,
            input [ 3: 0 ] scoreb1,
@@ -45,7 +46,7 @@ module game_logic_infinity(
            output reg gameover_infinity,
 
            output wire [ 15: 0 ] led_infinity,
-           output reg [ 7: 0 ] score_infinity,                        //[7:4] is player2 ,[3:0] is player1
+           output reg [ 7: 0 ] score_infinity,                                  //[7:4] is player2 ,[3:0] is player1
            output reg timeup
        );
 
@@ -60,7 +61,7 @@ reg item_addtime_last;
 initial begin
     gameover_infinity <= 0;
     cnt <= 0;
-    timer <= 16;
+    timer <= 0;
     score_infinity <= 0;
     score1 <= 0;
     score2 <= 0;
@@ -121,7 +122,7 @@ always @( posedge clk ) begin
     if ( !enable_game_infinity ) begin
         gameover_infinity <= 0;
         cnt <= 0;
-        timer <= 16;
+        timer <= initial_num;
         if ( btn_return ) begin
             score1 <= 0;
             score2 <= 0;
@@ -136,13 +137,13 @@ always @( posedge clk ) begin
 
     else begin
         if ( timer == 0 || btn_stop || ( | HP1_value == 0 ) || ( | HP2_value == 0 ) ) begin
-            timer <= 16;
+            timer <= initial_num;
             gameover_infinity <= 1;
             timeup <= 1'b1;
         end
         else begin
             if ( score1 < scorea1 + scoreb1 + scorec1 + scored1 ) begin
-                if ( add_flag == 0 && timer > 0 && timer < 16 ) begin
+                if ( add_flag == 0 && timer > 0 && timer < initial_num ) begin
                     timer <= timer + 3;
                     cnt <= 0;
                     add_flag = 1;
@@ -152,7 +153,7 @@ always @( posedge clk ) begin
                 add_flag = 0;
             end
             if ( score2 < scorea2 + scoreb2 + scorec2 + scored2 ) begin
-                if ( add_flag == 0 && timer > 0 && timer < 16 ) begin
+                if ( add_flag == 0 && timer > 0 && timer < initial_num ) begin
                     timer <= timer + 3;
                     cnt <= 0;
                     add_flag = 1;
@@ -166,12 +167,12 @@ always @( posedge clk ) begin
             score2 <= scorea2 + scoreb2 + scorec2 + scored2;
 
             if ( item_addtime == 1 ) begin
-                if ( item_flag == 0 && timer > 0 && timer < 16 ) begin
+                if ( item_flag == 0 && timer > 0 && timer < initial_num ) begin
                     begin
-                        if ( timer == 15 ) begin
+                        if ( timer == initial_num - 1 ) begin
                             timer <= timer + 1;
                         end
-                        else if ( timer == 14 ) begin
+                        else if ( timer == initial_num - 2 ) begin
                             timer <= timer + 2;
                         end
                         else begin
@@ -197,7 +198,7 @@ always @( posedge clk ) begin
             end
 
             if ( item_addtime && ~item_addtime_last ) begin
-                timer <= timer + 10;
+                timer <= 4'b1111;
             end
             item_addtime_last <= item_addtime;
         end

TankGame.srcs/sources_1/new/item_display.v

@@ -26,7 +26,7 @@ module item_display(
            input enable_reward,
            input [ 10: 0 ] random_xpos,
            input [ 10: 0 ] random_ypos,
-           input [ 1: 0 ] item_type,
+           input [ 2: 0 ] item_type,
            input [ 10: 0 ] VGA_h,
            input [ 10: 0 ] VGA_V,
            input enable_game_classic,
@@ -39,12 +39,12 @@ module item_display(
 wire [ 5: 0 ] ITEM_WIDTH ;
 wire [ 5: 0 ] ITEM_HEIGHT;
 
-assign ITEM_WIDTH = item_type == 2'b11 ? 32 : 20;
+assign ITEM_WIDTH = item_type == 3 ? 32 : 20;
-assign ITEM_HEIGHT = item_type == 2'b11 ? 32 : 20;
+assign ITEM_HEIGHT = item_type == 3 ? 32 : 20;
-reg [ 8: 0 ] addra_add_heart, addra_add_timing, addra_frozen;
+reg [ 8: 0 ] addra_add_heart, addra_add_timing, addra_frozen, addra_faster;
 reg [ 9: 0 ] addra_invincible;
 
-wire[ 11: 0 ] add_heart_pic, add_timing_pic, add_frozen_pic, invincible_pic;
+wire[ 11: 0 ] add_heart_pic, add_timing_pic, add_frozen_pic, invincible_pic, faster_pic;
 // reg [ 11: 0 ] add_heart_reg, add_timing_reg, add_frozen_reg, invincible_reg;
 
 
@@ -55,9 +55,10 @@ always @( posedge clk ) begin
             addra_add_heart <= ( VGA_h - random_xpos ) + ( VGA_V - random_ypos ) * 20;
             addra_add_timing <= ( VGA_h - random_xpos ) + ( VGA_V - random_ypos ) * 20;
             addra_frozen <= ( VGA_h - random_xpos ) + ( VGA_V - random_ypos ) * 20;
+            addra_faster <= ( VGA_h - random_xpos ) + ( VGA_V - random_ypos ) * 20;
             addra_invincible <= ( VGA_h - random_xpos ) + ( VGA_V - random_ypos ) * 32;
             case ( item_type )
-                2'b01: begin
+                1: begin
                     if ( enable_game_classic == 1 ) begin
                         VGA_data <= add_heart_pic;
                     end
@@ -65,12 +66,15 @@ always @( posedge clk ) begin
                         VGA_data <= add_timing_pic;
                     end
                 end
-                2'b10: begin
+                2: begin
                     VGA_data <= add_frozen_pic;
                 end
-                2'b11: begin
+                3: begin
                     VGA_data <= invincible_pic;
                 end
+                4: begin
+                    VGA_data <= faster_pic;
+                end
                 default : begin
                     VGA_data <= 0;
                 end
@@ -109,4 +113,11 @@ invincible_star_32_32 u_invincible_star(
                           .addra( addra_invincible ),
                           .douta( invincible_pic )
                       );
+
+lightning_20_20 u_lightning_20_20(
+                    .clka( clk ),
+                    .ena( 1'b1 ),
+                    .addra( addra_faster ),
+                    .douta( faster_pic )
+                );
 endmodule

TankGame.srcs/sources_1/new/item_logic.v

@@ -42,11 +42,12 @@ module item_logic(
            output reg item_addtime,
            output reg item_frozen,
            output reg item_addHP,
+           output reg item_faster,
            output reg which_player,
            output [ 11: 0 ] VGA_data_reward
        );
 
-wire [ 1: 0 ] item_type;
+wire [ 2: 0 ] item_type;
 wire [ 10: 0 ] random_xpos, random_ypos;
 reg [ 31: 0 ] cnt;
 
@@ -63,6 +64,7 @@ initial begin
     item_frozen <= 0;
     item_addHP <= 0;
     which_player <= 0;
+    item_faster <= 0;
 end
 
 wire player1_tank_get, player1_tank_tmp;
@@ -112,11 +114,17 @@ always @( posedge clk ) begin
                     item_invincible <= 1'b1;
                     which_player <= player2_tank_get;
                 end
+                4: begin
+                    item_faster <= 1'b1;
+                    which_player <= player2_tank_get;
+
+                end
                 default : begin
                     item_addHP <= 1'b0;
                     item_addtime <= 1'b0;
                     item_frozen <= 1'b0;
                     item_invincible <= 1'b0;
+                    item_faster <= 1'b0;
                 end
 
             endcase
@@ -125,6 +133,13 @@ always @( posedge clk ) begin
         else begin
             set_finish <= 1'b0;
         end
+        if ( item_faster ) begin
+            cnt <= cnt + 1;
+            if ( cnt >= 900000000 ) begin
+                item_faster <= 1'b0;
+                cnt <= 0;
+            end
+        end
         if ( item_invincible ) begin
             cnt <= cnt + 1;
             if ( cnt >= 800000000 ) begin
@@ -159,6 +174,7 @@ always @( posedge clk ) begin
         item_invincible <= 0;
         item_addtime <= 0;
         item_frozen <= 0;
+        item_faster <= 0;
         item_addHP <= 0;
         which_player <= 0;
     end

TankGame.srcs/sources_1/new/item_random_generator.v

@@ -27,7 +27,7 @@ module item_random_generator(
            input enable,
            output reg dout,
            output reg set_require,
-           output reg [ 1: 0 ] item_type,
+           output reg [ 2: 0 ] item_type,
            output reg [ 10: 0 ] random_xpos,
            output reg [ 10: 0 ] random_ypos
        );
@@ -81,7 +81,7 @@ always @( posedge clk ) begin
             lock <= 1'b1;
             random_xpos <= random_num[ 14: 1 ] % ( WIDTH - TANK_WIDTH );
             random_ypos <= random_num[ 13: 0 ] % ( HEIGHT - TANK_HEIGHT );
-            item_type <= ( random_num[ 14: 0 ] % 3 ) + 1;
+            item_type <= ( random_num[ 14: 0 ] % 4 ) + 1;
         end
     end
     else begin

TankGame.srcs/sources_1/new/tank_move.v

@@ -3,7 +3,7 @@
 module tank_move(
            clk, reset_n, start,
            init_H, init_V,
-           tank_dir, tank_en, tank_move_en, player_enermy, moving, item_frozen,
+           tank_dir, tank_en, tank_move_en, player_enermy, moving, item_frozen, item_faster,
            tank_H, tank_V, tank_dir_feedback
        );
 
@@ -17,6 +17,7 @@ input [ 10: 0 ] init_V;
 input [ 1: 0 ] tank_dir;
 input tank_en;
 input tank_move_en;
+input item_faster;
 input player_enermy;
 output reg [ 10: 0 ] tank_H;
 output reg [ 10: 0 ] tank_V;
@@ -170,7 +171,7 @@ always @( posedge clk ) begin: tank_move_logic
 end
 
 reg [ 31: 0 ] counter;
-wire [ 31: 0 ] counter_num = player_enermy ? 2_000_000 : 2_000_000;
+wire [ 31: 0 ] counter_num = item_faster ? 1_500_000 : 2_100_000;
 always @( posedge clk ) begin
     if ( !reset_n ) begin
         counter <= 0;

TankGame.srcs/sources_1/new/vga_data_background.v

@@ -91,17 +91,17 @@ startpic_450_200 u_start_pic(
                  );
 
 always@( posedge clk ) begin
-    if ( sw_mode_sel ) begin
+    if ( !sw_mode_sel ) begin
-        if ( vgaH >= 229 && vgaH <= 233 && vgaV >= 233 && vgaV <= 237 ) begin
+        if ( vgaH >= 223 && vgaH <= 233 && vgaV >= 227 && vgaV <= 237 ) begin
-            VGA_data_cursor <= 12'hFF0;
+            VGA_data_cursor <= 12'h0F0;
         end
         else begin
             VGA_data_cursor <= 12'h0;
         end
     end
     else begin
-        if ( vgaH >= 229 && vgaH <= 233 && vgaV >= 252 && vgaV <= 256 ) begin
+        if ( vgaH >= 223 && vgaH <= 233 && vgaV >= 246 && vgaV <= 256 ) begin
-            VGA_data_cursor <= 12'hFF0;
+            VGA_data_cursor <= 12'h0F0;
         end
         else begin
             VGA_data_cursor <= 12'h0;

TankGame.srcs/sources_1/new/vga_data_heart_gametips.v

@@ -23,6 +23,8 @@
 module vga_data_heart_gametips(
            input clk,
            input [ 2: 0 ] mode,
+           input [ 7: 0 ] initial_num,
+           input choose_mode,
            input [ 10: 0 ] vgaH,
            input [ 10: 0 ] vgaV,
            input [ 1: 0 ] winner,
@@ -42,6 +44,52 @@ wire [ 11: 0 ] heart_pic1 , heart_pic2, classic_gameover_tips_pic1, classic_game
 reg [ 8: 0 ] addra_heart_pic1, addra_heart_pic2;
 reg [ 12: 0 ] addr_classic_gameover_tips_pic1, addr_classic_gameover_tips_pic2, addr_infinity_gameover_tips_pic;
 
+reg [ 8: 0 ] addra_initial_heart;
+reg [ 7: 0 ] addra_initial_time;
+wire [ 11: 0 ] initial_heart_pic, initial_time_pic;
+reg [ 11: 0 ] initial_heart_reg, initial_time_reg;
+
+always @( posedge clk ) begin
+    if ( mode != 0 ) begin
+        initial_heart_reg <= 0;
+        initial_time_reg <= 0;
+    end
+    else begin
+        if ( choose_mode == 0 ) begin
+            initial_time_reg <= 0;
+            if ( vgaV >= 320 && vgaV < 340 && vgaH >= 320 && vgaH < 500 && ( vgaH - 320 ) < initial_num[ 3: 0 ] * 20 ) begin
+                addra_initial_heart <= ( vgaH - 320 ) % 20 + ( vgaV - 320 ) * 20;
+                initial_heart_reg <= initial_heart_pic;
+            end
+            else begin
+                initial_heart_reg <= 0;
+            end
+        end
+        else begin
+            initial_heart_reg <= 0;
+            if ( vgaV >= 320 && vgaV < 335 && vgaH >= 320 && vgaH < 640 && ( vgaH - 320 ) < initial_num[ 7: 4 ] * 15 ) begin
+                addra_initial_time <= ( vgaH - 320 ) % 15 + ( vgaV - 320 ) * 15;
+                initial_time_reg <= initial_time_pic;
+            end
+            else begin
+                initial_time_reg <= 0;
+            end
+        end
+    end
+end
+
+heart_20_20 u1_heart_20_20(
+                .clka( clk ),
+                .addra( addra_initial_heart ),
+                .ena( 1'b1 ),
+                .douta( initial_heart_pic )
+            );
+timing_15_15 u2_timing_15_15(
+                 .clka( clk ),
+                 .addra( addra_initial_time ),
+                 .ena( 1'b1 ),
+                 .douta( initial_time_pic )
+             );
 always @( posedge clk ) begin
     if ( mode == 0 || mode == 3 ) begin
         heart_reg1 <= 0;
@@ -129,8 +177,6 @@ heart_20_20 player1_heart(
                 .douta( heart_pic1 ),
                 .ena( 1'b1 )
             );
-
-
 heart_20_20 player2_heart(
                 .addra( addra_heart_pic2 ),
                 .clka( clk ),
@@ -158,5 +204,5 @@ timeisup_180_38 u_timeisup_180_38(
                     .douta( infinity_gameover_tips_pic ),
                     .ena( 1'b1 )
                 );
-assign vgaData = heart_reg1 | heart_reg2 | classic_gameover_tips_reg1 | classic_gameover_tips_reg2 | infinity_gameover_tips_reg;
+assign vgaData = heart_reg1 | heart_reg2 | classic_gameover_tips_reg1 | classic_gameover_tips_reg2 | infinity_gameover_tips_reg | initial_heart_reg | initial_time_reg;
 endmodule

TankGame.xpr

@@ -36,13 +36,13 @@
     <Option Name="WTVcsLaunchSim" Val="0"/>
     <Option Name="WTRivieraLaunchSim" Val="0"/>
     <Option Name="WTActivehdlLaunchSim" Val="0"/>
-    <Option Name="WTXSimExportSim" Val="34"/>
+    <Option Name="WTXSimExportSim" Val="35"/>
-    <Option Name="WTModelSimExportSim" Val="34"/>
+    <Option Name="WTModelSimExportSim" Val="35"/>
-    <Option Name="WTQuestaExportSim" Val="34"/>
+    <Option Name="WTQuestaExportSim" Val="35"/>
-    <Option Name="WTIesExportSim" Val="34"/>
+    <Option Name="WTIesExportSim" Val="35"/>
-    <Option Name="WTVcsExportSim" Val="34"/>
+    <Option Name="WTVcsExportSim" Val="35"/>
-    <Option Name="WTRivieraExportSim" Val="34"/>
+    <Option Name="WTRivieraExportSim" Val="35"/>
-    <Option Name="WTActivehdlExportSim" Val="34"/>
+    <Option Name="WTActivehdlExportSim" Val="35"/>
     <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
     <Option Name="XSimRadix" Val="hex"/>
     <Option Name="XSimTimeUnit" Val="ns"/>
@@ -54,6 +54,15 @@
   <FileSets Version="1" Minor="31">
     <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
       <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/imports/ScoreBoard/CreateNumber.v">
+        <FileInfo>
+          <Attr Name="ImportPath" Val="$PPRDIR/../../../ISE/Project/ScoreBoard/CreateNumber.v"/>
+          <Attr Name="ImportTime" Val="1603800848"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PSRCDIR/sources_1/new/Disp_Num.v">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -506,6 +515,12 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/pic/lightning_20_20.coe">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="Top"/>
@@ -555,7 +570,7 @@
       <File Path="$PSRCDIR/utils_1/imports/impl_1/Top_routed.dcp">
         <FileInfo>
           <Attr Name="ImportPath" Val="$PRUNDIR/impl_1/Top_routed.dcp"/>
-          <Attr Name="ImportTime" Val="1609923161"/>
+          <Attr Name="ImportTime" Val="1610626227"/>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedInSteps" Val="impl_1"/>
@@ -940,6 +955,19 @@
         <Option Name="UseBlackboxStub" Val="1"/>
       </Config>
     </FileSet>
+    <FileSet Name="lightning_20_20" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lightning_20_20">
+      <File Path="$PSRCDIR/sources_1/ip/lightning_20_20/lightning_20_20.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="lightning_20_20"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
   </FileSets>
   <Simulators>
     <Simulator Name="XSim">
@@ -1250,6 +1278,16 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
+    <Run Id="lightning_20_20_synth_1" Type="Ft3:Synth" SrcSet="lightning_20_20" Part="xc7a100tcsg324-1" ConstrsSet="lightning_20_20" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/lightning_20_20_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/impl_1/Top_routed.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
       <Strategy Version="1" Minor="2">
         <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
@@ -1744,6 +1782,23 @@
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
+    <Run Id="lightning_20_20_impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="lightning_20_20" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="lightning_20_20_synth_1" IncludeInArchive="false" GenFullBitstream="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design" EnableStepBool="1"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
   </Runs>
   <Board/>
   <DashboardSummary Version="1" Minor="0">