76 lines
1.8 KiB
Verilog
76 lines
1.8 KiB
Verilog
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 01/02/2021 06:07:12 PM
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// Design Name:
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// Module Name: Random
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module Random(
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input clk,
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input rst_n,
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input [ 1: 0 ] flag,
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output reg [ 1: 0 ] random,
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output [ 14: 0 ] random_14
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);
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reg [ 14: 0 ] rand_num;
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assign random_14 = rand_num;
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always @( * ) begin
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case ( flag )
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2'b00:
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random <= rand_num[ 1: 0 ];
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2'b01:
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random <= rand_num[ 3: 2 ];
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2'b10:
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random <= rand_num[ 5: 4 ];
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2'b11:
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random <= rand_num[ 7: 6 ];
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endcase
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end
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initial begin
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rand_num = 15'b1111_1111_1111_111;
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end
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always@( posedge clk ) begin
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if ( !rst_n ) begin
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rand_num <= 15'b1111_1111_1111_111;
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end
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else begin
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rand_num[ 0 ] <= rand_num[ 14 ];
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rand_num[ 1 ] <= rand_num[ 0 ];
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rand_num[ 2 ] <= rand_num[ 1 ];
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rand_num[ 3 ] <= rand_num[ 2 ];
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rand_num[ 4 ] <= rand_num[ 3 ] ^ rand_num[ 14 ];
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rand_num[ 5 ] <= rand_num[ 4 ] ^ rand_num[ 14 ];
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rand_num[ 6 ] <= rand_num[ 5 ] ^ rand_num[ 14 ];
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rand_num[ 7 ] <= rand_num[ 6 ];
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rand_num[ 9 ] <= rand_num[ 7 ];
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rand_num[ 8 ] <= rand_num[ 8 ] ^ rand_num[ 14 ];
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rand_num[ 10 ] <= rand_num[ 9 ];
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rand_num[ 11 ] <= rand_num[ 10 ];
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rand_num[ 12 ] <= rand_num[ 11 ] ^ rand_num[ 14 ];
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rand_num[ 13 ] <= rand_num[ 12 ];
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rand_num[ 14 ] <= rand_num[ 13 ];
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end
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end
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endmodule
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