95 lines
2.2 KiB
Verilog
95 lines
2.2 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 01/05/2021 10:41:37 PM
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// Design Name:
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// Module Name: item_random_generator
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module item_random_generator(
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input clk,
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input clk_4Hz,
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input set_finish,
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input enable,
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output reg dout,
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output reg set_require,
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output reg [ 2: 0 ] item_type,
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output reg [ 10: 0 ] random_xpos,
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output reg [ 10: 0 ] random_ypos
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);
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parameter ITEM_BASE_TIME = 24;
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parameter ITEM_STAY_TIME = 32;
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parameter TANK_WIDTH = 32;
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parameter TANK_HEIGHT = 32;
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parameter WIDTH = 640;
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parameter HEIGHT = 480;
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wire [ 14: 0 ] random_num;
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reg [ 31: 0 ] cnt;
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reg lock;
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initial begin
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random_xpos <= 0;
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random_ypos <= 0;
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item_type <= 0;
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lock <= 0;
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end
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Random u_Random(
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.clk( clk_4Hz ),
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.rst_n( 1'b1 ),
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.flag( 2'b00 ),
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.random( ),
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.random_14( random_num )
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);
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always @( posedge clk ) begin
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if ( enable ) begin
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cnt <= cnt + 1'b1;
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if ( cnt >= ITEM_BASE_TIME * 25000000 ) begin
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dout <= 1'b1;
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set_require <= 1'b1;
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if ( cnt >= ( ITEM_BASE_TIME + ITEM_STAY_TIME ) * 25000000 || set_finish == 1'b1 ) begin
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dout <= 1'b0;
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cnt <= 0;
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set_require <= 1'b0;
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end
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end
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else begin
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dout <= 1'b0;
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set_require <= 1'b0;
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end
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end
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end
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always @( posedge clk ) begin
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if ( dout ) begin
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if ( !lock ) begin
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lock <= 1'b1;
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random_xpos <= random_num[ 14: 1 ] % ( WIDTH - TANK_WIDTH );
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random_ypos <= random_num[ 13: 0 ] % ( HEIGHT - TANK_HEIGHT );
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item_type <= ( random_num[ 14: 0 ] % 4 ) + 1;
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end
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end
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else begin
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random_xpos <= 0;
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random_ypos <= 0;
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lock <= 0;
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item_type <= 0;
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end
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end
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endmodule
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