39 lines
761 B
Verilog
39 lines
761 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 12/16/2020 03:28:34 PM
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// Design Name:
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// Module Name: clk_div
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module clk_div(
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input clk,
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input rst ,
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output reg[ 31: 0 ] clkdiv
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);
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initial
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clkdiv <= 0;
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always @( posedge clk or posedge rst ) begin
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if ( rst ) begin
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clkdiv <= 0;
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end
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else begin
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clkdiv <= clkdiv + 1'b1;
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end
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end
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endmodule
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