143 lines
3.9 KiB
Verilog
143 lines
3.9 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 01/02/2021 03:30:42 PM
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// Design Name:
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// Module Name: game_information_display
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module game_information_display(
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input clk,
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input enable_game_classic,
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input enable_game_infinity,
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input [ 7: 0 ] score_classic,
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input [ 4: 0 ] timer,
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input [ 10: 0 ] vgaH,
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input [ 10: 0 ] vgaV,
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output [ 11: 0 ] VGA_data
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);
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wire [ 11: 0 ] VGA_data1, VGA_data2, VGA_data3;
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reg vga_en1, vga_en2, vga_en3, vga_en4, vga_en5;
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reg [ 13: 0 ] addr_info_classic;
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reg [ 12: 0 ] addr_info_infinity;
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reg [ 8: 0 ] addr_redflag;
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reg [ 7: 0 ] addr_timing;
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wire [ 11: 0 ] VGA_data4, VGA_data5;
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parameter RED = 12'hF00;
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parameter GREEN = 12'h0F0;
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parameter BLUE = 12'h00F;
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parameter WHITE = 12'hFFF;
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parameter BLACK = 12'h000;
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parameter YELLOW = 12'hFF0;
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parameter CYAN = 12'hF0F;
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parameter ROYAL = 12'h0FF;
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always @( posedge clk ) begin
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if ( enable_game_classic ) begin
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vga_en1 <= 1;
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if ( vgaH >= 130 && vgaH < 310 && vgaV >= 0 && vgaV < 46 ) begin
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addr_info_classic <= ( vgaV - 0 ) * 180 + vgaH - 130;
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end
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else begin
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vga_en1 <= 0;
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end
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end
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else begin
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vga_en1 <= 0;
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end
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end
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classic_info_180_46 u_classic_info_180_46(
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.clka( clk ),
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.addra( addr_info_classic ),
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.ena( 1'b1 ),
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.douta( VGA_data1 )
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);
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always @( posedge clk ) begin
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if ( enable_game_infinity ) begin
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vga_en2 <= 1;
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if ( vgaH >= 130 && vgaH < 310 && vgaV >= 0 && vgaV < 24 ) begin
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addr_info_infinity <= ( vgaV - 0 ) * 180 + vgaH - 130;
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end
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else begin
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vga_en2 <= 0;
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end
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end
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else begin
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vga_en2 <= 0;
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end
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end
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infinity_info_180_24 u_infinity_info_180_24(
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.clka( clk ),
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.addra( addr_info_infinity ),
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.ena( 1'b1 ),
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.douta( VGA_data2 )
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);
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always @( posedge clk ) begin
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if ( enable_game_classic ) begin
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vga_en3 <= 1;
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if ( vgaH >= 320 && vgaH < 480 && vgaV >= 1 && vgaV < 21 && ( vgaH - 320 ) < score_classic[ 3: 0 ] * 20 ) begin
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addr_redflag <= ( vgaH - 320 ) % 20 + ( vgaV - 1 ) * 20;
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end
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else if ( vgaH >= 320 && vgaH < 480 && vgaV >= 24 && vgaV < 44 && ( vgaH - 320 ) < score_classic[ 7: 4 ] * 20 ) begin
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addr_redflag <= ( vgaH - 320 ) % 20 + ( vgaV - 24 ) * 20;
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end
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else begin
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vga_en3 <= 0;
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end
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end
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else begin
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vga_en3 <= 0;
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end
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end
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redflag_20_20 u_redflag_20_20(
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.clka( clk ),
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.addra( addr_redflag ),
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.ena( 1'b1 ),
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.douta( VGA_data3 )
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);
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always @( posedge clk ) begin
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if ( enable_game_infinity ) begin
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vga_en4 <= 1;
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if ( vgaH >= 320 && vgaH < 560 && vgaV >= 5 && vgaV < 20 && ( vgaH - 320 ) < timer * 15 ) begin
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addr_timing <= ( vgaH - 320 ) % 15 + ( vgaV - 5 ) * 15;
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end
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else begin
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vga_en4 <= 0;
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end
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end
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else begin
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vga_en4 <= 0;
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end
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end
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timing_15_15 u_timing_15_15(
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.clka( clk ),
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.addra( addr_timing ),
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.ena( 1'b1 ),
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.douta( VGA_data4 )
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);
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assign VGA_data = ( vga_en1 ? VGA_data1 : 0 ) | ( vga_en2 ? VGA_data2 : 0 ) | ( vga_en3 ? VGA_data3 : 0 ) | ( vga_en4 ? VGA_data4 : 0 ) ;
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endmodule
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