35 lines
814 B
Verilog
35 lines
814 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 01/05/2021 10:41:37 PM
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// Design Name:
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// Module Name: item_random_generator
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module item_random_generator(
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input clk,
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input clk_4Hz,
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input set_finish,
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input enable,
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output reg dout,
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output reg set_require,
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output reg [ 1: 0 ] item_type,
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output [ 10: 0 ] random_xpos,
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output [ 10: 0 ] random_ypos
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);
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endmodule
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