125 lines
3.5 KiB
Verilog
125 lines
3.5 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 12/31/2020 05:00:13 PM
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// Design Name:
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// Module Name: tank_generate
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tank_generate(
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input clk_4Hz,
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input player1_tank_en,
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input player2_tank_en,
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input enermy1_tank_en,
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input enermy2_tank_en,
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input enermy3_tank_en,
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input enermy4_tank_en,
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output reg player1_revive,
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output reg player2_revive,
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output reg enermy1_revive,
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output reg enermy2_revive,
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output reg enermy3_revive,
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output reg enermy4_revive
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);
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reg [ 4: 0 ] cnt_reg_player1, cnt_reg_player2;
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reg [ 4: 0 ] cnt_reg_enermy1, cnt_reg_enermy2, cnt_reg_enermy3, cnt_reg_enermy4;
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initial begin
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cnt_reg_player1 <= 0;
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cnt_reg_player2 <= 0;
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cnt_reg_enermy1 <= 0;
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cnt_reg_enermy2 <= 0;
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cnt_reg_enermy3 <= 0;
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cnt_reg_enermy4 <= 0;
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player1_revive <= 0;
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player2_revive <= 0;
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enermy1_revive <= 0;
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enermy2_revive <= 0;
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enermy3_revive <= 0;
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enermy4_revive <= 0;
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end
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always @( posedge clk_4Hz ) begin
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if ( !player1_tank_en ) begin
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cnt_reg_player1 <= cnt_reg_player1 + 1'b1;
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end
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if ( !player2_tank_en ) begin
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cnt_reg_player2 <= cnt_reg_player2 + 1'b1;
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end
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if ( !enermy1_tank_en ) begin
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cnt_reg_enermy1 <= cnt_reg_enermy1 + 1'b1;
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end
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if ( !enermy2_tank_en ) begin
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cnt_reg_enermy2 <= cnt_reg_enermy2 + 1'b1;
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end
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if ( !enermy3_tank_en ) begin
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cnt_reg_enermy3 <= cnt_reg_enermy3 + 1'b1;
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end
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if ( !enermy4_tank_en ) begin
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cnt_reg_enermy4 <= cnt_reg_enermy4 + 1'b1;
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end
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if ( cnt_reg_player1 >= 12 && cnt_reg_player1 <= 19 ) begin
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cnt_reg_player1 <= cnt_reg_player1 + 1'b1;
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player1_revive <= 1'b1;
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end
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if ( cnt_reg_player2 >= 12 && cnt_reg_player2 <= 19 ) begin
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cnt_reg_player2 <= cnt_reg_player2 + 1'b1;
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player2_revive <= 1'b1;
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end
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if ( cnt_reg_enermy1 >= 12 && cnt_reg_enermy1 <= 19 ) begin
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cnt_reg_enermy1 <= cnt_reg_enermy1 + 1'b1;
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enermy1_revive <= 1'b1;
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end
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if ( cnt_reg_enermy2 >= 12 && cnt_reg_enermy2 <= 19 ) begin
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cnt_reg_enermy2 <= cnt_reg_enermy2 + 1'b1;
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enermy2_revive <= 1'b1;
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end
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if ( cnt_reg_enermy3 >= 12 && cnt_reg_enermy3 <= 19 ) begin
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cnt_reg_enermy3 <= cnt_reg_enermy3 + 1'b1;
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enermy3_revive <= 1'b1;
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end
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if ( cnt_reg_enermy4 >= 12 && cnt_reg_enermy4 <= 19 ) begin
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cnt_reg_enermy4 <= cnt_reg_enermy4 + 1'b1;
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enermy4_revive <= 1'b1;
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end
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if ( cnt_reg_player1 == 20 ) begin
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cnt_reg_player1 <= 0;
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player1_revive <= 1'b0;
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end
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if ( cnt_reg_player2 == 20 ) begin
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cnt_reg_player2 <= 0;
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player2_revive <= 1'b0;
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end
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if ( cnt_reg_enermy1 == 20 ) begin
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cnt_reg_enermy1 <= 0;
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enermy1_revive <= 1'b0;
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end
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if ( cnt_reg_enermy2 == 20 ) begin
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cnt_reg_enermy2 <= 0;
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enermy2_revive <= 1'b0;
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end
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if ( cnt_reg_enermy3 == 20 ) begin
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cnt_reg_enermy3 <= 0;
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enermy3_revive <= 1'b0;
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end
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if ( cnt_reg_enermy4 == 20 ) begin
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cnt_reg_enermy4 <= 0;
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enermy4_revive <= 1'b0;
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end
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end
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endmodule
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