80 lines
1.5 KiB
Verilog
80 lines
1.5 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 01/03/2021 09:20:53 PM
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// Design Name:
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// Module Name: SEG_P2S
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module SEG_P2S( clk,
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data_in,
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ena,
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S_DT,
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S_CLK,
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S_CLR,
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S_EN );
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parameter WIDTH = 64;
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parameter DELAY = 12;
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input clk;
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input ena;
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input [ WIDTH - 1: 0 ] data_in;
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output S_DT;
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output S_CLK;
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output S_CLR;
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output S_EN;
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wire s_clk, s_data;
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reg out_ena;
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assign S_CLK = s_clk;
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assign S_DT = s_data;
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assign S_EN = out_ena;
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assign S_CLR = 1'b1;
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reg [ WIDTH: 0 ] shift;
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reg [ DELAY - 1: 0 ] counter = -1;
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wire s_clk_Ena;
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assign s_clk_Ena = | shift[ WIDTH - 1: 0 ];
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assign s_clk = ~clk && s_clk_Ena;
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assign s_data = shift[ WIDTH ];
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always @ ( posedge clk or negedge ena ) begin
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if ( ena == 0 ) begin
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shift <= 0;
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counter <= 0;
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out_ena <= 1'b1;
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end
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else if ( s_clk_Ena ) begin
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shift <= { shift[ WIDTH - 1: 0 ], 1'b0 };
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end
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else begin
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if ( & counter ) begin
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shift <= { data_in, 1'b1 };
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out_ena <= 1'b0;
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end
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else begin
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out_ena <= 1'b1;
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end
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counter <= counter + 1'b1;
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end
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end
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endmodule
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