37 lines
1.2 KiB
Verilog
37 lines
1.2 KiB
Verilog
`timescale 1ns / 1ps
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module control(
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input clk,
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input [9:0] ps2_output,
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output reg [1:0] player1_dir_feedback,
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output wire player1_fire,
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output wire player1_moving,
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output reg [1:0] player2_dir_feedback,
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output wire player2_fire,
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output wire player2_moving
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);
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assign player1_moving = | ps2_output[3:0];
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assign player2_moving = | ps2_output[7:4];
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assign player1_fire = ps2_output[8];
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assign player2_fire = ps2_output[9];
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always @(posedge clk) begin
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if (ps2_output[0] == 1) player1_dir_feedback <= 2'b00;
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else if(ps2_output[1] == 1) player1_dir_feedback <= 2'b01;
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else if(ps2_output[2] == 1) player1_dir_feedback <= 2'b10;
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else if(ps2_output[3] == 1) player1_dir_feedback <= 2'b11;
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else player1_dir_feedback <= player1_dir_feedback;
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end
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always @(posedge clk) begin
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if (ps2_output[4] == 1) player2_dir_feedback <= 2'b00;
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else if(ps2_output[5] == 1) player2_dir_feedback <= 2'b01;
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else if(ps2_output[6] == 1) player2_dir_feedback <= 2'b10;
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else if(ps2_output[7] == 1) player2_dir_feedback <= 2'b11;
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else player2_dir_feedback <= player2_dir_feedback;
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end
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endmodule
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