126 lines
3.1 KiB
Verilog
126 lines
3.1 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 12/18/2020 01:43:30 PM
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// Design Name:
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// Module Name: vga_driver
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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// VGA 640*480 @ 60Hz
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`define H_FRONT 11'd16
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`define H_SYNC 11'd96
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`define H_BACK 11'd48
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`define H_DISPLAY 11'd640
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`define H_TOTAL 11'd800
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`define V_FRONT 11'd10
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`define V_SYNC 11'd2
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`define V_BACK 11'd33
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`define V_DISPLAY 11'd480
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`define V_TOTAL 11'd525
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module vga_driver(
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input clk_vga,
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input rst_n,
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output vga_en,
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output HSync,
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output VSync,
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output [ 3: 0 ] vgaRed,
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output [ 3: 0 ] vgaGreen,
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output [ 3: 0 ] vgaBlue,
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input [ 11: 0 ] vgaData,
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output [ 10: 0 ] vgaH,
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output [ 10: 0 ] vgaV
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);
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reg [ 10: 0 ] hCnt;
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// Horizontal Sync
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always @( posedge clk_vga or negedge rst_n ) begin
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if ( !rst_n ) begin
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hCnt <= 11'b0;
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end
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else begin
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if ( hCnt < `H_TOTAL - 1'b1 ) begin
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hCnt <= hCnt + 1'b1;
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end
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else begin
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hCnt <= 11'b0;
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end
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end
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end
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assign HSync = ( ( hCnt <= ( `H_DISPLAY + `H_FRONT - 1'b1 ) ) ||
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( hCnt > ( `H_TOTAL - `H_BACK - 1'b1 ) ) ) ? 1'b0 : 1'b1;
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reg [ 10: 0 ] vCnt;
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// Vertical Sync
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always @( posedge clk_vga or negedge rst_n ) begin
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if ( !rst_n ) begin
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vCnt <= 11'b0;
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end
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else begin
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if ( hCnt == `H_DISPLAY - 1'b1 ) begin
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if ( vCnt < `V_TOTAL - 1'b1 ) begin
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vCnt <= vCnt + 1'b1;
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end
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else begin
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vCnt <= 11'b0;
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end
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end
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end
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end
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// Field Sync
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assign VSync = ( ( vCnt <= ( `V_DISPLAY + `V_FRONT - 1'b1 ) ) ||
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( vCnt > ( `V_TOTAL - `V_BACK - 1'b1 ) ) ) ? 1'b0 : 1'b1;
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assign vga_en = ( hCnt < `H_DISPLAY && vCnt < `V_DISPLAY ) ? 1'b1 : 1'b0;
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assign vgaRed[ 3 ] = vga_en ? vgaData[ 3 ] : 1'b0;
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assign vgaRed[ 2 ] = vga_en ? vgaData[ 2 ] : 1'b0;
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assign vgaRed[ 1 ] = vga_en ? vgaData[ 1 ] : 1'b0;
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assign vgaRed[ 0 ] = vga_en ? vgaData[ 0 ] : 1'b0;
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assign vgaGreen[ 3 ] = vga_en ? vgaData[ 7 ] : 1'b0;
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assign vgaGreen[ 2 ] = vga_en ? vgaData[ 6 ] : 1'b0;
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assign vgaGreen[ 1 ] = vga_en ? vgaData[ 5 ] : 1'b0;
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assign vgaGreen[ 0 ] = vga_en ? vgaData[ 4 ] : 1'b0;
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assign vgaBlue[ 3 ] = vga_en ? vgaData[ 11 ] : 1'b0;
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assign vgaBlue[ 2 ] = vga_en ? vgaData[ 10 ] : 1'b0;
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assign vgaBlue[ 1 ] = vga_en ? vgaData[ 9 ] : 1'b0;
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assign vgaBlue[ 0 ] = vga_en ? vgaData[ 8 ] : 1'b0;
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/*
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assign vgaRed = (vgaX > 0) ? 4'b0000 : 4'b0000;
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assign vgaGreen = (vgaX > 0) ? 4'b0000 : 4'b0000;
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assign vgaBlue = (vgaX > 0) ? 4'b1111 : 4'b0000;
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*/
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assign vgaH = ( hCnt < `H_DISPLAY ) ? hCnt : 1'b0;
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assign vgaV = ( vCnt < `V_DISPLAY ) ? vCnt : 1'b0;
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endmodule
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