54 lines
1001 B
Verilog
54 lines
1001 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 12/16/2020 04:48:32 PM
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// Design Name:
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// Module Name: disp_num_sim
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module disp_num_sim;
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reg clk;
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reg RST;
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reg [ 31: 0 ] HEXS;
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reg [ 7: 0 ] points;
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reg [ 7: 0 ] LES;
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wire [ 7: 0 ] AN;
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wire [ 7: 0 ] Segment;
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Disp_Num my_test_Num(
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.clk( clk ),
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.RST( 1'b0 ),
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.HEXS( HEXS ),
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.points( 8'b1 ),
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.LES( 8'b0 ),
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.AN( AN ),
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.Segment( SEGMENT1 )
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);
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initial begin
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clk = 0;
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RST = 0;
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HEXS = 32'b0000_0001_0010_0011_0100_0101_0110_0111;
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end
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always begin
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#10 clk = 1;
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#10 clk = 0;
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end
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endmodule
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