153 lines
3.7 KiB
Verilog
153 lines
3.7 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 12/15/2020 11:04:04 PM
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// Design Name:
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// Module Name: Keyboard_PS2
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module KeyBoard_PS2(
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input clk_in,
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input rst_n_in,
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input key_clk,
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input key_data,
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output reg [ 9: 0 ] out
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);
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reg key_clk_r0 = 1'b1, key_clk_r1 = 1'b1;
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reg key_data_r0 = 1'b1, key_data_r1 = 1'b1;
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reg key_break;
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always @ ( posedge clk_in ) begin
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if ( !rst_n_in ) begin
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key_clk_r0 <= 1'b1;
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key_clk_r1 <= 1'b1;
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key_data_r0 <= 1'b1;
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key_data_r1 <= 1'b1;
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end
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else begin
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key_clk_r0 <= key_clk;
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key_clk_r1 <= key_clk_r0;
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key_data_r0 <= key_data;
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key_data_r1 <= key_data_r0;
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end
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end
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wire key_clk_neg = key_clk_r1 & ( ~key_clk_r0 );
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reg [ 3: 0 ] cnt;
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reg [ 7: 0 ] temp_data;
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always @ ( posedge clk_in ) begin
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if ( !rst_n_in ) begin
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cnt <= 4'd0;
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temp_data <= 8'd0;
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end
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else if ( key_clk_neg ) begin
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if ( cnt >= 4'd10 ) begin
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cnt <= 4'd0;
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end
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else begin
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cnt <= cnt + 1'b1;
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end
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case ( cnt )
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4'd0:
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;
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4'd1:
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temp_data[ 0 ] <= key_data_r1;
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4'd2:
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temp_data[ 1 ] <= key_data_r1;
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4'd3:
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temp_data[ 2 ] <= key_data_r1;
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4'd4:
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temp_data[ 3 ] <= key_data_r1;
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4'd5:
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temp_data[ 4 ] <= key_data_r1;
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4'd6:
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temp_data[ 5 ] <= key_data_r1;
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4'd7:
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temp_data[ 6 ] <= key_data_r1;
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4'd8:
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temp_data[ 7 ] <= key_data_r1;
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4'd9:
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;
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4'd10:
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;
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default:
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;
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endcase
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end
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end
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localparam TANK1_UP = 8'h1D, // W
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TANK1_DOWN = 8'h1B, // S
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TANK1_LEFT = 8'h1C, // A
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TANK1_RIGHT = 8'h23, // D
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TANK1_FIRE = 8'h3B, // J
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// we really ignore the ascii code "E0" because it's useless
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TANK2_UP = 8'h75, // UP
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TANK2_DOWN = 8'h72, // DOWN
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TANK2_LEFT = 8'h6B, // LEFT
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TANK2_RIGHT = 8'h74, //RIFHT
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TANK2_FIRE = 8'h70; // 0
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always @ ( posedge clk_in ) begin
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if ( !rst_n_in ) begin
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key_break <= 1'b0;
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end
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else if ( cnt == 4'd10 && key_clk_neg ) begin
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if ( temp_data == 8'hf0 ) begin
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key_break <= 1'b1;
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end
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else begin
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key_break <= 1'b0;
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end
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case ( temp_data )
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TANK1_UP:
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out[ 0 ] <= ~key_break;
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TANK1_DOWN:
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out[ 1 ] <= ~key_break;
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TANK1_LEFT :
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out[ 2 ] <= ~key_break;
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TANK1_RIGHT:
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out[ 3 ] <= ~key_break;
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TANK2_UP:
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out[ 4 ] <= ~key_break;
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TANK2_DOWN:
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out[ 5 ] <= ~key_break;
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TANK2_LEFT:
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out[ 6 ] <= ~key_break;
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TANK2_RIGHT:
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out[ 7 ] <= ~key_break;
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TANK1_FIRE:
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out[ 8 ] <= ~key_break;
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TANK2_FIRE:
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out[ 9 ] <= ~key_break;
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default:
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;
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endcase
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end
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end
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endmodule
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