87 lines
2.3 KiB
Verilog
87 lines
2.3 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 12/29/2020 03:54:49 PM
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// Design Name:
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// Module Name: SegAndLed
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module SegAndLed(
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input wire clk,
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input wire [ 2: 0 ] mode,
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input wire [ 15: 0 ] led_classic,
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input wire [ 15: 0 ] led_infinity,
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input wire [ 7: 0 ] score_classic,
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input wire [ 7: 0 ] score_infinity,
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input wire [ 31: 0 ] default_num, //when mode is 0
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input wire [ 4: 0 ] timer,
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input wire enable_game_classic,
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input wire enable_game_infinity,
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input wire player1_tank_en,
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input wire player2_tank_en,
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output wire [ 7: 0 ] AN ,
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output wire [ 7: 0 ] Segment,
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output reg [ 15: 0 ] LED
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);
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reg [ 31: 0 ] num;
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initial begin
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LED <= 0;
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num <= 0;
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end
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always @( posedge clk ) begin
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if ( enable_game_classic == 0 && enable_game_infinity == 0 ) begin
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LED <= 0;
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end
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else begin
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if ( enable_game_classic ) begin
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LED <= led_classic;
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end
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else if ( enable_game_infinity ) begin
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LED <= led_infinity;
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end
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end
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end
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always @( posedge clk ) begin
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case ( mode )
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2'b00:
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num <= default_num;
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2'b01:
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num <= { 4'b1010, 3'b000, player1_tank_en, score_classic[ 3: 0 ], 4'b000, 4'b1011, 3'b000, player2_tank_en, score_classic[ 7: 4 ], 4'b000 };
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2'b10:
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num <= { 4'b1010, 3'b000, player1_tank_en, 3'b000, player2_tank_en, score_infinity[ 3: 0 ], 4'b1011, score_infinity[ 7: 4 ], 3'b000, timer };
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2'b11:
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num <= { 4'b1000, 4'b1000, 4'b1000, 4'b1000, 4'b1000, 4'b1000, 4'b1000, 4'b1000 };
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default num <= 0;
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endcase
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end
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Disp_Num my_Disp_Num(
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.clk( clk ),
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.RST( 1'b0 ),
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.HEXS( num ),
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.points( 8'b1 ),
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.LES( 8'b0 ),
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.AN( AN ),
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.Segment( Segment )
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);
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endmodule
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