105 lines
2.7 KiB
Verilog
105 lines
2.7 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 12/31/2020 03:55:24 PM
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// Design Name:
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// Module Name: cal_score
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module cal_score(
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input clk,
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input reset_n,
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input enermy1_tank_en,
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input enermy2_tank_en,
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input enermy3_tank_en,
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input enermy4_tank_en,
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input player1_scored,
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input player2_scored,
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output reg [ 3: 0 ] scorea1,
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output reg [ 3: 0 ] scorea2,
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output reg [ 3: 0 ] scoreb1,
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output reg [ 3: 0 ] scoreb2,
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output reg [ 3: 0 ] scorec1,
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output reg [ 3: 0 ] scorec2,
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output reg [ 3: 0 ] scored1,
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output reg [ 3: 0 ] scored2
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);
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reg enermy1_tank_en_last, enermy2_tank_en_last, enermy3_tank_en_last, enermy4_tank_en_last;
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initial begin
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scorea1 <= 0;
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scorea2 <= 0;
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scoreb1 <= 0;
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scoreb2 <= 0;
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scorec1 <= 0;
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scorec2 <= 0;
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scored1 <= 0;
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scored2 <= 0;
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end
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always @( posedge clk ) begin
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if ( !reset_n ) begin
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scorea1 <= 0;
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scorea2 <= 0;
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scoreb1 <= 0;
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scoreb2 <= 0;
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scorec1 <= 0;
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scorec2 <= 0;
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scored1 <= 0;
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scored2 <= 0;
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end
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else begin
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if ( enermy1_tank_en_last && ~enermy1_tank_en ) begin
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if ( player1_scored ) begin
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scorea1 <= scorea1 + 1'b1;
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end
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else begin
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scorea2 <= scorea2 + 1'b1;
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end
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end
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else if ( enermy2_tank_en_last && ~enermy2_tank_en ) begin
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if ( player1_scored ) begin
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scoreb1 <= scoreb1 + 1'b1;
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end
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else begin
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scoreb2 <= scoreb2 + 1'b1;
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end
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end
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else if ( enermy3_tank_en_last && ~enermy3_tank_en ) begin
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if ( player1_scored ) begin
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scorec1 <= scorec1 + 1'b1;
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end
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else begin
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scorec2 <= scorec2 + 1'b1;
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end
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end
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else if ( enermy4_tank_en_last && ~enermy4_tank_en ) begin
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if ( player1_scored ) begin
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scored1 <= scored1 + 1'b1;
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end
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else begin
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scored2 <= scored2 + 1'b1;
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end
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end
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end
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enermy1_tank_en_last <= enermy1_tank_en;
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enermy2_tank_en_last <= enermy2_tank_en;
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enermy3_tank_en_last <= enermy3_tank_en;
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enermy4_tank_en_last <= enermy4_tank_en;
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end
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endmodule
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