110 lines
2.0 KiB
Verilog
110 lines
2.0 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 12/16/2020 02:29:20 PM
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// Design Name:
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// Module Name: clock
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module clock(
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input wire clk_100MHz,
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output reg clk_2Hz,
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output reg clk_4Hz,
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output reg clk_8Hz,
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output reg clk_10ms
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);
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reg [ 27: 0 ] cnt_2Hz, cnt_4Hz, cnt_8Hz, cnt_10ms;
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reg [ 27: 0 ] ending_4Hz;
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initial begin
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cnt_4Hz <= 0;
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cnt_2Hz <= 0;
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cnt_8Hz <= 0;
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cnt_10ms <= 0;
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end
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//calculate 2Hz clock
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always @( posedge clk_100MHz ) begin
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cnt_2Hz <= cnt_2Hz + 1'b1;
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if ( cnt_2Hz >= 25000000 ) begin
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clk_2Hz <= 1;
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end
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else begin
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clk_2Hz <= 0;
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end
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if ( cnt_2Hz >= 50000000 ) begin
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cnt_2Hz <= 28'b0;
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// clk_2Hz <= 0;
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end
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end
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//calculate 4Hz clock
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always @( posedge clk_100MHz ) begin
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cnt_4Hz <= cnt_4Hz + 1'b1;
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if ( cnt_4Hz >= ending_4Hz ) begin
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clk_4Hz <= 1;
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end
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else begin
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clk_4Hz <= 0;
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end
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if ( cnt_4Hz >= ending_4Hz * 2 ) begin
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cnt_4Hz <= 28'b0;
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// clk_4Hz <= 0;
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end
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end
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//calculate 8Hz clock
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always @( posedge clk_100MHz ) begin
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cnt_8Hz <= cnt_8Hz + 1'b1;
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if ( cnt_8Hz >= 6250000 ) begin
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clk_8Hz <= 1;
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end
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else begin
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clk_8Hz <= 0;
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end
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if ( cnt_8Hz >= 12500000 ) begin
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cnt_8Hz <= 28'b0;
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// clk_8Hz <= 0;
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end
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end
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always @( posedge clk_100MHz ) begin
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ending_4Hz <= 12500000;
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end
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always @( posedge clk_100MHz ) begin
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cnt_10ms <= cnt_10ms + 1'b1;
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if ( cnt_10ms >= 500_000 ) begin
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clk_10ms <= 1;
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end
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else begin
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clk_10ms <= 0;
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end
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if ( cnt_10ms >= 1000_000 ) begin
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cnt_10ms <= 0;
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end
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end
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endmodule
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