47 lines
946 B
Verilog
47 lines
946 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 12/18/2020 05:09:19 PM
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// Design Name:
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// Module Name: tank_data_selector
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tank_data_selector(
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input clk,
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input [11:0] UP,
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input [11:0] DOWN,
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input [11:0] LEFT,
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input [11:0] RIGHT,
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input [1:0] Dir,
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output reg [11:0] tankData
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);
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always @(posedge clk) begin
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case(Dir)
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2'b00:
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tankData <= UP;
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2'b01:
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tankData <= DOWN;
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2'b10:
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tankData <= LEFT;
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2'b11:
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tankData <= RIGHT;
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endcase
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end
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endmodule
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