基本全部完成，还剩选择生命和时间
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2019.2:
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* Version 8.4 (Rev. 4)
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* Feature Enhancement: Read Latency parameters exposed to IP GUI for URAM configurations
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2019.1.3:
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* Version 8.4 (Rev. 3)
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* No changes
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2019.1.2:
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* Version 8.4 (Rev. 3)
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* No changes
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2019.1.1:
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* Version 8.4 (Rev. 3)
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* No changes
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2019.1:
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* Version 8.4 (Rev. 3)
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* General: Internal device family change, no functional changes
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2018.3.1:
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* Version 8.4 (Rev. 2)
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* No changes
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2018.3:
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* Version 8.4 (Rev. 2)
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* Feature Enhancement: Read Latency Support added for URAM when selected through IP Integrator
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* Other: Power Calculations disabled for URAM primitives in IP GUI, no functional changes
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* Other: Internal device family change, no functional changes
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2018.2:
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* Version 8.4 (Rev. 1)
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* No changes
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2018.1:
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* Version 8.4 (Rev. 1)
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* No changes
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2017.4:
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* Version 8.4 (Rev. 1)
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* General: Write depth shown in IP GUI is now dependent on number of BRAMs available in a chosen device, no functional changes
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2017.3:
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* Version 8.4
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* General: Safety Circuit option is enabled by default if reset option in any one port is enabled
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2017.2:
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* Version 8.3 (Rev. 6)
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* No changes
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2017.1:
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* Version 8.3 (Rev. 6)
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* General: Internal device family change, no functional changes
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* General: When common_clock is selected clkb is internally connected to clka, but the interface remains same to support the backword compatiability. User make sure of connecting the both the clocks to same clock source when in common_clock mode
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2016.4:
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* Version 8.3 (Rev. 5)
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* General: Fixes for behavioral Model issues when built-IN ECC is enabled (to be consistent with RTL)
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2016.3:
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* Version 8.3 (Rev. 4)
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* Feature Enhancement: URAM addressing updates while calling XPM_Memory when 32-bit addressing is enabled
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* Other: Enable support for future devices
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* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
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2016.2:
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* Version 8.3 (Rev. 3)
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* updated the IP,not to set WRITE_DEPTH parameter to 8192 everytime when the mode is switched to BRAM_Controller
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* Updated the IP to support the device package changes
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2016.1:
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* Version 8.3 (Rev. 2)
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* Updated the IP to deliver only verilog behavioral model
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* Updated the IP to support UltraRAM in IP Integrator
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* Updated the IP to support the device package changes
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2015.4.2:
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* Version 8.3 (Rev. 1)
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* No changes
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2015.4.1:
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* Version 8.3 (Rev. 1)
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* No changes
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2015.4:
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* Version 8.3 (Rev. 1)
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* Updated the IP to support the device package changes
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2015.3:
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* Version 8.3
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* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
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* New ports rsta_busy and rstb_busy are added to enable the safety circuitry to minimize the occurrence of BRAM data corruption
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* Simulation models are delivered in VHDL only
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2015.2.1:
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* Version 8.2 (Rev. 5)
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* No changes
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2015.2:
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* Version 8.2 (Rev. 5)
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* No changes
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2015.1:
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* Version 8.2 (Rev. 5)
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* Delivering non encrypted behavioral models
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* Supported memory depth is increased up to 1M words
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* Added the power saving feature (RDADDRCHG) for ultrascale devices
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* Supported devices and production status are now determined automatically, to simplify support for future devices
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2014.4.1:
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* Version 8.2 (Rev. 4)
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* Updated the IP to support the device package changes
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2014.4:
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* Version 8.2 (Rev. 3)
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* Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
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* Added support for 7-series Automotive (XA) and Defense Grade (XQ) devices
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* Internal device family change, no functional changes
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2014.3:
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* Version 8.2 (Rev. 2)
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* Fixed the Memory Resource Doubling issue in Simple Dual Port RAM when aspect ratio is used
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* Fixed the GUI crash in Simple Dual Port RAM
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* Added support of all write modes in Simple Dual Port RAM when ECC is not used
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* Increased the supported depth to a maximum value of 256k
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2014.2:
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* Version 8.2 (Rev. 1)
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* Updated the GUI tool tip for Byte write enable in the page-1 of block memory generator GUI
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2014.1:
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* Version 8.2
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* Added support of the cascaded Primitives of widths 1 and 2 for ultra-scale devices
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* Added support of the ECCPIPE register in the built-in ecc mode for ultra-scale devices
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* Added support of the dynamic power saving for ultra-scale devices
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* Improved timing efficiency in the IP Integrator by minimizing the use of output mux for the 7-series devices
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* Internal device family name change, no functional changes
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2013.4:
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* Version 8.1
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* The Primitive output registers are made "ON" by default in the stand alone mode
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* Added cascaded support for ultrascale devices to construct 64Kx1 primitive by using two 32Kx1 primitives
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* Added support for ultrascale devices
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2013.3:
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* Version 8.0 (Rev. 2)
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* Added parameter "CTRL_ECC_ALGO" for supporting ECC in IP Integrator.
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* Improved GUI speed and responsivness, no functional changes
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* Reduced synthesis and simulation warnings
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* Added support for Cadence IES and Synopsys VCS simulators
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* Changed the default option of ENABLE PORT TYPE to "USE_ENA_PIN"
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* Changed BRAM Interface DIN and DOUT to match bus interface directions.
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2013.2:
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* Version 8.0 (Rev. 1)
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* No Changes
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2013.1:
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* Version 8.0
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* Native Vivado Release
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* There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1.
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(c) Copyright 2002 - 2019 Xilinx, Inc. All rights reserved.
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This file contains confidential and proprietary information
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of Xilinx, Inc. and is protected under U.S. and
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international copyright and other intellectual property
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laws.
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DISCLAIMER
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This disclaimer is not a license and does not grant any
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rights to the materials distributed herewith. Except as
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otherwise provided in a valid license issued to you by
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Xilinx, and to the maximum extent permitted by applicable
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law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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(2) Xilinx shall not be liable (whether in contract or tort,
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including negligence, or under any other theory of
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liability) for any loss or damage of any kind or nature
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related to, arising under or in connection with these
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materials, including for any direct, or any indirect,
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special, incidental, or consequential loss or damage
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(including loss of data, profits, goodwill, or any type of
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loss or damage suffered as a result of any action brought
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by a third party) even if such damage or loss was
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reasonably foreseeable or Xilinx had been advised of the
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possibility of the same.
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CRITICAL APPLICATIONS
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Xilinx products are not designed or intended to be fail-
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safe, or for use in any application requiring fail-safe
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performance, such as life-support or safety devices or
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systems, Class III medical devices, nuclear facilities,
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applications related to the deployment of airbags, or any
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other applications that could lead to death, personal
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injury, or severe property or environmental damage
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(individually and collectively, "Critical
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Applications"). Customer assumes the sole risk and
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liability of any use of Xilinx products in Critical
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Applications, subject only to applicable laws and
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regulations governing limitations on product liability.
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THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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PART OF THIS FILE AT ALL TIMES.
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||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP : 2.5432 mW</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">artix7</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">lightning_20_20.mem</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">lightning_20_20.mif</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">3</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">400</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">400</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">12</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">12</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">400</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">400</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">12</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">12</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">artix7</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">../../../pic/lightning_20_20.coe</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">lightning_20_20</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Use_ENA_Pin</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Single_Port_ROM</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">WRITE_FIRST</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">WRITE_FIRST</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_A">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_B">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">12</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">12</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">400</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">12</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">12</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a100t</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">csg324</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||||
|
</spirit:configurableElementValues>
|
||||||
|
<spirit:vendorExtensions>
|
||||||
|
<xilinx:componentInstanceExtensions>
|
||||||
|
<xilinx:configElementInfos>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coe_File" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Load_Init_File" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_A_Write_Rate" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
|
||||||
|
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
|
||||||
|
</xilinx:configElementInfos>
|
||||||
|
</xilinx:componentInstanceExtensions>
|
||||||
|
</spirit:vendorExtensions>
|
||||||
|
</spirit:componentInstance>
|
||||||
|
</spirit:componentInstances>
|
||||||
|
</spirit:design>
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,55 @@
|
||||||
|
################################################################################
|
||||||
|
#
|
||||||
|
# (c) Copyright 2002 - 2013 Xilinx, Inc. All rights reserved.
|
||||||
|
#
|
||||||
|
# This file contains confidential and proprietary information
|
||||||
|
# of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
# international copyright and other intellectual property
|
||||||
|
# laws.
|
||||||
|
#
|
||||||
|
# DISCLAIMER
|
||||||
|
# This disclaimer is not a license and does not grant any
|
||||||
|
# rights to the materials distributed herewith. Except as
|
||||||
|
# otherwise provided in a valid license issued to you by
|
||||||
|
# Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
# including negligence, or under any other theory of
|
||||||
|
# liability) for any loss or damage of any kind or nature
|
||||||
|
# related to, arising under or in connection with these
|
||||||
|
# materials, including for any direct, or any indirect,
|
||||||
|
# special, incidental, or consequential loss or damage
|
||||||
|
# (including loss of data, profits, goodwill, or any type of
|
||||||
|
# loss or damage suffered as a result of any action brought
|
||||||
|
# by a third party) even if such damage or loss was
|
||||||
|
# reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
# possibility of the same.
|
||||||
|
#
|
||||||
|
# CRITICAL APPLICATIONS
|
||||||
|
# Xilinx products are not designed or intended to be fail-
|
||||||
|
# safe, or for use in any application requiring fail-safe
|
||||||
|
# performance, such as life-support or safety devices or
|
||||||
|
# systems, Class III medical devices, nuclear facilities,
|
||||||
|
# applications related to the deployment of airbags, or any
|
||||||
|
# other applications that could lead to death, personal
|
||||||
|
# injury, or severe property or environmental damage
|
||||||
|
# (individually and collectively, "Critical
|
||||||
|
# Applications"). Customer assumes the sole risk and
|
||||||
|
# liability of any use of Xilinx products in Critical
|
||||||
|
# Applications, subject only to applicable laws and
|
||||||
|
# regulations governing limitations on product liability.
|
||||||
|
#
|
||||||
|
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
# PART OF THIS FILE AT ALL TIMES.
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
# Core Period Constraint. This constraint can be modified, and is
|
||||||
|
# valid as long as it is met after place and route.
|
||||||
|
create_clock -name "TS_CLKA" -period 20.0 [ get_ports clka ]
|
||||||
|
set_property HD.CLK_SRC BUFGCTRL_X0Y0 [ get_ports clka ]
|
||||||
|
################################################################################
|
||||||
|
|
@ -0,0 +1,755 @@
|
||||||
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
|
// Date : Wed Jan 6 17:21:01 2021
|
||||||
|
// Host : cxz666 running 64-bit major release (build 9200)
|
||||||
|
// Command : write_verilog -force -mode funcsim
|
||||||
|
// e:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/lightning_20_20/lightning_20_20_sim_netlist.v
|
||||||
|
// Design : lightning_20_20
|
||||||
|
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||||
|
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
// Device : xc7a100tcsg324-1
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
`timescale 1 ps / 1 ps
|
||||||
|
|
||||||
|
(* CHECK_LICENSE_TYPE = "lightning_20_20,blk_mem_gen_v8_4_4,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2019.2" *)
|
||||||
|
(* NotValidForBitStream *)
|
||||||
|
module lightning_20_20
|
||||||
|
(clka,
|
||||||
|
ena,
|
||||||
|
addra,
|
||||||
|
douta);
|
||||||
|
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) input clka;
|
||||||
|
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
|
||||||
|
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [8:0]addra;
|
||||||
|
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [11:0]douta;
|
||||||
|
|
||||||
|
wire [8:0]addra;
|
||||||
|
wire clka;
|
||||||
|
wire [11:0]douta;
|
||||||
|
wire ena;
|
||||||
|
wire NLW_U0_dbiterr_UNCONNECTED;
|
||||||
|
wire NLW_U0_rsta_busy_UNCONNECTED;
|
||||||
|
wire NLW_U0_rstb_busy_UNCONNECTED;
|
||||||
|
wire NLW_U0_s_axi_arready_UNCONNECTED;
|
||||||
|
wire NLW_U0_s_axi_awready_UNCONNECTED;
|
||||||
|
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
|
||||||
|
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
|
||||||
|
wire NLW_U0_s_axi_rlast_UNCONNECTED;
|
||||||
|
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
|
||||||
|
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
|
||||||
|
wire NLW_U0_s_axi_wready_UNCONNECTED;
|
||||||
|
wire NLW_U0_sbiterr_UNCONNECTED;
|
||||||
|
wire [11:0]NLW_U0_doutb_UNCONNECTED;
|
||||||
|
wire [8:0]NLW_U0_rdaddrecc_UNCONNECTED;
|
||||||
|
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
|
||||||
|
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
|
||||||
|
wire [8:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
|
||||||
|
wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
|
||||||
|
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
|
||||||
|
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
|
||||||
|
|
||||||
|
(* C_ADDRA_WIDTH = "9" *)
|
||||||
|
(* C_ADDRB_WIDTH = "9" *)
|
||||||
|
(* C_ALGORITHM = "1" *)
|
||||||
|
(* C_AXI_ID_WIDTH = "4" *)
|
||||||
|
(* C_AXI_SLAVE_TYPE = "0" *)
|
||||||
|
(* C_AXI_TYPE = "1" *)
|
||||||
|
(* C_BYTE_SIZE = "9" *)
|
||||||
|
(* C_COMMON_CLK = "0" *)
|
||||||
|
(* C_COUNT_18K_BRAM = "1" *)
|
||||||
|
(* C_COUNT_36K_BRAM = "0" *)
|
||||||
|
(* C_CTRL_ECC_ALGO = "NONE" *)
|
||||||
|
(* C_DEFAULT_DATA = "0" *)
|
||||||
|
(* C_DISABLE_WARN_BHV_COLL = "0" *)
|
||||||
|
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
|
||||||
|
(* C_ELABORATION_DIR = "./" *)
|
||||||
|
(* C_ENABLE_32BIT_ADDRESS = "0" *)
|
||||||
|
(* C_EN_DEEPSLEEP_PIN = "0" *)
|
||||||
|
(* C_EN_ECC_PIPE = "0" *)
|
||||||
|
(* C_EN_RDADDRA_CHG = "0" *)
|
||||||
|
(* C_EN_RDADDRB_CHG = "0" *)
|
||||||
|
(* C_EN_SAFETY_CKT = "0" *)
|
||||||
|
(* C_EN_SHUTDOWN_PIN = "0" *)
|
||||||
|
(* C_EN_SLEEP_PIN = "0" *)
|
||||||
|
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.5432 mW" *)
|
||||||
|
(* C_FAMILY = "artix7" *)
|
||||||
|
(* C_HAS_AXI_ID = "0" *)
|
||||||
|
(* C_HAS_ENA = "1" *)
|
||||||
|
(* C_HAS_ENB = "0" *)
|
||||||
|
(* C_HAS_INJECTERR = "0" *)
|
||||||
|
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
|
||||||
|
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
|
||||||
|
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
|
||||||
|
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
|
||||||
|
(* C_HAS_REGCEA = "0" *)
|
||||||
|
(* C_HAS_REGCEB = "0" *)
|
||||||
|
(* C_HAS_RSTA = "0" *)
|
||||||
|
(* C_HAS_RSTB = "0" *)
|
||||||
|
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
|
||||||
|
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
|
||||||
|
(* C_INITA_VAL = "0" *)
|
||||||
|
(* C_INITB_VAL = "0" *)
|
||||||
|
(* C_INIT_FILE = "lightning_20_20.mem" *)
|
||||||
|
(* C_INIT_FILE_NAME = "lightning_20_20.mif" *)
|
||||||
|
(* C_INTERFACE_TYPE = "0" *)
|
||||||
|
(* C_LOAD_INIT_FILE = "1" *)
|
||||||
|
(* C_MEM_TYPE = "3" *)
|
||||||
|
(* C_MUX_PIPELINE_STAGES = "0" *)
|
||||||
|
(* C_PRIM_TYPE = "1" *)
|
||||||
|
(* C_READ_DEPTH_A = "400" *)
|
||||||
|
(* C_READ_DEPTH_B = "400" *)
|
||||||
|
(* C_READ_LATENCY_A = "1" *)
|
||||||
|
(* C_READ_LATENCY_B = "1" *)
|
||||||
|
(* C_READ_WIDTH_A = "12" *)
|
||||||
|
(* C_READ_WIDTH_B = "12" *)
|
||||||
|
(* C_RSTRAM_A = "0" *)
|
||||||
|
(* C_RSTRAM_B = "0" *)
|
||||||
|
(* C_RST_PRIORITY_A = "CE" *)
|
||||||
|
(* C_RST_PRIORITY_B = "CE" *)
|
||||||
|
(* C_SIM_COLLISION_CHECK = "ALL" *)
|
||||||
|
(* C_USE_BRAM_BLOCK = "0" *)
|
||||||
|
(* C_USE_BYTE_WEA = "0" *)
|
||||||
|
(* C_USE_BYTE_WEB = "0" *)
|
||||||
|
(* C_USE_DEFAULT_DATA = "0" *)
|
||||||
|
(* C_USE_ECC = "0" *)
|
||||||
|
(* C_USE_SOFTECC = "0" *)
|
||||||
|
(* C_USE_URAM = "0" *)
|
||||||
|
(* C_WEA_WIDTH = "1" *)
|
||||||
|
(* C_WEB_WIDTH = "1" *)
|
||||||
|
(* C_WRITE_DEPTH_A = "400" *)
|
||||||
|
(* C_WRITE_DEPTH_B = "400" *)
|
||||||
|
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
|
||||||
|
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
||||||
|
(* C_WRITE_WIDTH_A = "12" *)
|
||||||
|
(* C_WRITE_WIDTH_B = "12" *)
|
||||||
|
(* C_XDEVICEFAMILY = "artix7" *)
|
||||||
|
(* downgradeipidentifiedwarnings = "yes" *)
|
||||||
|
lightning_20_20_blk_mem_gen_v8_4_4 U0
|
||||||
|
(.addra(addra),
|
||||||
|
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||||
|
.clka(clka),
|
||||||
|
.clkb(1'b0),
|
||||||
|
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
|
||||||
|
.deepsleep(1'b0),
|
||||||
|
.dina({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||||
|
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||||
|
.douta(douta),
|
||||||
|
.doutb(NLW_U0_doutb_UNCONNECTED[11:0]),
|
||||||
|
.eccpipece(1'b0),
|
||||||
|
.ena(ena),
|
||||||
|
.enb(1'b0),
|
||||||
|
.injectdbiterr(1'b0),
|
||||||
|
.injectsbiterr(1'b0),
|
||||||
|
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[8:0]),
|
||||||
|
.regcea(1'b0),
|
||||||
|
.regceb(1'b0),
|
||||||
|
.rsta(1'b0),
|
||||||
|
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
|
||||||
|
.rstb(1'b0),
|
||||||
|
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
|
||||||
|
.s_aclk(1'b0),
|
||||||
|
.s_aresetn(1'b0),
|
||||||
|
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||||
|
.s_axi_arburst({1'b0,1'b0}),
|
||||||
|
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
|
||||||
|
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||||
|
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
|
||||||
|
.s_axi_arsize({1'b0,1'b0,1'b0}),
|
||||||
|
.s_axi_arvalid(1'b0),
|
||||||
|
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||||
|
.s_axi_awburst({1'b0,1'b0}),
|
||||||
|
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
|
||||||
|
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||||
|
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
|
||||||
|
.s_axi_awsize({1'b0,1'b0,1'b0}),
|
||||||
|
.s_axi_awvalid(1'b0),
|
||||||
|
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
|
||||||
|
.s_axi_bready(1'b0),
|
||||||
|
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
|
||||||
|
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
|
||||||
|
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
|
||||||
|
.s_axi_injectdbiterr(1'b0),
|
||||||
|
.s_axi_injectsbiterr(1'b0),
|
||||||
|
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[8:0]),
|
||||||
|
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
|
||||||
|
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
|
||||||
|
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
|
||||||
|
.s_axi_rready(1'b0),
|
||||||
|
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
|
||||||
|
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
|
||||||
|
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
|
||||||
|
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||||
|
.s_axi_wlast(1'b0),
|
||||||
|
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
|
||||||
|
.s_axi_wstrb(1'b0),
|
||||||
|
.s_axi_wvalid(1'b0),
|
||||||
|
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
|
||||||
|
.shutdown(1'b0),
|
||||||
|
.sleep(1'b0),
|
||||||
|
.wea(1'b0),
|
||||||
|
.web(1'b0));
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
|
||||||
|
module lightning_20_20_blk_mem_gen_generic_cstr
|
||||||
|
(douta,
|
||||||
|
clka,
|
||||||
|
ena,
|
||||||
|
addra);
|
||||||
|
output [11:0]douta;
|
||||||
|
input clka;
|
||||||
|
input ena;
|
||||||
|
input [8:0]addra;
|
||||||
|
|
||||||
|
wire [8:0]addra;
|
||||||
|
wire clka;
|
||||||
|
wire [11:0]douta;
|
||||||
|
wire ena;
|
||||||
|
|
||||||
|
lightning_20_20_blk_mem_gen_prim_width \ramloop[0].ram.r
|
||||||
|
(.addra(addra),
|
||||||
|
.clka(clka),
|
||||||
|
.douta(douta),
|
||||||
|
.ena(ena));
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
|
||||||
|
module lightning_20_20_blk_mem_gen_prim_width
|
||||||
|
(douta,
|
||||||
|
clka,
|
||||||
|
ena,
|
||||||
|
addra);
|
||||||
|
output [11:0]douta;
|
||||||
|
input clka;
|
||||||
|
input ena;
|
||||||
|
input [8:0]addra;
|
||||||
|
|
||||||
|
wire [8:0]addra;
|
||||||
|
wire clka;
|
||||||
|
wire [11:0]douta;
|
||||||
|
wire ena;
|
||||||
|
|
||||||
|
lightning_20_20_blk_mem_gen_prim_wrapper_init \prim_init.ram
|
||||||
|
(.addra(addra),
|
||||||
|
.clka(clka),
|
||||||
|
.douta(douta),
|
||||||
|
.ena(ena));
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
|
||||||
|
module lightning_20_20_blk_mem_gen_prim_wrapper_init
|
||||||
|
(douta,
|
||||||
|
clka,
|
||||||
|
ena,
|
||||||
|
addra);
|
||||||
|
output [11:0]douta;
|
||||||
|
input clka;
|
||||||
|
input ena;
|
||||||
|
input [8:0]addra;
|
||||||
|
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8 ;
|
||||||
|
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9 ;
|
||||||
|
wire [8:0]addra;
|
||||||
|
wire clka;
|
||||||
|
wire [11:0]douta;
|
||||||
|
wire ena;
|
||||||
|
|
||||||
|
(* box_type = "PRIMITIVE" *)
|
||||||
|
RAMB18E1 #(
|
||||||
|
.DOA_REG(1),
|
||||||
|
.DOB_REG(1),
|
||||||
|
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INIT_00(256'h0506070706070507070707070707070707070707070707070707070707070707),
|
||||||
|
.INIT_01(256'h0707070707070707060705070506070702050506000405050004050502050506),
|
||||||
|
.INIT_02(256'h0707070707070707070707070707070707070707070707070707070707070707),
|
||||||
|
.INIT_03(256'h0301070606070307060703070301070600000305000405050105010505020507),
|
||||||
|
.INIT_04(256'h0707070707070707070707070707070705020507010501050004050500000305),
|
||||||
|
.INIT_05(256'h0707070705020507030107060004070500040505020505060707070707070707),
|
||||||
|
.INIT_06(256'h0004070503010706050205070707070707070707070707070707070707070707),
|
||||||
|
.INIT_07(256'h0507010700000505070707070707070707070707070707070205050600040505),
|
||||||
|
.INIT_08(256'h0703050707070707070707070707070707070707070707070707070707070707),
|
||||||
|
.INIT_09(256'h0707070707070707000005050507010707070707070707070707070707070707),
|
||||||
|
.INIT_0A(256'h0707070707070707070707070707070706070307000005050707070707070707),
|
||||||
|
.INIT_0B(256'h0707070707070707070707070707070705060707070707070707070707070707),
|
||||||
|
.INIT_0C(256'h0607030700000505070707070707070707070707070707070000050506070307),
|
||||||
|
.INIT_0D(256'h0502050703050706070707070707070707070707070707070707070707070707),
|
||||||
|
.INIT_0E(256'h0707070707070707000005050607030707070707070707070707070707070707),
|
||||||
|
.INIT_0F(256'h0707070707070707070707070707070706070307000005050707070707070707),
|
||||||
|
.INIT_10(256'h0707070707070707070707070707070705060707000005050507010707070707),
|
||||||
|
.INIT_11(256'h0607030700040505070707070707070707070707070707070000050506070307),
|
||||||
|
.INIT_12(256'h0607030700000305000407050607030707070707070707070707070707070707),
|
||||||
|
.INIT_13(256'h0707070707070707000405050607030707070707070707070707070707070707),
|
||||||
|
.INIT_14(256'h0707070707070707070707070707070706070307000405050707070707070707),
|
||||||
|
.INIT_15(256'h0707070707070707070707070707070707030507000003050000030502010306),
|
||||||
|
.INIT_16(256'h0607030700040505070707070707070707070707070707070004050506070307),
|
||||||
|
.INIT_17(256'h0105030600000305000003050000030503060106070707070707070707070707),
|
||||||
|
.INIT_18(256'h0707070707070707000405050607030707070707070707070607030702010306),
|
||||||
|
.INIT_19(256'h0201030606070307070707070707070706070307000405050707070707070707),
|
||||||
|
.INIT_1A(256'h0707070707070707070707070306010600000305000003050000030501050306),
|
||||||
|
.INIT_1B(256'h0607030700040705070707070707070707070707070707070004050506070307),
|
||||||
|
.INIT_1C(256'h0201030600000305000003050703050707070707070707070707070707070707),
|
||||||
|
.INIT_1D(256'h0707070707070707000407050607030707070707070707070707070707070707),
|
||||||
|
.INIT_1E(256'h0707070707070707070707070707070706070307000407050707070707070707),
|
||||||
|
.INIT_1F(256'h0707070707070707070707070707070706070307000407050000030506070307),
|
||||||
|
.INIT_20(256'h0406030601050106070707070707070707070707070707070004070506070307),
|
||||||
|
.INIT_21(256'h0707070705070107000005050507010707070707070707070707070707070707),
|
||||||
|
.INIT_22(256'h0707070707070707010501060406030607070707070707070707070707070707),
|
||||||
|
.INIT_23(256'h0707070707070707070707070707070700040505040203060707070707070707),
|
||||||
|
.INIT_24(256'h0707070707070707070707070707070707070707070707070305070605020507),
|
||||||
|
.INIT_25(256'h0201030607070707070707070707070707070707070707070402030600040505),
|
||||||
|
.INIT_26(256'h0707070707070707070707070506070707070707070707070607030701000705),
|
||||||
|
.INIT_27(256'h0707070707070707070707070201030601000705060703070707070707070707),
|
||||||
|
.INIT_28(256'h0707070705020707000405050100070507070707070707070707070707070707),
|
||||||
|
.INIT_29(256'h0105010500040505050607070707070707070707070707070707070707030707),
|
||||||
|
.INIT_2A(256'h0707070707070707070707070707070707070707070707070707070707070707),
|
||||||
|
.INIT_2B(256'h0607030707070707070707070603010702050506000405050402030607070707),
|
||||||
|
.INIT_2C(256'h0707070707070707070707070707070707070707040603060100070503010706),
|
||||||
|
.INIT_2D(256'h0100070506030107070707070707070707070707070707070707070707070707),
|
||||||
|
.INIT_2E(256'h0707070707070707070305070105010600000505030601060306010600000505),
|
||||||
|
.INIT_2F(256'h0707070707070707070707070707070707070707070707070707070707070707),
|
||||||
|
.INIT_30(256'h0502070701050106010501060506070707070707070707070707070707070707),
|
||||||
|
.INIT_31(256'h0707070707070707070707070707070707070707070707070707070707070707),
|
||||||
|
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||||
|
.INIT_A(18'h00000),
|
||||||
|
.INIT_B(18'h00000),
|
||||||
|
.INIT_FILE("NONE"),
|
||||||
|
.IS_CLKARDCLK_INVERTED(1'b0),
|
||||||
|
.IS_CLKBWRCLK_INVERTED(1'b0),
|
||||||
|
.IS_ENARDEN_INVERTED(1'b0),
|
||||||
|
.IS_ENBWREN_INVERTED(1'b0),
|
||||||
|
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
|
||||||
|
.IS_RSTRAMB_INVERTED(1'b0),
|
||||||
|
.IS_RSTREGARSTREG_INVERTED(1'b0),
|
||||||
|
.IS_RSTREGB_INVERTED(1'b0),
|
||||||
|
.RAM_MODE("TDP"),
|
||||||
|
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
|
||||||
|
.READ_WIDTH_A(18),
|
||||||
|
.READ_WIDTH_B(18),
|
||||||
|
.RSTREG_PRIORITY_A("REGCE"),
|
||||||
|
.RSTREG_PRIORITY_B("REGCE"),
|
||||||
|
.SIM_COLLISION_CHECK("ALL"),
|
||||||
|
.SIM_DEVICE("7SERIES"),
|
||||||
|
.SRVAL_A(18'h00000),
|
||||||
|
.SRVAL_B(18'h00000),
|
||||||
|
.WRITE_MODE_A("WRITE_FIRST"),
|
||||||
|
.WRITE_MODE_B("WRITE_FIRST"),
|
||||||
|
.WRITE_WIDTH_A(18),
|
||||||
|
.WRITE_WIDTH_B(18))
|
||||||
|
\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram
|
||||||
|
(.ADDRARDADDR({addra,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||||
|
.ADDRBWRADDR({addra,1'b1,1'b0,1'b0,1'b0,1'b0}),
|
||||||
|
.CLKARDCLK(clka),
|
||||||
|
.CLKBWRCLK(clka),
|
||||||
|
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||||
|
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||||
|
.DIPADIP({1'b0,1'b0}),
|
||||||
|
.DIPBDIP({1'b0,1'b0}),
|
||||||
|
.DOADO({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4 ,douta[5:3],\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12 ,douta[2:0]}),
|
||||||
|
.DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20 ,douta[11:9],\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28 ,douta[8:6]}),
|
||||||
|
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 }),
|
||||||
|
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 }),
|
||||||
|
.ENARDEN(ena),
|
||||||
|
.ENBWREN(ena),
|
||||||
|
.REGCEAREGCE(ena),
|
||||||
|
.REGCEB(ena),
|
||||||
|
.RSTRAMARSTRAM(1'b0),
|
||||||
|
.RSTRAMB(1'b0),
|
||||||
|
.RSTREGARSTREG(1'b0),
|
||||||
|
.RSTREGB(1'b0),
|
||||||
|
.WEA({1'b0,1'b0}),
|
||||||
|
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
|
||||||
|
module lightning_20_20_blk_mem_gen_top
|
||||||
|
(douta,
|
||||||
|
clka,
|
||||||
|
ena,
|
||||||
|
addra);
|
||||||
|
output [11:0]douta;
|
||||||
|
input clka;
|
||||||
|
input ena;
|
||||||
|
input [8:0]addra;
|
||||||
|
|
||||||
|
wire [8:0]addra;
|
||||||
|
wire clka;
|
||||||
|
wire [11:0]douta;
|
||||||
|
wire ena;
|
||||||
|
|
||||||
|
lightning_20_20_blk_mem_gen_generic_cstr \valid.cstr
|
||||||
|
(.addra(addra),
|
||||||
|
.clka(clka),
|
||||||
|
.douta(douta),
|
||||||
|
.ena(ena));
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
(* C_ADDRA_WIDTH = "9" *) (* C_ADDRB_WIDTH = "9" *) (* C_ALGORITHM = "1" *)
|
||||||
|
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
|
||||||
|
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
|
||||||
|
(* C_COUNT_36K_BRAM = "0" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
|
||||||
|
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
|
||||||
|
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
|
||||||
|
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
|
||||||
|
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.5432 mW" *)
|
||||||
|
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *)
|
||||||
|
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
|
||||||
|
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
|
||||||
|
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
|
||||||
|
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
|
||||||
|
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "lightning_20_20.mem" *)
|
||||||
|
(* C_INIT_FILE_NAME = "lightning_20_20.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
|
||||||
|
(* C_MEM_TYPE = "3" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
|
||||||
|
(* C_READ_DEPTH_A = "400" *) (* C_READ_DEPTH_B = "400" *) (* C_READ_LATENCY_A = "1" *)
|
||||||
|
(* C_READ_LATENCY_B = "1" *) (* C_READ_WIDTH_A = "12" *) (* C_READ_WIDTH_B = "12" *)
|
||||||
|
(* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *)
|
||||||
|
(* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *)
|
||||||
|
(* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *)
|
||||||
|
(* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *)
|
||||||
|
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "400" *)
|
||||||
|
(* C_WRITE_DEPTH_B = "400" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
||||||
|
(* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *) (* C_XDEVICEFAMILY = "artix7" *)
|
||||||
|
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
|
||||||
|
module lightning_20_20_blk_mem_gen_v8_4_4
|
||||||
|
(clka,
|
||||||
|
rsta,
|
||||||
|
ena,
|
||||||
|
regcea,
|
||||||
|
wea,
|
||||||
|
addra,
|
||||||
|
dina,
|
||||||
|
douta,
|
||||||
|
clkb,
|
||||||
|
rstb,
|
||||||
|
enb,
|
||||||
|
regceb,
|
||||||
|
web,
|
||||||
|
addrb,
|
||||||
|
dinb,
|
||||||
|
doutb,
|
||||||
|
injectsbiterr,
|
||||||
|
injectdbiterr,
|
||||||
|
eccpipece,
|
||||||
|
sbiterr,
|
||||||
|
dbiterr,
|
||||||
|
rdaddrecc,
|
||||||
|
sleep,
|
||||||
|
deepsleep,
|
||||||
|
shutdown,
|
||||||
|
rsta_busy,
|
||||||
|
rstb_busy,
|
||||||
|
s_aclk,
|
||||||
|
s_aresetn,
|
||||||
|
s_axi_awid,
|
||||||
|
s_axi_awaddr,
|
||||||
|
s_axi_awlen,
|
||||||
|
s_axi_awsize,
|
||||||
|
s_axi_awburst,
|
||||||
|
s_axi_awvalid,
|
||||||
|
s_axi_awready,
|
||||||
|
s_axi_wdata,
|
||||||
|
s_axi_wstrb,
|
||||||
|
s_axi_wlast,
|
||||||
|
s_axi_wvalid,
|
||||||
|
s_axi_wready,
|
||||||
|
s_axi_bid,
|
||||||
|
s_axi_bresp,
|
||||||
|
s_axi_bvalid,
|
||||||
|
s_axi_bready,
|
||||||
|
s_axi_arid,
|
||||||
|
s_axi_araddr,
|
||||||
|
s_axi_arlen,
|
||||||
|
s_axi_arsize,
|
||||||
|
s_axi_arburst,
|
||||||
|
s_axi_arvalid,
|
||||||
|
s_axi_arready,
|
||||||
|
s_axi_rid,
|
||||||
|
s_axi_rdata,
|
||||||
|
s_axi_rresp,
|
||||||
|
s_axi_rlast,
|
||||||
|
s_axi_rvalid,
|
||||||
|
s_axi_rready,
|
||||||
|
s_axi_injectsbiterr,
|
||||||
|
s_axi_injectdbiterr,
|
||||||
|
s_axi_sbiterr,
|
||||||
|
s_axi_dbiterr,
|
||||||
|
s_axi_rdaddrecc);
|
||||||
|
input clka;
|
||||||
|
input rsta;
|
||||||
|
input ena;
|
||||||
|
input regcea;
|
||||||
|
input [0:0]wea;
|
||||||
|
input [8:0]addra;
|
||||||
|
input [11:0]dina;
|
||||||
|
output [11:0]douta;
|
||||||
|
input clkb;
|
||||||
|
input rstb;
|
||||||
|
input enb;
|
||||||
|
input regceb;
|
||||||
|
input [0:0]web;
|
||||||
|
input [8:0]addrb;
|
||||||
|
input [11:0]dinb;
|
||||||
|
output [11:0]doutb;
|
||||||
|
input injectsbiterr;
|
||||||
|
input injectdbiterr;
|
||||||
|
input eccpipece;
|
||||||
|
output sbiterr;
|
||||||
|
output dbiterr;
|
||||||
|
output [8:0]rdaddrecc;
|
||||||
|
input sleep;
|
||||||
|
input deepsleep;
|
||||||
|
input shutdown;
|
||||||
|
output rsta_busy;
|
||||||
|
output rstb_busy;
|
||||||
|
input s_aclk;
|
||||||
|
input s_aresetn;
|
||||||
|
input [3:0]s_axi_awid;
|
||||||
|
input [31:0]s_axi_awaddr;
|
||||||
|
input [7:0]s_axi_awlen;
|
||||||
|
input [2:0]s_axi_awsize;
|
||||||
|
input [1:0]s_axi_awburst;
|
||||||
|
input s_axi_awvalid;
|
||||||
|
output s_axi_awready;
|
||||||
|
input [11:0]s_axi_wdata;
|
||||||
|
input [0:0]s_axi_wstrb;
|
||||||
|
input s_axi_wlast;
|
||||||
|
input s_axi_wvalid;
|
||||||
|
output s_axi_wready;
|
||||||
|
output [3:0]s_axi_bid;
|
||||||
|
output [1:0]s_axi_bresp;
|
||||||
|
output s_axi_bvalid;
|
||||||
|
input s_axi_bready;
|
||||||
|
input [3:0]s_axi_arid;
|
||||||
|
input [31:0]s_axi_araddr;
|
||||||
|
input [7:0]s_axi_arlen;
|
||||||
|
input [2:0]s_axi_arsize;
|
||||||
|
input [1:0]s_axi_arburst;
|
||||||
|
input s_axi_arvalid;
|
||||||
|
output s_axi_arready;
|
||||||
|
output [3:0]s_axi_rid;
|
||||||
|
output [11:0]s_axi_rdata;
|
||||||
|
output [1:0]s_axi_rresp;
|
||||||
|
output s_axi_rlast;
|
||||||
|
output s_axi_rvalid;
|
||||||
|
input s_axi_rready;
|
||||||
|
input s_axi_injectsbiterr;
|
||||||
|
input s_axi_injectdbiterr;
|
||||||
|
output s_axi_sbiterr;
|
||||||
|
output s_axi_dbiterr;
|
||||||
|
output [8:0]s_axi_rdaddrecc;
|
||||||
|
|
||||||
|
wire \<const0> ;
|
||||||
|
wire [8:0]addra;
|
||||||
|
wire clka;
|
||||||
|
wire [11:0]douta;
|
||||||
|
wire ena;
|
||||||
|
|
||||||
|
assign dbiterr = \<const0> ;
|
||||||
|
assign doutb[11] = \<const0> ;
|
||||||
|
assign doutb[10] = \<const0> ;
|
||||||
|
assign doutb[9] = \<const0> ;
|
||||||
|
assign doutb[8] = \<const0> ;
|
||||||
|
assign doutb[7] = \<const0> ;
|
||||||
|
assign doutb[6] = \<const0> ;
|
||||||
|
assign doutb[5] = \<const0> ;
|
||||||
|
assign doutb[4] = \<const0> ;
|
||||||
|
assign doutb[3] = \<const0> ;
|
||||||
|
assign doutb[2] = \<const0> ;
|
||||||
|
assign doutb[1] = \<const0> ;
|
||||||
|
assign doutb[0] = \<const0> ;
|
||||||
|
assign rdaddrecc[8] = \<const0> ;
|
||||||
|
assign rdaddrecc[7] = \<const0> ;
|
||||||
|
assign rdaddrecc[6] = \<const0> ;
|
||||||
|
assign rdaddrecc[5] = \<const0> ;
|
||||||
|
assign rdaddrecc[4] = \<const0> ;
|
||||||
|
assign rdaddrecc[3] = \<const0> ;
|
||||||
|
assign rdaddrecc[2] = \<const0> ;
|
||||||
|
assign rdaddrecc[1] = \<const0> ;
|
||||||
|
assign rdaddrecc[0] = \<const0> ;
|
||||||
|
assign rsta_busy = \<const0> ;
|
||||||
|
assign rstb_busy = \<const0> ;
|
||||||
|
assign s_axi_arready = \<const0> ;
|
||||||
|
assign s_axi_awready = \<const0> ;
|
||||||
|
assign s_axi_bid[3] = \<const0> ;
|
||||||
|
assign s_axi_bid[2] = \<const0> ;
|
||||||
|
assign s_axi_bid[1] = \<const0> ;
|
||||||
|
assign s_axi_bid[0] = \<const0> ;
|
||||||
|
assign s_axi_bresp[1] = \<const0> ;
|
||||||
|
assign s_axi_bresp[0] = \<const0> ;
|
||||||
|
assign s_axi_bvalid = \<const0> ;
|
||||||
|
assign s_axi_dbiterr = \<const0> ;
|
||||||
|
assign s_axi_rdaddrecc[8] = \<const0> ;
|
||||||
|
assign s_axi_rdaddrecc[7] = \<const0> ;
|
||||||
|
assign s_axi_rdaddrecc[6] = \<const0> ;
|
||||||
|
assign s_axi_rdaddrecc[5] = \<const0> ;
|
||||||
|
assign s_axi_rdaddrecc[4] = \<const0> ;
|
||||||
|
assign s_axi_rdaddrecc[3] = \<const0> ;
|
||||||
|
assign s_axi_rdaddrecc[2] = \<const0> ;
|
||||||
|
assign s_axi_rdaddrecc[1] = \<const0> ;
|
||||||
|
assign s_axi_rdaddrecc[0] = \<const0> ;
|
||||||
|
assign s_axi_rdata[11] = \<const0> ;
|
||||||
|
assign s_axi_rdata[10] = \<const0> ;
|
||||||
|
assign s_axi_rdata[9] = \<const0> ;
|
||||||
|
assign s_axi_rdata[8] = \<const0> ;
|
||||||
|
assign s_axi_rdata[7] = \<const0> ;
|
||||||
|
assign s_axi_rdata[6] = \<const0> ;
|
||||||
|
assign s_axi_rdata[5] = \<const0> ;
|
||||||
|
assign s_axi_rdata[4] = \<const0> ;
|
||||||
|
assign s_axi_rdata[3] = \<const0> ;
|
||||||
|
assign s_axi_rdata[2] = \<const0> ;
|
||||||
|
assign s_axi_rdata[1] = \<const0> ;
|
||||||
|
assign s_axi_rdata[0] = \<const0> ;
|
||||||
|
assign s_axi_rid[3] = \<const0> ;
|
||||||
|
assign s_axi_rid[2] = \<const0> ;
|
||||||
|
assign s_axi_rid[1] = \<const0> ;
|
||||||
|
assign s_axi_rid[0] = \<const0> ;
|
||||||
|
assign s_axi_rlast = \<const0> ;
|
||||||
|
assign s_axi_rresp[1] = \<const0> ;
|
||||||
|
assign s_axi_rresp[0] = \<const0> ;
|
||||||
|
assign s_axi_rvalid = \<const0> ;
|
||||||
|
assign s_axi_sbiterr = \<const0> ;
|
||||||
|
assign s_axi_wready = \<const0> ;
|
||||||
|
assign sbiterr = \<const0> ;
|
||||||
|
GND GND
|
||||||
|
(.G(\<const0> ));
|
||||||
|
lightning_20_20_blk_mem_gen_v8_4_4_synth inst_blk_mem_gen
|
||||||
|
(.addra(addra),
|
||||||
|
.clka(clka),
|
||||||
|
.douta(douta),
|
||||||
|
.ena(ena));
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
|
||||||
|
module lightning_20_20_blk_mem_gen_v8_4_4_synth
|
||||||
|
(douta,
|
||||||
|
clka,
|
||||||
|
ena,
|
||||||
|
addra);
|
||||||
|
output [11:0]douta;
|
||||||
|
input clka;
|
||||||
|
input ena;
|
||||||
|
input [8:0]addra;
|
||||||
|
|
||||||
|
wire [8:0]addra;
|
||||||
|
wire clka;
|
||||||
|
wire [11:0]douta;
|
||||||
|
wire ena;
|
||||||
|
|
||||||
|
lightning_20_20_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
|
||||||
|
(.addra(addra),
|
||||||
|
.clka(clka),
|
||||||
|
.douta(douta),
|
||||||
|
.ena(ena));
|
||||||
|
endmodule
|
||||||
|
`ifndef GLBL
|
||||||
|
`define GLBL
|
||||||
|
`timescale 1 ps / 1 ps
|
||||||
|
|
||||||
|
module glbl ();
|
||||||
|
|
||||||
|
parameter ROC_WIDTH = 100000;
|
||||||
|
parameter TOC_WIDTH = 0;
|
||||||
|
|
||||||
|
//-------- STARTUP Globals --------------
|
||||||
|
wire GSR;
|
||||||
|
wire GTS;
|
||||||
|
wire GWE;
|
||||||
|
wire PRLD;
|
||||||
|
tri1 p_up_tmp;
|
||||||
|
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||||
|
|
||||||
|
wire PROGB_GLBL;
|
||||||
|
wire CCLKO_GLBL;
|
||||||
|
wire FCSBO_GLBL;
|
||||||
|
wire [3:0] DO_GLBL;
|
||||||
|
wire [3:0] DI_GLBL;
|
||||||
|
|
||||||
|
reg GSR_int;
|
||||||
|
reg GTS_int;
|
||||||
|
reg PRLD_int;
|
||||||
|
|
||||||
|
//-------- JTAG Globals --------------
|
||||||
|
wire JTAG_TDO_GLBL;
|
||||||
|
wire JTAG_TCK_GLBL;
|
||||||
|
wire JTAG_TDI_GLBL;
|
||||||
|
wire JTAG_TMS_GLBL;
|
||||||
|
wire JTAG_TRST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_CAPTURE_GLBL;
|
||||||
|
reg JTAG_RESET_GLBL;
|
||||||
|
reg JTAG_SHIFT_GLBL;
|
||||||
|
reg JTAG_UPDATE_GLBL;
|
||||||
|
reg JTAG_RUNTEST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_SEL1_GLBL = 0;
|
||||||
|
reg JTAG_SEL2_GLBL = 0 ;
|
||||||
|
reg JTAG_SEL3_GLBL = 0;
|
||||||
|
reg JTAG_SEL4_GLBL = 0;
|
||||||
|
|
||||||
|
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||||
|
|
||||||
|
assign (strong1, weak0) GSR = GSR_int;
|
||||||
|
assign (strong1, weak0) GTS = GTS_int;
|
||||||
|
assign (weak1, weak0) PRLD = PRLD_int;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GSR_int = 1'b1;
|
||||||
|
PRLD_int = 1'b1;
|
||||||
|
#(ROC_WIDTH)
|
||||||
|
GSR_int = 1'b0;
|
||||||
|
PRLD_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GTS_int = 1'b1;
|
||||||
|
#(TOC_WIDTH)
|
||||||
|
GTS_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
|
|
@ -0,0 +1,883 @@
|
||||||
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||||
|
-- Date : Wed Jan 6 17:21:01 2021
|
||||||
|
-- Host : cxz666 running 64-bit major release (build 9200)
|
||||||
|
-- Command : write_vhdl -force -mode funcsim
|
||||||
|
-- e:/linux/Compressed/FPGA-TankGame/TankGame.srcs/sources_1/ip/lightning_20_20/lightning_20_20_sim_netlist.vhdl
|
||||||
|
-- Design : lightning_20_20
|
||||||
|
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||||
|
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
-- Device : xc7a100tcsg324-1
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
library UNISIM;
|
||||||
|
use UNISIM.VCOMPONENTS.ALL;
|
||||||
|
entity lightning_20_20_blk_mem_gen_prim_wrapper_init is
|
||||||
|
port (
|
||||||
|
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||||
|
clka : in STD_LOGIC;
|
||||||
|
ena : in STD_LOGIC;
|
||||||
|
addra : in STD_LOGIC_VECTOR ( 8 downto 0 )
|
||||||
|
);
|
||||||
|
attribute ORIG_REF_NAME : string;
|
||||||
|
attribute ORIG_REF_NAME of lightning_20_20_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
|
||||||
|
end lightning_20_20_blk_mem_gen_prim_wrapper_init;
|
||||||
|
|
||||||
|
architecture STRUCTURE of lightning_20_20_blk_mem_gen_prim_wrapper_init is
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8\ : STD_LOGIC;
|
||||||
|
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9\ : STD_LOGIC;
|
||||||
|
attribute box_type : string;
|
||||||
|
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
|
||||||
|
begin
|
||||||
|
\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
|
||||||
|
generic map(
|
||||||
|
DOA_REG => 1,
|
||||||
|
DOB_REG => 1,
|
||||||
|
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INIT_00 => X"0506070706070507070707070707070707070707070707070707070707070707",
|
||||||
|
INIT_01 => X"0707070707070707060705070506070702050506000405050004050502050506",
|
||||||
|
INIT_02 => X"0707070707070707070707070707070707070707070707070707070707070707",
|
||||||
|
INIT_03 => X"0301070606070307060703070301070600000305000405050105010505020507",
|
||||||
|
INIT_04 => X"0707070707070707070707070707070705020507010501050004050500000305",
|
||||||
|
INIT_05 => X"0707070705020507030107060004070500040505020505060707070707070707",
|
||||||
|
INIT_06 => X"0004070503010706050205070707070707070707070707070707070707070707",
|
||||||
|
INIT_07 => X"0507010700000505070707070707070707070707070707070205050600040505",
|
||||||
|
INIT_08 => X"0703050707070707070707070707070707070707070707070707070707070707",
|
||||||
|
INIT_09 => X"0707070707070707000005050507010707070707070707070707070707070707",
|
||||||
|
INIT_0A => X"0707070707070707070707070707070706070307000005050707070707070707",
|
||||||
|
INIT_0B => X"0707070707070707070707070707070705060707070707070707070707070707",
|
||||||
|
INIT_0C => X"0607030700000505070707070707070707070707070707070000050506070307",
|
||||||
|
INIT_0D => X"0502050703050706070707070707070707070707070707070707070707070707",
|
||||||
|
INIT_0E => X"0707070707070707000005050607030707070707070707070707070707070707",
|
||||||
|
INIT_0F => X"0707070707070707070707070707070706070307000005050707070707070707",
|
||||||
|
INIT_10 => X"0707070707070707070707070707070705060707000005050507010707070707",
|
||||||
|
INIT_11 => X"0607030700040505070707070707070707070707070707070000050506070307",
|
||||||
|
INIT_12 => X"0607030700000305000407050607030707070707070707070707070707070707",
|
||||||
|
INIT_13 => X"0707070707070707000405050607030707070707070707070707070707070707",
|
||||||
|
INIT_14 => X"0707070707070707070707070707070706070307000405050707070707070707",
|
||||||
|
INIT_15 => X"0707070707070707070707070707070707030507000003050000030502010306",
|
||||||
|
INIT_16 => X"0607030700040505070707070707070707070707070707070004050506070307",
|
||||||
|
INIT_17 => X"0105030600000305000003050000030503060106070707070707070707070707",
|
||||||
|
INIT_18 => X"0707070707070707000405050607030707070707070707070607030702010306",
|
||||||
|
INIT_19 => X"0201030606070307070707070707070706070307000405050707070707070707",
|
||||||
|
INIT_1A => X"0707070707070707070707070306010600000305000003050000030501050306",
|
||||||
|
INIT_1B => X"0607030700040705070707070707070707070707070707070004050506070307",
|
||||||
|
INIT_1C => X"0201030600000305000003050703050707070707070707070707070707070707",
|
||||||
|
INIT_1D => X"0707070707070707000407050607030707070707070707070707070707070707",
|
||||||
|
INIT_1E => X"0707070707070707070707070707070706070307000407050707070707070707",
|
||||||
|
INIT_1F => X"0707070707070707070707070707070706070307000407050000030506070307",
|
||||||
|
INIT_20 => X"0406030601050106070707070707070707070707070707070004070506070307",
|
||||||
|
INIT_21 => X"0707070705070107000005050507010707070707070707070707070707070707",
|
||||||
|
INIT_22 => X"0707070707070707010501060406030607070707070707070707070707070707",
|
||||||
|
INIT_23 => X"0707070707070707070707070707070700040505040203060707070707070707",
|
||||||
|
INIT_24 => X"0707070707070707070707070707070707070707070707070305070605020507",
|
||||||
|
INIT_25 => X"0201030607070707070707070707070707070707070707070402030600040505",
|
||||||
|
INIT_26 => X"0707070707070707070707070506070707070707070707070607030701000705",
|
||||||
|
INIT_27 => X"0707070707070707070707070201030601000705060703070707070707070707",
|
||||||
|
INIT_28 => X"0707070705020707000405050100070507070707070707070707070707070707",
|
||||||
|
INIT_29 => X"0105010500040505050607070707070707070707070707070707070707030707",
|
||||||
|
INIT_2A => X"0707070707070707070707070707070707070707070707070707070707070707",
|
||||||
|
INIT_2B => X"0607030707070707070707070603010702050506000405050402030607070707",
|
||||||
|
INIT_2C => X"0707070707070707070707070707070707070707040603060100070503010706",
|
||||||
|
INIT_2D => X"0100070506030107070707070707070707070707070707070707070707070707",
|
||||||
|
INIT_2E => X"0707070707070707070305070105010600000505030601060306010600000505",
|
||||||
|
INIT_2F => X"0707070707070707070707070707070707070707070707070707070707070707",
|
||||||
|
INIT_30 => X"0502070701050106010501060506070707070707070707070707070707070707",
|
||||||
|
INIT_31 => X"0707070707070707070707070707070707070707070707070707070707070707",
|
||||||
|
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||||
|
INIT_A => X"00000",
|
||||||
|
INIT_B => X"00000",
|
||||||
|
INIT_FILE => "NONE",
|
||||||
|
IS_CLKARDCLK_INVERTED => '0',
|
||||||
|
IS_CLKBWRCLK_INVERTED => '0',
|
||||||
|
IS_ENARDEN_INVERTED => '0',
|
||||||
|
IS_ENBWREN_INVERTED => '0',
|
||||||
|
IS_RSTRAMARSTRAM_INVERTED => '0',
|
||||||
|
IS_RSTRAMB_INVERTED => '0',
|
||||||
|
IS_RSTREGARSTREG_INVERTED => '0',
|
||||||
|
IS_RSTREGB_INVERTED => '0',
|
||||||
|
RAM_MODE => "TDP",
|
||||||
|
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
|
||||||
|
READ_WIDTH_A => 18,
|
||||||
|
READ_WIDTH_B => 18,
|
||||||
|
RSTREG_PRIORITY_A => "REGCE",
|
||||||
|
RSTREG_PRIORITY_B => "REGCE",
|
||||||
|
SIM_COLLISION_CHECK => "ALL",
|
||||||
|
SIM_DEVICE => "7SERIES",
|
||||||
|
SRVAL_A => X"00000",
|
||||||
|
SRVAL_B => X"00000",
|
||||||
|
WRITE_MODE_A => "WRITE_FIRST",
|
||||||
|
WRITE_MODE_B => "WRITE_FIRST",
|
||||||
|
WRITE_WIDTH_A => 18,
|
||||||
|
WRITE_WIDTH_B => 18
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
ADDRARDADDR(13 downto 5) => addra(8 downto 0),
|
||||||
|
ADDRARDADDR(4 downto 0) => B"00000",
|
||||||
|
ADDRBWRADDR(13 downto 5) => addra(8 downto 0),
|
||||||
|
ADDRBWRADDR(4 downto 0) => B"10000",
|
||||||
|
CLKARDCLK => clka,
|
||||||
|
CLKBWRCLK => clka,
|
||||||
|
DIADI(15 downto 0) => B"0000000000000000",
|
||||||
|
DIBDI(15 downto 0) => B"0000000000000000",
|
||||||
|
DIPADIP(1 downto 0) => B"00",
|
||||||
|
DIPBDIP(1 downto 0) => B"00",
|
||||||
|
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0\,
|
||||||
|
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1\,
|
||||||
|
DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2\,
|
||||||
|
DOADO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3\,
|
||||||
|
DOADO(11) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4\,
|
||||||
|
DOADO(10 downto 8) => douta(5 downto 3),
|
||||||
|
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8\,
|
||||||
|
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9\,
|
||||||
|
DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10\,
|
||||||
|
DOADO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11\,
|
||||||
|
DOADO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12\,
|
||||||
|
DOADO(2 downto 0) => douta(2 downto 0),
|
||||||
|
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16\,
|
||||||
|
DOBDO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17\,
|
||||||
|
DOBDO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18\,
|
||||||
|
DOBDO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19\,
|
||||||
|
DOBDO(11) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20\,
|
||||||
|
DOBDO(10 downto 8) => douta(11 downto 9),
|
||||||
|
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24\,
|
||||||
|
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25\,
|
||||||
|
DOBDO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26\,
|
||||||
|
DOBDO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27\,
|
||||||
|
DOBDO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28\,
|
||||||
|
DOBDO(2 downto 0) => douta(8 downto 6),
|
||||||
|
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\,
|
||||||
|
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\,
|
||||||
|
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\,
|
||||||
|
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\,
|
||||||
|
ENARDEN => ena,
|
||||||
|
ENBWREN => ena,
|
||||||
|
REGCEAREGCE => ena,
|
||||||
|
REGCEB => ena,
|
||||||
|
RSTRAMARSTRAM => '0',
|
||||||
|
RSTRAMB => '0',
|
||||||
|
RSTREGARSTREG => '0',
|
||||||
|
RSTREGB => '0',
|
||||||
|
WEA(1 downto 0) => B"00",
|
||||||
|
WEBWE(3 downto 0) => B"0000"
|
||||||
|
);
|
||||||
|
end STRUCTURE;
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
library UNISIM;
|
||||||
|
use UNISIM.VCOMPONENTS.ALL;
|
||||||
|
entity lightning_20_20_blk_mem_gen_prim_width is
|
||||||
|
port (
|
||||||
|
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||||
|
clka : in STD_LOGIC;
|
||||||
|
ena : in STD_LOGIC;
|
||||||
|
addra : in STD_LOGIC_VECTOR ( 8 downto 0 )
|
||||||
|
);
|
||||||
|
attribute ORIG_REF_NAME : string;
|
||||||
|
attribute ORIG_REF_NAME of lightning_20_20_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
|
||||||
|
end lightning_20_20_blk_mem_gen_prim_width;
|
||||||
|
|
||||||
|
architecture STRUCTURE of lightning_20_20_blk_mem_gen_prim_width is
|
||||||
|
begin
|
||||||
|
\prim_init.ram\: entity work.lightning_20_20_blk_mem_gen_prim_wrapper_init
|
||||||
|
port map (
|
||||||
|
addra(8 downto 0) => addra(8 downto 0),
|
||||||
|
clka => clka,
|
||||||
|
douta(11 downto 0) => douta(11 downto 0),
|
||||||
|
ena => ena
|
||||||
|
);
|
||||||
|
end STRUCTURE;
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
library UNISIM;
|
||||||
|
use UNISIM.VCOMPONENTS.ALL;
|
||||||
|
entity lightning_20_20_blk_mem_gen_generic_cstr is
|
||||||
|
port (
|
||||||
|
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||||
|
clka : in STD_LOGIC;
|
||||||
|
ena : in STD_LOGIC;
|
||||||
|
addra : in STD_LOGIC_VECTOR ( 8 downto 0 )
|
||||||
|
);
|
||||||
|
attribute ORIG_REF_NAME : string;
|
||||||
|
attribute ORIG_REF_NAME of lightning_20_20_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
|
||||||
|
end lightning_20_20_blk_mem_gen_generic_cstr;
|
||||||
|
|
||||||
|
architecture STRUCTURE of lightning_20_20_blk_mem_gen_generic_cstr is
|
||||||
|
begin
|
||||||
|
\ramloop[0].ram.r\: entity work.lightning_20_20_blk_mem_gen_prim_width
|
||||||
|
port map (
|
||||||
|
addra(8 downto 0) => addra(8 downto 0),
|
||||||
|
clka => clka,
|
||||||
|
douta(11 downto 0) => douta(11 downto 0),
|
||||||
|
ena => ena
|
||||||
|
);
|
||||||
|
end STRUCTURE;
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
library UNISIM;
|
||||||
|
use UNISIM.VCOMPONENTS.ALL;
|
||||||
|
entity lightning_20_20_blk_mem_gen_top is
|
||||||
|
port (
|
||||||
|
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||||
|
clka : in STD_LOGIC;
|
||||||
|
ena : in STD_LOGIC;
|
||||||
|
addra : in STD_LOGIC_VECTOR ( 8 downto 0 )
|
||||||
|
);
|
||||||
|
attribute ORIG_REF_NAME : string;
|
||||||
|
attribute ORIG_REF_NAME of lightning_20_20_blk_mem_gen_top : entity is "blk_mem_gen_top";
|
||||||
|
end lightning_20_20_blk_mem_gen_top;
|
||||||
|
|
||||||
|
architecture STRUCTURE of lightning_20_20_blk_mem_gen_top is
|
||||||
|
begin
|
||||||
|
\valid.cstr\: entity work.lightning_20_20_blk_mem_gen_generic_cstr
|
||||||
|
port map (
|
||||||
|
addra(8 downto 0) => addra(8 downto 0),
|
||||||
|
clka => clka,
|
||||||
|
douta(11 downto 0) => douta(11 downto 0),
|
||||||
|
ena => ena
|
||||||
|
);
|
||||||
|
end STRUCTURE;
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
library UNISIM;
|
||||||
|
use UNISIM.VCOMPONENTS.ALL;
|
||||||
|
entity lightning_20_20_blk_mem_gen_v8_4_4_synth is
|
||||||
|
port (
|
||||||
|
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||||
|
clka : in STD_LOGIC;
|
||||||
|
ena : in STD_LOGIC;
|
||||||
|
addra : in STD_LOGIC_VECTOR ( 8 downto 0 )
|
||||||
|
);
|
||||||
|
attribute ORIG_REF_NAME : string;
|
||||||
|
attribute ORIG_REF_NAME of lightning_20_20_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
|
||||||
|
end lightning_20_20_blk_mem_gen_v8_4_4_synth;
|
||||||
|
|
||||||
|
architecture STRUCTURE of lightning_20_20_blk_mem_gen_v8_4_4_synth is
|
||||||
|
begin
|
||||||
|
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.lightning_20_20_blk_mem_gen_top
|
||||||
|
port map (
|
||||||
|
addra(8 downto 0) => addra(8 downto 0),
|
||||||
|
clka => clka,
|
||||||
|
douta(11 downto 0) => douta(11 downto 0),
|
||||||
|
ena => ena
|
||||||
|
);
|
||||||
|
end STRUCTURE;
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
library UNISIM;
|
||||||
|
use UNISIM.VCOMPONENTS.ALL;
|
||||||
|
entity lightning_20_20_blk_mem_gen_v8_4_4 is
|
||||||
|
port (
|
||||||
|
clka : in STD_LOGIC;
|
||||||
|
rsta : in STD_LOGIC;
|
||||||
|
ena : in STD_LOGIC;
|
||||||
|
regcea : in STD_LOGIC;
|
||||||
|
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||||
|
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||||
|
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||||
|
clkb : in STD_LOGIC;
|
||||||
|
rstb : in STD_LOGIC;
|
||||||
|
enb : in STD_LOGIC;
|
||||||
|
regceb : in STD_LOGIC;
|
||||||
|
web : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
addrb : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||||
|
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||||
|
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||||
|
injectsbiterr : in STD_LOGIC;
|
||||||
|
injectdbiterr : in STD_LOGIC;
|
||||||
|
eccpipece : in STD_LOGIC;
|
||||||
|
sbiterr : out STD_LOGIC;
|
||||||
|
dbiterr : out STD_LOGIC;
|
||||||
|
rdaddrecc : out STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||||
|
sleep : in STD_LOGIC;
|
||||||
|
deepsleep : in STD_LOGIC;
|
||||||
|
shutdown : in STD_LOGIC;
|
||||||
|
rsta_busy : out STD_LOGIC;
|
||||||
|
rstb_busy : out STD_LOGIC;
|
||||||
|
s_aclk : in STD_LOGIC;
|
||||||
|
s_aresetn : in STD_LOGIC;
|
||||||
|
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||||
|
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||||
|
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||||
|
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||||
|
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||||
|
s_axi_awvalid : in STD_LOGIC;
|
||||||
|
s_axi_awready : out STD_LOGIC;
|
||||||
|
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||||
|
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
s_axi_wlast : in STD_LOGIC;
|
||||||
|
s_axi_wvalid : in STD_LOGIC;
|
||||||
|
s_axi_wready : out STD_LOGIC;
|
||||||
|
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||||
|
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||||
|
s_axi_bvalid : out STD_LOGIC;
|
||||||
|
s_axi_bready : in STD_LOGIC;
|
||||||
|
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||||
|
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||||
|
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||||
|
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||||
|
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||||
|
s_axi_arvalid : in STD_LOGIC;
|
||||||
|
s_axi_arready : out STD_LOGIC;
|
||||||
|
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||||
|
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||||
|
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||||
|
s_axi_rlast : out STD_LOGIC;
|
||||||
|
s_axi_rvalid : out STD_LOGIC;
|
||||||
|
s_axi_rready : in STD_LOGIC;
|
||||||
|
s_axi_injectsbiterr : in STD_LOGIC;
|
||||||
|
s_axi_injectdbiterr : in STD_LOGIC;
|
||||||
|
s_axi_sbiterr : out STD_LOGIC;
|
||||||
|
s_axi_dbiterr : out STD_LOGIC;
|
||||||
|
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 8 downto 0 )
|
||||||
|
);
|
||||||
|
attribute C_ADDRA_WIDTH : integer;
|
||||||
|
attribute C_ADDRA_WIDTH of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 9;
|
||||||
|
attribute C_ADDRB_WIDTH : integer;
|
||||||
|
attribute C_ADDRB_WIDTH of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 9;
|
||||||
|
attribute C_ALGORITHM : integer;
|
||||||
|
attribute C_ALGORITHM of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 1;
|
||||||
|
attribute C_AXI_ID_WIDTH : integer;
|
||||||
|
attribute C_AXI_ID_WIDTH of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 4;
|
||||||
|
attribute C_AXI_SLAVE_TYPE : integer;
|
||||||
|
attribute C_AXI_SLAVE_TYPE of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_AXI_TYPE : integer;
|
||||||
|
attribute C_AXI_TYPE of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 1;
|
||||||
|
attribute C_BYTE_SIZE : integer;
|
||||||
|
attribute C_BYTE_SIZE of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 9;
|
||||||
|
attribute C_COMMON_CLK : integer;
|
||||||
|
attribute C_COMMON_CLK of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_COUNT_18K_BRAM : string;
|
||||||
|
attribute C_COUNT_18K_BRAM of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "1";
|
||||||
|
attribute C_COUNT_36K_BRAM : string;
|
||||||
|
attribute C_COUNT_36K_BRAM of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "0";
|
||||||
|
attribute C_CTRL_ECC_ALGO : string;
|
||||||
|
attribute C_CTRL_ECC_ALGO of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "NONE";
|
||||||
|
attribute C_DEFAULT_DATA : string;
|
||||||
|
attribute C_DEFAULT_DATA of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "0";
|
||||||
|
attribute C_DISABLE_WARN_BHV_COLL : integer;
|
||||||
|
attribute C_DISABLE_WARN_BHV_COLL of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_DISABLE_WARN_BHV_RANGE : integer;
|
||||||
|
attribute C_DISABLE_WARN_BHV_RANGE of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_ELABORATION_DIR : string;
|
||||||
|
attribute C_ELABORATION_DIR of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "./";
|
||||||
|
attribute C_ENABLE_32BIT_ADDRESS : integer;
|
||||||
|
attribute C_ENABLE_32BIT_ADDRESS of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_EN_DEEPSLEEP_PIN : integer;
|
||||||
|
attribute C_EN_DEEPSLEEP_PIN of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_EN_ECC_PIPE : integer;
|
||||||
|
attribute C_EN_ECC_PIPE of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_EN_RDADDRA_CHG : integer;
|
||||||
|
attribute C_EN_RDADDRA_CHG of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_EN_RDADDRB_CHG : integer;
|
||||||
|
attribute C_EN_RDADDRB_CHG of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_EN_SAFETY_CKT : integer;
|
||||||
|
attribute C_EN_SAFETY_CKT of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_EN_SHUTDOWN_PIN : integer;
|
||||||
|
attribute C_EN_SHUTDOWN_PIN of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_EN_SLEEP_PIN : integer;
|
||||||
|
attribute C_EN_SLEEP_PIN of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_EST_POWER_SUMMARY : string;
|
||||||
|
attribute C_EST_POWER_SUMMARY of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "Estimated Power for IP : 2.5432 mW";
|
||||||
|
attribute C_FAMILY : string;
|
||||||
|
attribute C_FAMILY of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "artix7";
|
||||||
|
attribute C_HAS_AXI_ID : integer;
|
||||||
|
attribute C_HAS_AXI_ID of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_HAS_ENA : integer;
|
||||||
|
attribute C_HAS_ENA of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 1;
|
||||||
|
attribute C_HAS_ENB : integer;
|
||||||
|
attribute C_HAS_ENB of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_HAS_INJECTERR : integer;
|
||||||
|
attribute C_HAS_INJECTERR of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
|
||||||
|
attribute C_HAS_MEM_OUTPUT_REGS_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 1;
|
||||||
|
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
|
||||||
|
attribute C_HAS_MEM_OUTPUT_REGS_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
|
||||||
|
attribute C_HAS_MUX_OUTPUT_REGS_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
|
||||||
|
attribute C_HAS_MUX_OUTPUT_REGS_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_HAS_REGCEA : integer;
|
||||||
|
attribute C_HAS_REGCEA of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_HAS_REGCEB : integer;
|
||||||
|
attribute C_HAS_REGCEB of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_HAS_RSTA : integer;
|
||||||
|
attribute C_HAS_RSTA of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_HAS_RSTB : integer;
|
||||||
|
attribute C_HAS_RSTB of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
|
||||||
|
attribute C_HAS_SOFTECC_INPUT_REGS_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
|
||||||
|
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_INITA_VAL : string;
|
||||||
|
attribute C_INITA_VAL of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "0";
|
||||||
|
attribute C_INITB_VAL : string;
|
||||||
|
attribute C_INITB_VAL of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "0";
|
||||||
|
attribute C_INIT_FILE : string;
|
||||||
|
attribute C_INIT_FILE of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "lightning_20_20.mem";
|
||||||
|
attribute C_INIT_FILE_NAME : string;
|
||||||
|
attribute C_INIT_FILE_NAME of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "lightning_20_20.mif";
|
||||||
|
attribute C_INTERFACE_TYPE : integer;
|
||||||
|
attribute C_INTERFACE_TYPE of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_LOAD_INIT_FILE : integer;
|
||||||
|
attribute C_LOAD_INIT_FILE of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 1;
|
||||||
|
attribute C_MEM_TYPE : integer;
|
||||||
|
attribute C_MEM_TYPE of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 3;
|
||||||
|
attribute C_MUX_PIPELINE_STAGES : integer;
|
||||||
|
attribute C_MUX_PIPELINE_STAGES of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_PRIM_TYPE : integer;
|
||||||
|
attribute C_PRIM_TYPE of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 1;
|
||||||
|
attribute C_READ_DEPTH_A : integer;
|
||||||
|
attribute C_READ_DEPTH_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 400;
|
||||||
|
attribute C_READ_DEPTH_B : integer;
|
||||||
|
attribute C_READ_DEPTH_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 400;
|
||||||
|
attribute C_READ_LATENCY_A : integer;
|
||||||
|
attribute C_READ_LATENCY_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 1;
|
||||||
|
attribute C_READ_LATENCY_B : integer;
|
||||||
|
attribute C_READ_LATENCY_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 1;
|
||||||
|
attribute C_READ_WIDTH_A : integer;
|
||||||
|
attribute C_READ_WIDTH_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 12;
|
||||||
|
attribute C_READ_WIDTH_B : integer;
|
||||||
|
attribute C_READ_WIDTH_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 12;
|
||||||
|
attribute C_RSTRAM_A : integer;
|
||||||
|
attribute C_RSTRAM_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_RSTRAM_B : integer;
|
||||||
|
attribute C_RSTRAM_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_RST_PRIORITY_A : string;
|
||||||
|
attribute C_RST_PRIORITY_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "CE";
|
||||||
|
attribute C_RST_PRIORITY_B : string;
|
||||||
|
attribute C_RST_PRIORITY_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "CE";
|
||||||
|
attribute C_SIM_COLLISION_CHECK : string;
|
||||||
|
attribute C_SIM_COLLISION_CHECK of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "ALL";
|
||||||
|
attribute C_USE_BRAM_BLOCK : integer;
|
||||||
|
attribute C_USE_BRAM_BLOCK of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_USE_BYTE_WEA : integer;
|
||||||
|
attribute C_USE_BYTE_WEA of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_USE_BYTE_WEB : integer;
|
||||||
|
attribute C_USE_BYTE_WEB of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_USE_DEFAULT_DATA : integer;
|
||||||
|
attribute C_USE_DEFAULT_DATA of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_USE_ECC : integer;
|
||||||
|
attribute C_USE_ECC of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_USE_SOFTECC : integer;
|
||||||
|
attribute C_USE_SOFTECC of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_USE_URAM : integer;
|
||||||
|
attribute C_USE_URAM of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 0;
|
||||||
|
attribute C_WEA_WIDTH : integer;
|
||||||
|
attribute C_WEA_WIDTH of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 1;
|
||||||
|
attribute C_WEB_WIDTH : integer;
|
||||||
|
attribute C_WEB_WIDTH of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 1;
|
||||||
|
attribute C_WRITE_DEPTH_A : integer;
|
||||||
|
attribute C_WRITE_DEPTH_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 400;
|
||||||
|
attribute C_WRITE_DEPTH_B : integer;
|
||||||
|
attribute C_WRITE_DEPTH_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 400;
|
||||||
|
attribute C_WRITE_MODE_A : string;
|
||||||
|
attribute C_WRITE_MODE_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "WRITE_FIRST";
|
||||||
|
attribute C_WRITE_MODE_B : string;
|
||||||
|
attribute C_WRITE_MODE_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "WRITE_FIRST";
|
||||||
|
attribute C_WRITE_WIDTH_A : integer;
|
||||||
|
attribute C_WRITE_WIDTH_A of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 12;
|
||||||
|
attribute C_WRITE_WIDTH_B : integer;
|
||||||
|
attribute C_WRITE_WIDTH_B of lightning_20_20_blk_mem_gen_v8_4_4 : entity is 12;
|
||||||
|
attribute C_XDEVICEFAMILY : string;
|
||||||
|
attribute C_XDEVICEFAMILY of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "artix7";
|
||||||
|
attribute ORIG_REF_NAME : string;
|
||||||
|
attribute ORIG_REF_NAME of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
|
||||||
|
attribute downgradeipidentifiedwarnings : string;
|
||||||
|
attribute downgradeipidentifiedwarnings of lightning_20_20_blk_mem_gen_v8_4_4 : entity is "yes";
|
||||||
|
end lightning_20_20_blk_mem_gen_v8_4_4;
|
||||||
|
|
||||||
|
architecture STRUCTURE of lightning_20_20_blk_mem_gen_v8_4_4 is
|
||||||
|
signal \<const0>\ : STD_LOGIC;
|
||||||
|
begin
|
||||||
|
dbiterr <= \<const0>\;
|
||||||
|
doutb(11) <= \<const0>\;
|
||||||
|
doutb(10) <= \<const0>\;
|
||||||
|
doutb(9) <= \<const0>\;
|
||||||
|
doutb(8) <= \<const0>\;
|
||||||
|
doutb(7) <= \<const0>\;
|
||||||
|
doutb(6) <= \<const0>\;
|
||||||
|
doutb(5) <= \<const0>\;
|
||||||
|
doutb(4) <= \<const0>\;
|
||||||
|
doutb(3) <= \<const0>\;
|
||||||
|
doutb(2) <= \<const0>\;
|
||||||
|
doutb(1) <= \<const0>\;
|
||||||
|
doutb(0) <= \<const0>\;
|
||||||
|
rdaddrecc(8) <= \<const0>\;
|
||||||
|
rdaddrecc(7) <= \<const0>\;
|
||||||
|
rdaddrecc(6) <= \<const0>\;
|
||||||
|
rdaddrecc(5) <= \<const0>\;
|
||||||
|
rdaddrecc(4) <= \<const0>\;
|
||||||
|
rdaddrecc(3) <= \<const0>\;
|
||||||
|
rdaddrecc(2) <= \<const0>\;
|
||||||
|
rdaddrecc(1) <= \<const0>\;
|
||||||
|
rdaddrecc(0) <= \<const0>\;
|
||||||
|
rsta_busy <= \<const0>\;
|
||||||
|
rstb_busy <= \<const0>\;
|
||||||
|
s_axi_arready <= \<const0>\;
|
||||||
|
s_axi_awready <= \<const0>\;
|
||||||
|
s_axi_bid(3) <= \<const0>\;
|
||||||
|
s_axi_bid(2) <= \<const0>\;
|
||||||
|
s_axi_bid(1) <= \<const0>\;
|
||||||
|
s_axi_bid(0) <= \<const0>\;
|
||||||
|
s_axi_bresp(1) <= \<const0>\;
|
||||||
|
s_axi_bresp(0) <= \<const0>\;
|
||||||
|
s_axi_bvalid <= \<const0>\;
|
||||||
|
s_axi_dbiterr <= \<const0>\;
|
||||||
|
s_axi_rdaddrecc(8) <= \<const0>\;
|
||||||
|
s_axi_rdaddrecc(7) <= \<const0>\;
|
||||||
|
s_axi_rdaddrecc(6) <= \<const0>\;
|
||||||
|
s_axi_rdaddrecc(5) <= \<const0>\;
|
||||||
|
s_axi_rdaddrecc(4) <= \<const0>\;
|
||||||
|
s_axi_rdaddrecc(3) <= \<const0>\;
|
||||||
|
s_axi_rdaddrecc(2) <= \<const0>\;
|
||||||
|
s_axi_rdaddrecc(1) <= \<const0>\;
|
||||||
|
s_axi_rdaddrecc(0) <= \<const0>\;
|
||||||
|
s_axi_rdata(11) <= \<const0>\;
|
||||||
|
s_axi_rdata(10) <= \<const0>\;
|
||||||
|
s_axi_rdata(9) <= \<const0>\;
|
||||||
|
s_axi_rdata(8) <= \<const0>\;
|
||||||
|
s_axi_rdata(7) <= \<const0>\;
|
||||||
|
s_axi_rdata(6) <= \<const0>\;
|
||||||
|
s_axi_rdata(5) <= \<const0>\;
|
||||||
|
s_axi_rdata(4) <= \<const0>\;
|
||||||
|
s_axi_rdata(3) <= \<const0>\;
|
||||||
|
s_axi_rdata(2) <= \<const0>\;
|
||||||
|
s_axi_rdata(1) <= \<const0>\;
|
||||||
|
s_axi_rdata(0) <= \<const0>\;
|
||||||
|
s_axi_rid(3) <= \<const0>\;
|
||||||
|
s_axi_rid(2) <= \<const0>\;
|
||||||
|
s_axi_rid(1) <= \<const0>\;
|
||||||
|
s_axi_rid(0) <= \<const0>\;
|
||||||
|
s_axi_rlast <= \<const0>\;
|
||||||
|
s_axi_rresp(1) <= \<const0>\;
|
||||||
|
s_axi_rresp(0) <= \<const0>\;
|
||||||
|
s_axi_rvalid <= \<const0>\;
|
||||||
|
s_axi_sbiterr <= \<const0>\;
|
||||||
|
s_axi_wready <= \<const0>\;
|
||||||
|
sbiterr <= \<const0>\;
|
||||||
|
GND: unisim.vcomponents.GND
|
||||||
|
port map (
|
||||||
|
G => \<const0>\
|
||||||
|
);
|
||||||
|
inst_blk_mem_gen: entity work.lightning_20_20_blk_mem_gen_v8_4_4_synth
|
||||||
|
port map (
|
||||||
|
addra(8 downto 0) => addra(8 downto 0),
|
||||||
|
clka => clka,
|
||||||
|
douta(11 downto 0) => douta(11 downto 0),
|
||||||
|
ena => ena
|
||||||
|
);
|
||||||
|
end STRUCTURE;
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
library UNISIM;
|
||||||
|
use UNISIM.VCOMPONENTS.ALL;
|
||||||
|
entity lightning_20_20 is
|
||||||
|
port (
|
||||||
|
clka : in STD_LOGIC;
|
||||||
|
ena : in STD_LOGIC;
|
||||||
|
addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||||
|
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
|
||||||
|
);
|
||||||
|
attribute NotValidForBitStream : boolean;
|
||||||
|
attribute NotValidForBitStream of lightning_20_20 : entity is true;
|
||||||
|
attribute CHECK_LICENSE_TYPE : string;
|
||||||
|
attribute CHECK_LICENSE_TYPE of lightning_20_20 : entity is "lightning_20_20,blk_mem_gen_v8_4_4,{}";
|
||||||
|
attribute downgradeipidentifiedwarnings : string;
|
||||||
|
attribute downgradeipidentifiedwarnings of lightning_20_20 : entity is "yes";
|
||||||
|
attribute x_core_info : string;
|
||||||
|
attribute x_core_info of lightning_20_20 : entity is "blk_mem_gen_v8_4_4,Vivado 2019.2";
|
||||||
|
end lightning_20_20;
|
||||||
|
|
||||||
|
architecture STRUCTURE of lightning_20_20 is
|
||||||
|
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
|
||||||
|
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||||
|
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||||
|
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||||
|
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||||
|
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
|
||||||
|
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||||
|
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||||
|
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||||
|
attribute C_ADDRA_WIDTH : integer;
|
||||||
|
attribute C_ADDRA_WIDTH of U0 : label is 9;
|
||||||
|
attribute C_ADDRB_WIDTH : integer;
|
||||||
|
attribute C_ADDRB_WIDTH of U0 : label is 9;
|
||||||
|
attribute C_ALGORITHM : integer;
|
||||||
|
attribute C_ALGORITHM of U0 : label is 1;
|
||||||
|
attribute C_AXI_ID_WIDTH : integer;
|
||||||
|
attribute C_AXI_ID_WIDTH of U0 : label is 4;
|
||||||
|
attribute C_AXI_SLAVE_TYPE : integer;
|
||||||
|
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
|
||||||
|
attribute C_AXI_TYPE : integer;
|
||||||
|
attribute C_AXI_TYPE of U0 : label is 1;
|
||||||
|
attribute C_BYTE_SIZE : integer;
|
||||||
|
attribute C_BYTE_SIZE of U0 : label is 9;
|
||||||
|
attribute C_COMMON_CLK : integer;
|
||||||
|
attribute C_COMMON_CLK of U0 : label is 0;
|
||||||
|
attribute C_COUNT_18K_BRAM : string;
|
||||||
|
attribute C_COUNT_18K_BRAM of U0 : label is "1";
|
||||||
|
attribute C_COUNT_36K_BRAM : string;
|
||||||
|
attribute C_COUNT_36K_BRAM of U0 : label is "0";
|
||||||
|
attribute C_CTRL_ECC_ALGO : string;
|
||||||
|
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
|
||||||
|
attribute C_DEFAULT_DATA : string;
|
||||||
|
attribute C_DEFAULT_DATA of U0 : label is "0";
|
||||||
|
attribute C_DISABLE_WARN_BHV_COLL : integer;
|
||||||
|
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
|
||||||
|
attribute C_DISABLE_WARN_BHV_RANGE : integer;
|
||||||
|
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
|
||||||
|
attribute C_ELABORATION_DIR : string;
|
||||||
|
attribute C_ELABORATION_DIR of U0 : label is "./";
|
||||||
|
attribute C_ENABLE_32BIT_ADDRESS : integer;
|
||||||
|
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
|
||||||
|
attribute C_EN_DEEPSLEEP_PIN : integer;
|
||||||
|
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
|
||||||
|
attribute C_EN_ECC_PIPE : integer;
|
||||||
|
attribute C_EN_ECC_PIPE of U0 : label is 0;
|
||||||
|
attribute C_EN_RDADDRA_CHG : integer;
|
||||||
|
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
|
||||||
|
attribute C_EN_RDADDRB_CHG : integer;
|
||||||
|
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
|
||||||
|
attribute C_EN_SAFETY_CKT : integer;
|
||||||
|
attribute C_EN_SAFETY_CKT of U0 : label is 0;
|
||||||
|
attribute C_EN_SHUTDOWN_PIN : integer;
|
||||||
|
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
|
||||||
|
attribute C_EN_SLEEP_PIN : integer;
|
||||||
|
attribute C_EN_SLEEP_PIN of U0 : label is 0;
|
||||||
|
attribute C_EST_POWER_SUMMARY : string;
|
||||||
|
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.5432 mW";
|
||||||
|
attribute C_FAMILY : string;
|
||||||
|
attribute C_FAMILY of U0 : label is "artix7";
|
||||||
|
attribute C_HAS_AXI_ID : integer;
|
||||||
|
attribute C_HAS_AXI_ID of U0 : label is 0;
|
||||||
|
attribute C_HAS_ENA : integer;
|
||||||
|
attribute C_HAS_ENA of U0 : label is 1;
|
||||||
|
attribute C_HAS_ENB : integer;
|
||||||
|
attribute C_HAS_ENB of U0 : label is 0;
|
||||||
|
attribute C_HAS_INJECTERR : integer;
|
||||||
|
attribute C_HAS_INJECTERR of U0 : label is 0;
|
||||||
|
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
|
||||||
|
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
|
||||||
|
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
|
||||||
|
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
|
||||||
|
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
|
||||||
|
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
|
||||||
|
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
|
||||||
|
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
|
||||||
|
attribute C_HAS_REGCEA : integer;
|
||||||
|
attribute C_HAS_REGCEA of U0 : label is 0;
|
||||||
|
attribute C_HAS_REGCEB : integer;
|
||||||
|
attribute C_HAS_REGCEB of U0 : label is 0;
|
||||||
|
attribute C_HAS_RSTA : integer;
|
||||||
|
attribute C_HAS_RSTA of U0 : label is 0;
|
||||||
|
attribute C_HAS_RSTB : integer;
|
||||||
|
attribute C_HAS_RSTB of U0 : label is 0;
|
||||||
|
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
|
||||||
|
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
|
||||||
|
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
|
||||||
|
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
|
||||||
|
attribute C_INITA_VAL : string;
|
||||||
|
attribute C_INITA_VAL of U0 : label is "0";
|
||||||
|
attribute C_INITB_VAL : string;
|
||||||
|
attribute C_INITB_VAL of U0 : label is "0";
|
||||||
|
attribute C_INIT_FILE : string;
|
||||||
|
attribute C_INIT_FILE of U0 : label is "lightning_20_20.mem";
|
||||||
|
attribute C_INIT_FILE_NAME : string;
|
||||||
|
attribute C_INIT_FILE_NAME of U0 : label is "lightning_20_20.mif";
|
||||||
|
attribute C_INTERFACE_TYPE : integer;
|
||||||
|
attribute C_INTERFACE_TYPE of U0 : label is 0;
|
||||||
|
attribute C_LOAD_INIT_FILE : integer;
|
||||||
|
attribute C_LOAD_INIT_FILE of U0 : label is 1;
|
||||||
|
attribute C_MEM_TYPE : integer;
|
||||||
|
attribute C_MEM_TYPE of U0 : label is 3;
|
||||||
|
attribute C_MUX_PIPELINE_STAGES : integer;
|
||||||
|
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
|
||||||
|
attribute C_PRIM_TYPE : integer;
|
||||||
|
attribute C_PRIM_TYPE of U0 : label is 1;
|
||||||
|
attribute C_READ_DEPTH_A : integer;
|
||||||
|
attribute C_READ_DEPTH_A of U0 : label is 400;
|
||||||
|
attribute C_READ_DEPTH_B : integer;
|
||||||
|
attribute C_READ_DEPTH_B of U0 : label is 400;
|
||||||
|
attribute C_READ_LATENCY_A : integer;
|
||||||
|
attribute C_READ_LATENCY_A of U0 : label is 1;
|
||||||
|
attribute C_READ_LATENCY_B : integer;
|
||||||
|
attribute C_READ_LATENCY_B of U0 : label is 1;
|
||||||
|
attribute C_READ_WIDTH_A : integer;
|
||||||
|
attribute C_READ_WIDTH_A of U0 : label is 12;
|
||||||
|
attribute C_READ_WIDTH_B : integer;
|
||||||
|
attribute C_READ_WIDTH_B of U0 : label is 12;
|
||||||
|
attribute C_RSTRAM_A : integer;
|
||||||
|
attribute C_RSTRAM_A of U0 : label is 0;
|
||||||
|
attribute C_RSTRAM_B : integer;
|
||||||
|
attribute C_RSTRAM_B of U0 : label is 0;
|
||||||
|
attribute C_RST_PRIORITY_A : string;
|
||||||
|
attribute C_RST_PRIORITY_A of U0 : label is "CE";
|
||||||
|
attribute C_RST_PRIORITY_B : string;
|
||||||
|
attribute C_RST_PRIORITY_B of U0 : label is "CE";
|
||||||
|
attribute C_SIM_COLLISION_CHECK : string;
|
||||||
|
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
|
||||||
|
attribute C_USE_BRAM_BLOCK : integer;
|
||||||
|
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
|
||||||
|
attribute C_USE_BYTE_WEA : integer;
|
||||||
|
attribute C_USE_BYTE_WEA of U0 : label is 0;
|
||||||
|
attribute C_USE_BYTE_WEB : integer;
|
||||||
|
attribute C_USE_BYTE_WEB of U0 : label is 0;
|
||||||
|
attribute C_USE_DEFAULT_DATA : integer;
|
||||||
|
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
|
||||||
|
attribute C_USE_ECC : integer;
|
||||||
|
attribute C_USE_ECC of U0 : label is 0;
|
||||||
|
attribute C_USE_SOFTECC : integer;
|
||||||
|
attribute C_USE_SOFTECC of U0 : label is 0;
|
||||||
|
attribute C_USE_URAM : integer;
|
||||||
|
attribute C_USE_URAM of U0 : label is 0;
|
||||||
|
attribute C_WEA_WIDTH : integer;
|
||||||
|
attribute C_WEA_WIDTH of U0 : label is 1;
|
||||||
|
attribute C_WEB_WIDTH : integer;
|
||||||
|
attribute C_WEB_WIDTH of U0 : label is 1;
|
||||||
|
attribute C_WRITE_DEPTH_A : integer;
|
||||||
|
attribute C_WRITE_DEPTH_A of U0 : label is 400;
|
||||||
|
attribute C_WRITE_DEPTH_B : integer;
|
||||||
|
attribute C_WRITE_DEPTH_B of U0 : label is 400;
|
||||||
|
attribute C_WRITE_MODE_A : string;
|
||||||
|
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
|
||||||
|
attribute C_WRITE_MODE_B : string;
|
||||||
|
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
|
||||||
|
attribute C_WRITE_WIDTH_A : integer;
|
||||||
|
attribute C_WRITE_WIDTH_A of U0 : label is 12;
|
||||||
|
attribute C_WRITE_WIDTH_B : integer;
|
||||||
|
attribute C_WRITE_WIDTH_B of U0 : label is 12;
|
||||||
|
attribute C_XDEVICEFAMILY : string;
|
||||||
|
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
|
||||||
|
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
|
||||||
|
attribute x_interface_info : string;
|
||||||
|
attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
|
||||||
|
attribute x_interface_parameter : string;
|
||||||
|
attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
|
||||||
|
attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
|
||||||
|
attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
|
||||||
|
attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
|
||||||
|
begin
|
||||||
|
U0: entity work.lightning_20_20_blk_mem_gen_v8_4_4
|
||||||
|
port map (
|
||||||
|
addra(8 downto 0) => addra(8 downto 0),
|
||||||
|
addrb(8 downto 0) => B"000000000",
|
||||||
|
clka => clka,
|
||||||
|
clkb => '0',
|
||||||
|
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
|
||||||
|
deepsleep => '0',
|
||||||
|
dina(11 downto 0) => B"000000000000",
|
||||||
|
dinb(11 downto 0) => B"000000000000",
|
||||||
|
douta(11 downto 0) => douta(11 downto 0),
|
||||||
|
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
|
||||||
|
eccpipece => '0',
|
||||||
|
ena => ena,
|
||||||
|
enb => '0',
|
||||||
|
injectdbiterr => '0',
|
||||||
|
injectsbiterr => '0',
|
||||||
|
rdaddrecc(8 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(8 downto 0),
|
||||||
|
regcea => '0',
|
||||||
|
regceb => '0',
|
||||||
|
rsta => '0',
|
||||||
|
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
|
||||||
|
rstb => '0',
|
||||||
|
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
|
||||||
|
s_aclk => '0',
|
||||||
|
s_aresetn => '0',
|
||||||
|
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
|
||||||
|
s_axi_arburst(1 downto 0) => B"00",
|
||||||
|
s_axi_arid(3 downto 0) => B"0000",
|
||||||
|
s_axi_arlen(7 downto 0) => B"00000000",
|
||||||
|
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
|
||||||
|
s_axi_arsize(2 downto 0) => B"000",
|
||||||
|
s_axi_arvalid => '0',
|
||||||
|
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
|
||||||
|
s_axi_awburst(1 downto 0) => B"00",
|
||||||
|
s_axi_awid(3 downto 0) => B"0000",
|
||||||
|
s_axi_awlen(7 downto 0) => B"00000000",
|
||||||
|
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
|
||||||
|
s_axi_awsize(2 downto 0) => B"000",
|
||||||
|
s_axi_awvalid => '0',
|
||||||
|
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
|
||||||
|
s_axi_bready => '0',
|
||||||
|
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
|
||||||
|
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
|
||||||
|
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
|
||||||
|
s_axi_injectdbiterr => '0',
|
||||||
|
s_axi_injectsbiterr => '0',
|
||||||
|
s_axi_rdaddrecc(8 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(8 downto 0),
|
||||||
|
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
|
||||||
|
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
|
||||||
|
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
|
||||||
|
s_axi_rready => '0',
|
||||||
|
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
|
||||||
|
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
|
||||||
|
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
|
||||||
|
s_axi_wdata(11 downto 0) => B"000000000000",
|
||||||
|
s_axi_wlast => '0',
|
||||||
|
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
|
||||||
|
s_axi_wstrb(0) => '0',
|
||||||
|
s_axi_wvalid => '0',
|
||||||
|
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
|
||||||
|
shutdown => '0',
|
||||||
|
sleep => '0',
|
||||||
|
wea(0) => '0',
|
||||||
|
web(0) => '0'
|
||||||
|
);
|
||||||
|
end STRUCTURE;
|
||||||
|
|
@ -0,0 +1,150 @@
|
||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity blk_mem_gen_v8_4_4 is
|
||||||
|
generic (
|
||||||
|
C_FAMILY : string := "virtex7";
|
||||||
|
C_XDEVICEFAMILY : string := "virtex7";
|
||||||
|
C_ELABORATION_DIR : string := "";
|
||||||
|
C_INTERFACE_TYPE : integer := 0;
|
||||||
|
C_AXI_TYPE : integer := 1;
|
||||||
|
C_AXI_SLAVE_TYPE : integer := 0;
|
||||||
|
C_USE_BRAM_BLOCK : integer := 0;
|
||||||
|
C_ENABLE_32BIT_ADDRESS : integer := 0;
|
||||||
|
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
|
||||||
|
C_HAS_AXI_ID : integer := 0;
|
||||||
|
C_AXI_ID_WIDTH : integer := 4;
|
||||||
|
C_MEM_TYPE : integer := 2;
|
||||||
|
C_BYTE_SIZE : integer := 9;
|
||||||
|
C_ALGORITHM : integer := 0;
|
||||||
|
C_PRIM_TYPE : integer := 3;
|
||||||
|
C_LOAD_INIT_FILE : integer := 0;
|
||||||
|
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
|
||||||
|
C_INIT_FILE : string := "no_mem_file_loaded";
|
||||||
|
C_USE_DEFAULT_DATA : integer := 0;
|
||||||
|
C_DEFAULT_DATA : string := "0";
|
||||||
|
C_HAS_RSTA : integer := 0;
|
||||||
|
C_RST_PRIORITY_A : string := "ce";
|
||||||
|
C_RSTRAM_A : integer := 0;
|
||||||
|
C_INITA_VAL : string := "0";
|
||||||
|
C_HAS_ENA : integer := 1;
|
||||||
|
C_HAS_REGCEA : integer := 0;
|
||||||
|
C_USE_BYTE_WEA : integer := 0;
|
||||||
|
C_WEA_WIDTH : integer := 1;
|
||||||
|
C_WRITE_MODE_A : string := "WRITE_FIRST";
|
||||||
|
C_WRITE_WIDTH_A : integer := 9;
|
||||||
|
C_READ_WIDTH_A : integer := 9;
|
||||||
|
C_WRITE_DEPTH_A : integer := 2048;
|
||||||
|
C_READ_DEPTH_A : integer := 2048;
|
||||||
|
C_ADDRA_WIDTH : integer := 11;
|
||||||
|
C_HAS_RSTB : integer := 0;
|
||||||
|
C_RST_PRIORITY_B : string := "ce";
|
||||||
|
C_RSTRAM_B : integer := 0;
|
||||||
|
C_INITB_VAL : string := "0";
|
||||||
|
C_HAS_ENB : integer := 1;
|
||||||
|
C_HAS_REGCEB : integer := 0;
|
||||||
|
C_USE_BYTE_WEB : integer := 0;
|
||||||
|
C_WEB_WIDTH : integer := 1;
|
||||||
|
C_WRITE_MODE_B : string := "WRITE_FIRST";
|
||||||
|
C_WRITE_WIDTH_B : integer := 9;
|
||||||
|
C_READ_WIDTH_B : integer := 9;
|
||||||
|
C_WRITE_DEPTH_B : integer := 2048;
|
||||||
|
C_READ_DEPTH_B : integer := 2048;
|
||||||
|
C_ADDRB_WIDTH : integer := 11;
|
||||||
|
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
|
||||||
|
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
|
||||||
|
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
|
||||||
|
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
|
||||||
|
C_MUX_PIPELINE_STAGES : integer := 0;
|
||||||
|
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
|
||||||
|
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
|
||||||
|
C_USE_SOFTECC : integer := 0;
|
||||||
|
C_USE_ECC : integer := 0;
|
||||||
|
C_EN_ECC_PIPE : integer := 0;
|
||||||
|
C_HAS_INJECTERR : integer := 0;
|
||||||
|
C_SIM_COLLISION_CHECK : string := "none";
|
||||||
|
C_COMMON_CLK : integer := 0;
|
||||||
|
C_DISABLE_WARN_BHV_COLL : integer := 0;
|
||||||
|
C_EN_SLEEP_PIN : integer := 0;
|
||||||
|
C_USE_URAM : integer := 0;
|
||||||
|
C_EN_RDADDRA_CHG : integer := 0;
|
||||||
|
C_EN_RDADDRB_CHG : integer := 0;
|
||||||
|
C_EN_DEEPSLEEP_PIN : integer := 0;
|
||||||
|
C_EN_SHUTDOWN_PIN : integer := 0;
|
||||||
|
C_EN_SAFETY_CKT : integer := 0;
|
||||||
|
C_DISABLE_WARN_BHV_RANGE : integer := 0;
|
||||||
|
C_COUNT_36K_BRAM : string := "";
|
||||||
|
C_COUNT_18K_BRAM : string := "";
|
||||||
|
C_EST_POWER_SUMMARY : string := ""
|
||||||
|
);
|
||||||
|
port (
|
||||||
|
clka : in std_logic := '0';
|
||||||
|
rsta : in std_logic := '0';
|
||||||
|
ena : in std_logic := '0';
|
||||||
|
regcea : in std_logic := '0';
|
||||||
|
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
|
||||||
|
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
|
||||||
|
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
|
||||||
|
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
|
||||||
|
clkb : in std_logic := '0';
|
||||||
|
rstb : in std_logic := '0';
|
||||||
|
enb : in std_logic := '0';
|
||||||
|
regceb : in std_logic := '0';
|
||||||
|
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
|
||||||
|
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
|
||||||
|
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
|
||||||
|
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
|
||||||
|
injectsbiterr : in std_logic := '0';
|
||||||
|
injectdbiterr : in std_logic := '0';
|
||||||
|
eccpipece : in std_logic := '0';
|
||||||
|
sbiterr : out std_logic;
|
||||||
|
dbiterr : out std_logic;
|
||||||
|
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
|
||||||
|
sleep : in std_logic := '0';
|
||||||
|
deepsleep : in std_logic := '0';
|
||||||
|
shutdown : in std_logic := '0';
|
||||||
|
rsta_busy : out std_logic;
|
||||||
|
rstb_busy : out std_logic;
|
||||||
|
s_aclk : in std_logic := '0';
|
||||||
|
s_aresetn : in std_logic := '0';
|
||||||
|
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
|
||||||
|
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
|
||||||
|
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
|
||||||
|
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
|
||||||
|
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
|
||||||
|
s_axi_awvalid : in std_logic := '0';
|
||||||
|
s_axi_awready : out std_logic;
|
||||||
|
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
|
||||||
|
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
|
||||||
|
s_axi_wlast : in std_logic := '0';
|
||||||
|
s_axi_wvalid : in std_logic := '0';
|
||||||
|
s_axi_wready : out std_logic;
|
||||||
|
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
|
||||||
|
s_axi_bresp : out std_logic_vector(1 downto 0);
|
||||||
|
s_axi_bvalid : out std_logic;
|
||||||
|
s_axi_bready : in std_logic := '0';
|
||||||
|
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
|
||||||
|
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
|
||||||
|
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
|
||||||
|
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
|
||||||
|
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
|
||||||
|
s_axi_arvalid : in std_logic := '0';
|
||||||
|
s_axi_arready : out std_logic;
|
||||||
|
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
|
||||||
|
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
|
||||||
|
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
|
||||||
|
s_axi_rlast : out std_logic;
|
||||||
|
s_axi_rvalid : out std_logic;
|
||||||
|
s_axi_rready : in std_logic := '0';
|
||||||
|
s_axi_injectsbiterr : in std_logic := '0';
|
||||||
|
s_axi_injectdbiterr : in std_logic := '0';
|
||||||
|
s_axi_sbiterr : out std_logic;
|
||||||
|
s_axi_dbiterr : out std_logic;
|
||||||
|
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
|
||||||
|
);
|
||||||
|
end entity blk_mem_gen_v8_4_4;
|
||||||
|
|
||||||
|
architecture xilinx of blk_mem_gen_v8_4_4 is
|
||||||
|
begin
|
||||||
|
end
|
||||||
|
architecture xilinx;
|
||||||
|
|
@ -0,0 +1,214 @@
|
||||||
|
// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||||
|
// IP Revision: 4
|
||||||
|
|
||||||
|
`timescale 1ns/1ps
|
||||||
|
|
||||||
|
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||||
|
module lightning_20_20 (
|
||||||
|
clka,
|
||||||
|
ena,
|
||||||
|
addra,
|
||||||
|
douta
|
||||||
|
);
|
||||||
|
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
|
||||||
|
input wire clka;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
|
||||||
|
input wire ena;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
|
||||||
|
input wire [8 : 0] addra;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
|
||||||
|
output wire [11 : 0] douta;
|
||||||
|
|
||||||
|
blk_mem_gen_v8_4_4 #(
|
||||||
|
.C_FAMILY("artix7"),
|
||||||
|
.C_XDEVICEFAMILY("artix7"),
|
||||||
|
.C_ELABORATION_DIR("./"),
|
||||||
|
.C_INTERFACE_TYPE(0),
|
||||||
|
.C_AXI_TYPE(1),
|
||||||
|
.C_AXI_SLAVE_TYPE(0),
|
||||||
|
.C_USE_BRAM_BLOCK(0),
|
||||||
|
.C_ENABLE_32BIT_ADDRESS(0),
|
||||||
|
.C_CTRL_ECC_ALGO("NONE"),
|
||||||
|
.C_HAS_AXI_ID(0),
|
||||||
|
.C_AXI_ID_WIDTH(4),
|
||||||
|
.C_MEM_TYPE(3),
|
||||||
|
.C_BYTE_SIZE(9),
|
||||||
|
.C_ALGORITHM(1),
|
||||||
|
.C_PRIM_TYPE(1),
|
||||||
|
.C_LOAD_INIT_FILE(1),
|
||||||
|
.C_INIT_FILE_NAME("lightning_20_20.mif"),
|
||||||
|
.C_INIT_FILE("lightning_20_20.mem"),
|
||||||
|
.C_USE_DEFAULT_DATA(0),
|
||||||
|
.C_DEFAULT_DATA("0"),
|
||||||
|
.C_HAS_RSTA(0),
|
||||||
|
.C_RST_PRIORITY_A("CE"),
|
||||||
|
.C_RSTRAM_A(0),
|
||||||
|
.C_INITA_VAL("0"),
|
||||||
|
.C_HAS_ENA(1),
|
||||||
|
.C_HAS_REGCEA(0),
|
||||||
|
.C_USE_BYTE_WEA(0),
|
||||||
|
.C_WEA_WIDTH(1),
|
||||||
|
.C_WRITE_MODE_A("WRITE_FIRST"),
|
||||||
|
.C_WRITE_WIDTH_A(12),
|
||||||
|
.C_READ_WIDTH_A(12),
|
||||||
|
.C_WRITE_DEPTH_A(400),
|
||||||
|
.C_READ_DEPTH_A(400),
|
||||||
|
.C_ADDRA_WIDTH(9),
|
||||||
|
.C_HAS_RSTB(0),
|
||||||
|
.C_RST_PRIORITY_B("CE"),
|
||||||
|
.C_RSTRAM_B(0),
|
||||||
|
.C_INITB_VAL("0"),
|
||||||
|
.C_HAS_ENB(0),
|
||||||
|
.C_HAS_REGCEB(0),
|
||||||
|
.C_USE_BYTE_WEB(0),
|
||||||
|
.C_WEB_WIDTH(1),
|
||||||
|
.C_WRITE_MODE_B("WRITE_FIRST"),
|
||||||
|
.C_WRITE_WIDTH_B(12),
|
||||||
|
.C_READ_WIDTH_B(12),
|
||||||
|
.C_WRITE_DEPTH_B(400),
|
||||||
|
.C_READ_DEPTH_B(400),
|
||||||
|
.C_ADDRB_WIDTH(9),
|
||||||
|
.C_HAS_MEM_OUTPUT_REGS_A(1),
|
||||||
|
.C_HAS_MEM_OUTPUT_REGS_B(0),
|
||||||
|
.C_HAS_MUX_OUTPUT_REGS_A(0),
|
||||||
|
.C_HAS_MUX_OUTPUT_REGS_B(0),
|
||||||
|
.C_MUX_PIPELINE_STAGES(0),
|
||||||
|
.C_HAS_SOFTECC_INPUT_REGS_A(0),
|
||||||
|
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
|
||||||
|
.C_USE_SOFTECC(0),
|
||||||
|
.C_USE_ECC(0),
|
||||||
|
.C_EN_ECC_PIPE(0),
|
||||||
|
.C_READ_LATENCY_A(1),
|
||||||
|
.C_READ_LATENCY_B(1),
|
||||||
|
.C_HAS_INJECTERR(0),
|
||||||
|
.C_SIM_COLLISION_CHECK("ALL"),
|
||||||
|
.C_COMMON_CLK(0),
|
||||||
|
.C_DISABLE_WARN_BHV_COLL(0),
|
||||||
|
.C_EN_SLEEP_PIN(0),
|
||||||
|
.C_USE_URAM(0),
|
||||||
|
.C_EN_RDADDRA_CHG(0),
|
||||||
|
.C_EN_RDADDRB_CHG(0),
|
||||||
|
.C_EN_DEEPSLEEP_PIN(0),
|
||||||
|
.C_EN_SHUTDOWN_PIN(0),
|
||||||
|
.C_EN_SAFETY_CKT(0),
|
||||||
|
.C_DISABLE_WARN_BHV_RANGE(0),
|
||||||
|
.C_COUNT_36K_BRAM("0"),
|
||||||
|
.C_COUNT_18K_BRAM("1"),
|
||||||
|
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.5432 mW")
|
||||||
|
) inst (
|
||||||
|
.clka(clka),
|
||||||
|
.rsta(1'D0),
|
||||||
|
.ena(ena),
|
||||||
|
.regcea(1'D0),
|
||||||
|
.wea(1'B0),
|
||||||
|
.addra(addra),
|
||||||
|
.dina(12'B0),
|
||||||
|
.douta(douta),
|
||||||
|
.clkb(1'D0),
|
||||||
|
.rstb(1'D0),
|
||||||
|
.enb(1'D0),
|
||||||
|
.regceb(1'D0),
|
||||||
|
.web(1'B0),
|
||||||
|
.addrb(9'B0),
|
||||||
|
.dinb(12'B0),
|
||||||
|
.doutb(),
|
||||||
|
.injectsbiterr(1'D0),
|
||||||
|
.injectdbiterr(1'D0),
|
||||||
|
.eccpipece(1'D0),
|
||||||
|
.sbiterr(),
|
||||||
|
.dbiterr(),
|
||||||
|
.rdaddrecc(),
|
||||||
|
.sleep(1'D0),
|
||||||
|
.deepsleep(1'D0),
|
||||||
|
.shutdown(1'D0),
|
||||||
|
.rsta_busy(),
|
||||||
|
.rstb_busy(),
|
||||||
|
.s_aclk(1'H0),
|
||||||
|
.s_aresetn(1'D0),
|
||||||
|
.s_axi_awid(4'B0),
|
||||||
|
.s_axi_awaddr(32'B0),
|
||||||
|
.s_axi_awlen(8'B0),
|
||||||
|
.s_axi_awsize(3'B0),
|
||||||
|
.s_axi_awburst(2'B0),
|
||||||
|
.s_axi_awvalid(1'D0),
|
||||||
|
.s_axi_awready(),
|
||||||
|
.s_axi_wdata(12'B0),
|
||||||
|
.s_axi_wstrb(1'B0),
|
||||||
|
.s_axi_wlast(1'D0),
|
||||||
|
.s_axi_wvalid(1'D0),
|
||||||
|
.s_axi_wready(),
|
||||||
|
.s_axi_bid(),
|
||||||
|
.s_axi_bresp(),
|
||||||
|
.s_axi_bvalid(),
|
||||||
|
.s_axi_bready(1'D0),
|
||||||
|
.s_axi_arid(4'B0),
|
||||||
|
.s_axi_araddr(32'B0),
|
||||||
|
.s_axi_arlen(8'B0),
|
||||||
|
.s_axi_arsize(3'B0),
|
||||||
|
.s_axi_arburst(2'B0),
|
||||||
|
.s_axi_arvalid(1'D0),
|
||||||
|
.s_axi_arready(),
|
||||||
|
.s_axi_rid(),
|
||||||
|
.s_axi_rdata(),
|
||||||
|
.s_axi_rresp(),
|
||||||
|
.s_axi_rlast(),
|
||||||
|
.s_axi_rvalid(),
|
||||||
|
.s_axi_rready(1'D0),
|
||||||
|
.s_axi_injectsbiterr(1'D0),
|
||||||
|
.s_axi_injectdbiterr(1'D0),
|
||||||
|
.s_axi_sbiterr(),
|
||||||
|
.s_axi_dbiterr(),
|
||||||
|
.s_axi_rdaddrecc()
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,355 @@
|
||||||
|
-- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
|
||||||
|
--
|
||||||
|
-- This file contains confidential and proprietary information
|
||||||
|
-- of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
-- international copyright and other intellectual property
|
||||||
|
-- laws.
|
||||||
|
--
|
||||||
|
-- DISCLAIMER
|
||||||
|
-- This disclaimer is not a license and does not grant any
|
||||||
|
-- rights to the materials distributed herewith. Except as
|
||||||
|
-- otherwise provided in a valid license issued to you by
|
||||||
|
-- Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
-- including negligence, or under any other theory of
|
||||||
|
-- liability) for any loss or damage of any kind or nature
|
||||||
|
-- related to, arising under or in connection with these
|
||||||
|
-- materials, including for any direct, or any indirect,
|
||||||
|
-- special, incidental, or consequential loss or damage
|
||||||
|
-- (including loss of data, profits, goodwill, or any type of
|
||||||
|
-- loss or damage suffered as a result of any action brought
|
||||||
|
-- by a third party) even if such damage or loss was
|
||||||
|
-- reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
-- possibility of the same.
|
||||||
|
--
|
||||||
|
-- CRITICAL APPLICATIONS
|
||||||
|
-- Xilinx products are not designed or intended to be fail-
|
||||||
|
-- safe, or for use in any application requiring fail-safe
|
||||||
|
-- performance, such as life-support or safety devices or
|
||||||
|
-- systems, Class III medical devices, nuclear facilities,
|
||||||
|
-- applications related to the deployment of airbags, or any
|
||||||
|
-- other applications that could lead to death, personal
|
||||||
|
-- injury, or severe property or environmental damage
|
||||||
|
-- (individually and collectively, "Critical
|
||||||
|
-- Applications"). Customer assumes the sole risk and
|
||||||
|
-- liability of any use of Xilinx products in Critical
|
||||||
|
-- Applications, subject only to applicable laws and
|
||||||
|
-- regulations governing limitations on product liability.
|
||||||
|
--
|
||||||
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
-- PART OF THIS FILE AT ALL TIMES.
|
||||||
|
--
|
||||||
|
-- DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||||
|
-- IP Revision: 4
|
||||||
|
|
||||||
|
LIBRARY ieee;
|
||||||
|
USE ieee.std_logic_1164.ALL;
|
||||||
|
USE ieee.numeric_std.ALL;
|
||||||
|
|
||||||
|
LIBRARY blk_mem_gen_v8_4_4;
|
||||||
|
USE blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4;
|
||||||
|
|
||||||
|
ENTITY lightning_20_20 IS
|
||||||
|
PORT (
|
||||||
|
clka : IN STD_LOGIC;
|
||||||
|
ena : IN STD_LOGIC;
|
||||||
|
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||||
|
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END lightning_20_20;
|
||||||
|
|
||||||
|
ARCHITECTURE lightning_20_20_arch OF lightning_20_20 IS
|
||||||
|
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||||
|
ATTRIBUTE DowngradeIPIdentifiedWarnings OF lightning_20_20_arch: ARCHITECTURE IS "yes";
|
||||||
|
COMPONENT blk_mem_gen_v8_4_4 IS
|
||||||
|
GENERIC (
|
||||||
|
C_FAMILY : STRING;
|
||||||
|
C_XDEVICEFAMILY : STRING;
|
||||||
|
C_ELABORATION_DIR : STRING;
|
||||||
|
C_INTERFACE_TYPE : INTEGER;
|
||||||
|
C_AXI_TYPE : INTEGER;
|
||||||
|
C_AXI_SLAVE_TYPE : INTEGER;
|
||||||
|
C_USE_BRAM_BLOCK : INTEGER;
|
||||||
|
C_ENABLE_32BIT_ADDRESS : INTEGER;
|
||||||
|
C_CTRL_ECC_ALGO : STRING;
|
||||||
|
C_HAS_AXI_ID : INTEGER;
|
||||||
|
C_AXI_ID_WIDTH : INTEGER;
|
||||||
|
C_MEM_TYPE : INTEGER;
|
||||||
|
C_BYTE_SIZE : INTEGER;
|
||||||
|
C_ALGORITHM : INTEGER;
|
||||||
|
C_PRIM_TYPE : INTEGER;
|
||||||
|
C_LOAD_INIT_FILE : INTEGER;
|
||||||
|
C_INIT_FILE_NAME : STRING;
|
||||||
|
C_INIT_FILE : STRING;
|
||||||
|
C_USE_DEFAULT_DATA : INTEGER;
|
||||||
|
C_DEFAULT_DATA : STRING;
|
||||||
|
C_HAS_RSTA : INTEGER;
|
||||||
|
C_RST_PRIORITY_A : STRING;
|
||||||
|
C_RSTRAM_A : INTEGER;
|
||||||
|
C_INITA_VAL : STRING;
|
||||||
|
C_HAS_ENA : INTEGER;
|
||||||
|
C_HAS_REGCEA : INTEGER;
|
||||||
|
C_USE_BYTE_WEA : INTEGER;
|
||||||
|
C_WEA_WIDTH : INTEGER;
|
||||||
|
C_WRITE_MODE_A : STRING;
|
||||||
|
C_WRITE_WIDTH_A : INTEGER;
|
||||||
|
C_READ_WIDTH_A : INTEGER;
|
||||||
|
C_WRITE_DEPTH_A : INTEGER;
|
||||||
|
C_READ_DEPTH_A : INTEGER;
|
||||||
|
C_ADDRA_WIDTH : INTEGER;
|
||||||
|
C_HAS_RSTB : INTEGER;
|
||||||
|
C_RST_PRIORITY_B : STRING;
|
||||||
|
C_RSTRAM_B : INTEGER;
|
||||||
|
C_INITB_VAL : STRING;
|
||||||
|
C_HAS_ENB : INTEGER;
|
||||||
|
C_HAS_REGCEB : INTEGER;
|
||||||
|
C_USE_BYTE_WEB : INTEGER;
|
||||||
|
C_WEB_WIDTH : INTEGER;
|
||||||
|
C_WRITE_MODE_B : STRING;
|
||||||
|
C_WRITE_WIDTH_B : INTEGER;
|
||||||
|
C_READ_WIDTH_B : INTEGER;
|
||||||
|
C_WRITE_DEPTH_B : INTEGER;
|
||||||
|
C_READ_DEPTH_B : INTEGER;
|
||||||
|
C_ADDRB_WIDTH : INTEGER;
|
||||||
|
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
|
||||||
|
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
|
||||||
|
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
|
||||||
|
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
|
||||||
|
C_MUX_PIPELINE_STAGES : INTEGER;
|
||||||
|
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
|
||||||
|
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
|
||||||
|
C_USE_SOFTECC : INTEGER;
|
||||||
|
C_USE_ECC : INTEGER;
|
||||||
|
C_EN_ECC_PIPE : INTEGER;
|
||||||
|
C_READ_LATENCY_A : INTEGER;
|
||||||
|
C_READ_LATENCY_B : INTEGER;
|
||||||
|
C_HAS_INJECTERR : INTEGER;
|
||||||
|
C_SIM_COLLISION_CHECK : STRING;
|
||||||
|
C_COMMON_CLK : INTEGER;
|
||||||
|
C_DISABLE_WARN_BHV_COLL : INTEGER;
|
||||||
|
C_EN_SLEEP_PIN : INTEGER;
|
||||||
|
C_USE_URAM : INTEGER;
|
||||||
|
C_EN_RDADDRA_CHG : INTEGER;
|
||||||
|
C_EN_RDADDRB_CHG : INTEGER;
|
||||||
|
C_EN_DEEPSLEEP_PIN : INTEGER;
|
||||||
|
C_EN_SHUTDOWN_PIN : INTEGER;
|
||||||
|
C_EN_SAFETY_CKT : INTEGER;
|
||||||
|
C_DISABLE_WARN_BHV_RANGE : INTEGER;
|
||||||
|
C_COUNT_36K_BRAM : STRING;
|
||||||
|
C_COUNT_18K_BRAM : STRING;
|
||||||
|
C_EST_POWER_SUMMARY : STRING
|
||||||
|
);
|
||||||
|
PORT (
|
||||||
|
clka : IN STD_LOGIC;
|
||||||
|
rsta : IN STD_LOGIC;
|
||||||
|
ena : IN STD_LOGIC;
|
||||||
|
regcea : IN STD_LOGIC;
|
||||||
|
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||||
|
dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||||
|
douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||||
|
clkb : IN STD_LOGIC;
|
||||||
|
rstb : IN STD_LOGIC;
|
||||||
|
enb : IN STD_LOGIC;
|
||||||
|
regceb : IN STD_LOGIC;
|
||||||
|
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||||
|
dinb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||||
|
doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||||
|
injectsbiterr : IN STD_LOGIC;
|
||||||
|
injectdbiterr : IN STD_LOGIC;
|
||||||
|
eccpipece : IN STD_LOGIC;
|
||||||
|
sbiterr : OUT STD_LOGIC;
|
||||||
|
dbiterr : OUT STD_LOGIC;
|
||||||
|
rdaddrecc : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
|
||||||
|
sleep : IN STD_LOGIC;
|
||||||
|
deepsleep : IN STD_LOGIC;
|
||||||
|
shutdown : IN STD_LOGIC;
|
||||||
|
rsta_busy : OUT STD_LOGIC;
|
||||||
|
rstb_busy : OUT STD_LOGIC;
|
||||||
|
s_aclk : IN STD_LOGIC;
|
||||||
|
s_aresetn : IN STD_LOGIC;
|
||||||
|
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||||
|
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||||
|
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||||
|
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||||
|
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||||
|
s_axi_awvalid : IN STD_LOGIC;
|
||||||
|
s_axi_awready : OUT STD_LOGIC;
|
||||||
|
s_axi_wdata : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||||
|
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
s_axi_wlast : IN STD_LOGIC;
|
||||||
|
s_axi_wvalid : IN STD_LOGIC;
|
||||||
|
s_axi_wready : OUT STD_LOGIC;
|
||||||
|
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||||
|
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||||
|
s_axi_bvalid : OUT STD_LOGIC;
|
||||||
|
s_axi_bready : IN STD_LOGIC;
|
||||||
|
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||||
|
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||||
|
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||||
|
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||||
|
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||||
|
s_axi_arvalid : IN STD_LOGIC;
|
||||||
|
s_axi_arready : OUT STD_LOGIC;
|
||||||
|
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||||
|
s_axi_rdata : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||||
|
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||||
|
s_axi_rlast : OUT STD_LOGIC;
|
||||||
|
s_axi_rvalid : OUT STD_LOGIC;
|
||||||
|
s_axi_rready : IN STD_LOGIC;
|
||||||
|
s_axi_injectsbiterr : IN STD_LOGIC;
|
||||||
|
s_axi_injectdbiterr : IN STD_LOGIC;
|
||||||
|
s_axi_sbiterr : OUT STD_LOGIC;
|
||||||
|
s_axi_dbiterr : OUT STD_LOGIC;
|
||||||
|
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END COMPONENT blk_mem_gen_v8_4_4;
|
||||||
|
ATTRIBUTE X_CORE_INFO : STRING;
|
||||||
|
ATTRIBUTE X_CORE_INFO OF lightning_20_20_arch: ARCHITECTURE IS "blk_mem_gen_v8_4_4,Vivado 2019.2";
|
||||||
|
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||||
|
ATTRIBUTE CHECK_LICENSE_TYPE OF lightning_20_20_arch : ARCHITECTURE IS "lightning_20_20,blk_mem_gen_v8_4_4,{}";
|
||||||
|
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||||
|
ATTRIBUTE CORE_GENERATION_INFO OF lightning_20_20_arch: ARCHITECTURE IS "lightning_20_20,blk_mem_gen_v8_4_4,{x_ipProduct=Vivado 2019.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.4,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=lig" &
|
||||||
|
"htning_20_20.mif,C_INIT_FILE=lightning_20_20.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=400,C_READ_DEPTH_A=400,C_ADDRA_WIDTH=9,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH" &
|
||||||
|
"_B=12,C_WRITE_DEPTH_B=400,C_READ_DEPTH_B=400,C_ADDRB_WIDTH=9,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_READ_LATENCY_A=1,C_READ_LATENCY_B=1,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PI" &
|
||||||
|
"N=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.5432 mW}";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||||
|
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
|
||||||
|
ATTRIBUTE X_INTERFACE_PARAMETER OF clka: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
|
||||||
|
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
|
||||||
|
BEGIN
|
||||||
|
U0 : blk_mem_gen_v8_4_4
|
||||||
|
GENERIC MAP (
|
||||||
|
C_FAMILY => "artix7",
|
||||||
|
C_XDEVICEFAMILY => "artix7",
|
||||||
|
C_ELABORATION_DIR => "./",
|
||||||
|
C_INTERFACE_TYPE => 0,
|
||||||
|
C_AXI_TYPE => 1,
|
||||||
|
C_AXI_SLAVE_TYPE => 0,
|
||||||
|
C_USE_BRAM_BLOCK => 0,
|
||||||
|
C_ENABLE_32BIT_ADDRESS => 0,
|
||||||
|
C_CTRL_ECC_ALGO => "NONE",
|
||||||
|
C_HAS_AXI_ID => 0,
|
||||||
|
C_AXI_ID_WIDTH => 4,
|
||||||
|
C_MEM_TYPE => 3,
|
||||||
|
C_BYTE_SIZE => 9,
|
||||||
|
C_ALGORITHM => 1,
|
||||||
|
C_PRIM_TYPE => 1,
|
||||||
|
C_LOAD_INIT_FILE => 1,
|
||||||
|
C_INIT_FILE_NAME => "lightning_20_20.mif",
|
||||||
|
C_INIT_FILE => "lightning_20_20.mem",
|
||||||
|
C_USE_DEFAULT_DATA => 0,
|
||||||
|
C_DEFAULT_DATA => "0",
|
||||||
|
C_HAS_RSTA => 0,
|
||||||
|
C_RST_PRIORITY_A => "CE",
|
||||||
|
C_RSTRAM_A => 0,
|
||||||
|
C_INITA_VAL => "0",
|
||||||
|
C_HAS_ENA => 1,
|
||||||
|
C_HAS_REGCEA => 0,
|
||||||
|
C_USE_BYTE_WEA => 0,
|
||||||
|
C_WEA_WIDTH => 1,
|
||||||
|
C_WRITE_MODE_A => "WRITE_FIRST",
|
||||||
|
C_WRITE_WIDTH_A => 12,
|
||||||
|
C_READ_WIDTH_A => 12,
|
||||||
|
C_WRITE_DEPTH_A => 400,
|
||||||
|
C_READ_DEPTH_A => 400,
|
||||||
|
C_ADDRA_WIDTH => 9,
|
||||||
|
C_HAS_RSTB => 0,
|
||||||
|
C_RST_PRIORITY_B => "CE",
|
||||||
|
C_RSTRAM_B => 0,
|
||||||
|
C_INITB_VAL => "0",
|
||||||
|
C_HAS_ENB => 0,
|
||||||
|
C_HAS_REGCEB => 0,
|
||||||
|
C_USE_BYTE_WEB => 0,
|
||||||
|
C_WEB_WIDTH => 1,
|
||||||
|
C_WRITE_MODE_B => "WRITE_FIRST",
|
||||||
|
C_WRITE_WIDTH_B => 12,
|
||||||
|
C_READ_WIDTH_B => 12,
|
||||||
|
C_WRITE_DEPTH_B => 400,
|
||||||
|
C_READ_DEPTH_B => 400,
|
||||||
|
C_ADDRB_WIDTH => 9,
|
||||||
|
C_HAS_MEM_OUTPUT_REGS_A => 1,
|
||||||
|
C_HAS_MEM_OUTPUT_REGS_B => 0,
|
||||||
|
C_HAS_MUX_OUTPUT_REGS_A => 0,
|
||||||
|
C_HAS_MUX_OUTPUT_REGS_B => 0,
|
||||||
|
C_MUX_PIPELINE_STAGES => 0,
|
||||||
|
C_HAS_SOFTECC_INPUT_REGS_A => 0,
|
||||||
|
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
|
||||||
|
C_USE_SOFTECC => 0,
|
||||||
|
C_USE_ECC => 0,
|
||||||
|
C_EN_ECC_PIPE => 0,
|
||||||
|
C_READ_LATENCY_A => 1,
|
||||||
|
C_READ_LATENCY_B => 1,
|
||||||
|
C_HAS_INJECTERR => 0,
|
||||||
|
C_SIM_COLLISION_CHECK => "ALL",
|
||||||
|
C_COMMON_CLK => 0,
|
||||||
|
C_DISABLE_WARN_BHV_COLL => 0,
|
||||||
|
C_EN_SLEEP_PIN => 0,
|
||||||
|
C_USE_URAM => 0,
|
||||||
|
C_EN_RDADDRA_CHG => 0,
|
||||||
|
C_EN_RDADDRB_CHG => 0,
|
||||||
|
C_EN_DEEPSLEEP_PIN => 0,
|
||||||
|
C_EN_SHUTDOWN_PIN => 0,
|
||||||
|
C_EN_SAFETY_CKT => 0,
|
||||||
|
C_DISABLE_WARN_BHV_RANGE => 0,
|
||||||
|
C_COUNT_36K_BRAM => "0",
|
||||||
|
C_COUNT_18K_BRAM => "1",
|
||||||
|
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.5432 mW"
|
||||||
|
)
|
||||||
|
PORT MAP (
|
||||||
|
clka => clka,
|
||||||
|
rsta => '0',
|
||||||
|
ena => ena,
|
||||||
|
regcea => '0',
|
||||||
|
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||||
|
addra => addra,
|
||||||
|
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
|
||||||
|
douta => douta,
|
||||||
|
clkb => '0',
|
||||||
|
rstb => '0',
|
||||||
|
enb => '0',
|
||||||
|
regceb => '0',
|
||||||
|
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||||
|
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
|
||||||
|
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
|
||||||
|
injectsbiterr => '0',
|
||||||
|
injectdbiterr => '0',
|
||||||
|
eccpipece => '0',
|
||||||
|
sleep => '0',
|
||||||
|
deepsleep => '0',
|
||||||
|
shutdown => '0',
|
||||||
|
s_aclk => '0',
|
||||||
|
s_aresetn => '0',
|
||||||
|
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||||
|
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||||
|
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||||
|
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||||
|
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||||
|
s_axi_awvalid => '0',
|
||||||
|
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
|
||||||
|
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||||
|
s_axi_wlast => '0',
|
||||||
|
s_axi_wvalid => '0',
|
||||||
|
s_axi_bready => '0',
|
||||||
|
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||||
|
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||||
|
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||||
|
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||||
|
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||||
|
s_axi_arvalid => '0',
|
||||||
|
s_axi_rready => '0',
|
||||||
|
s_axi_injectsbiterr => '0',
|
||||||
|
s_axi_injectdbiterr => '0'
|
||||||
|
);
|
||||||
|
END lightning_20_20_arch;
|
||||||
|
|
@ -107,7 +107,6 @@ assign reset_n = ~BTNC;
|
||||||
|
|
||||||
clock MyClock(
|
clock MyClock(
|
||||||
.clk_100MHz( clk ),
|
.clk_100MHz( clk ),
|
||||||
.item_faster( item_faster ),
|
|
||||||
.clk_2Hz( clk_2Hz ),
|
.clk_2Hz( clk_2Hz ),
|
||||||
.clk_4Hz( clk_4Hz ),
|
.clk_4Hz( clk_4Hz ),
|
||||||
.clk_8Hz( clk_8Hz ),
|
.clk_8Hz( clk_8Hz ),
|
||||||
|
|
@ -343,41 +342,41 @@ tank_display enermy4_tank_display(
|
||||||
tank_move player1_tank_move(
|
tank_move player1_tank_move(
|
||||||
clk, reset_n, 1,
|
clk, reset_n, 1,
|
||||||
150, 150,
|
150, 150,
|
||||||
player1_tank_dir, player1_tank_en, player1_tank_move_en, 1'b0, player1_moving, item_frozen,
|
player1_tank_dir, player1_tank_en, player1_tank_move_en, 1'b0, player1_moving, item_frozen, item_faster,
|
||||||
player1_tank_H, player1_tank_V, player1_tank_moving_direction
|
player1_tank_H, player1_tank_V, player1_tank_moving_direction
|
||||||
);
|
);
|
||||||
|
|
||||||
tank_move player2_tank_move(
|
tank_move player2_tank_move(
|
||||||
clk, reset_n, 1,
|
clk, reset_n, 1,
|
||||||
350, 350,
|
350, 350,
|
||||||
player2_tank_dir, player2_tank_en, player2_tank_move_en, 1'b0, player2_moving, item_frozen,
|
player2_tank_dir, player2_tank_en, player2_tank_move_en, 1'b0, player2_moving, item_frozen, item_faster,
|
||||||
player2_tank_H, player2_tank_V, player2_tank_moving_direction
|
player2_tank_H, player2_tank_V, player2_tank_moving_direction
|
||||||
);
|
);
|
||||||
|
|
||||||
tank_move enermy1_tank_move(
|
tank_move enermy1_tank_move(
|
||||||
clk, reset_n, 1,
|
clk, reset_n, 1,
|
||||||
0, 0,
|
0, 0,
|
||||||
enermy1_tank_dir, enermy1_tank_en, enermy1_tank_move_en, 1'b1, enermy1_moving, item_frozen,
|
enermy1_tank_dir, enermy1_tank_en, enermy1_tank_move_en, 1'b1, enermy1_moving, item_frozen, item_faster,
|
||||||
enermy1_tank_H, enermy1_tank_V, enermy1_tank_moving_direction
|
enermy1_tank_H, enermy1_tank_V, enermy1_tank_moving_direction
|
||||||
);
|
);
|
||||||
|
|
||||||
tank_move enermy2_tank_move(
|
tank_move enermy2_tank_move(
|
||||||
clk, reset_n, 1,
|
clk, reset_n, 1,
|
||||||
540, 0,
|
540, 0,
|
||||||
enermy2_tank_dir, enermy2_tank_en, enermy2_tank_move_en, 1'b1, enermy2_moving, item_frozen,
|
enermy2_tank_dir, enermy2_tank_en, enermy2_tank_move_en, 1'b1, enermy2_moving, item_frozen, item_faster,
|
||||||
enermy2_tank_H, enermy2_tank_V, enermy2_tank_moving_direction
|
enermy2_tank_H, enermy2_tank_V, enermy2_tank_moving_direction
|
||||||
);
|
);
|
||||||
tank_move enermy3_tank_move(
|
tank_move enermy3_tank_move(
|
||||||
clk, reset_n, 1,
|
clk, reset_n, 1,
|
||||||
0, 350,
|
0, 350,
|
||||||
enermy3_tank_dir, enermy3_tank_en, enermy3_tank_move_en, 1'b1, enermy3_moving, item_frozen,
|
enermy3_tank_dir, enermy3_tank_en, enermy3_tank_move_en, 1'b1, enermy3_moving, item_frozen, item_faster,
|
||||||
enermy3_tank_H, enermy3_tank_V, enermy3_tank_moving_direction
|
enermy3_tank_H, enermy3_tank_V, enermy3_tank_moving_direction
|
||||||
);
|
);
|
||||||
|
|
||||||
tank_move enermy4_tank_move(
|
tank_move enermy4_tank_move(
|
||||||
clk, reset_n, 1,
|
clk, reset_n, 1,
|
||||||
540, 350,
|
540, 350,
|
||||||
enermy4_tank_dir, enermy4_tank_en, enermy4_tank_move_en, 1'b1, enermy4_moving, item_frozen,
|
enermy4_tank_dir, enermy4_tank_en, enermy4_tank_move_en, 1'b1, enermy4_moving, item_frozen, item_faster,
|
||||||
enermy4_tank_H, enermy4_tank_V, enermy4_tank_moving_direction
|
enermy4_tank_H, enermy4_tank_V, enermy4_tank_moving_direction
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
@ -493,6 +492,7 @@ enermy_control enermy4_control(
|
||||||
|
|
||||||
control_signals u_control_signals(
|
control_signals u_control_signals(
|
||||||
clk, reset_n,
|
clk, reset_n,
|
||||||
|
item_invincible,
|
||||||
player1_bullet_H, player1_bullet_V, player2_bullet_H, player2_bullet_V,
|
player1_bullet_H, player1_bullet_V, player2_bullet_H, player2_bullet_V,
|
||||||
enermy1_bullet_H, enermy1_bullet_V,
|
enermy1_bullet_H, enermy1_bullet_V,
|
||||||
enermy2_bullet_H, enermy2_bullet_V,
|
enermy2_bullet_H, enermy2_bullet_V,
|
||||||
|
|
@ -533,7 +533,7 @@ bullet_control bullet_player1(
|
||||||
.tank_dir( player1_tank_dir ),
|
.tank_dir( player1_tank_dir ),
|
||||||
.tank_fire( player1_fire ),
|
.tank_fire( player1_fire ),
|
||||||
.player_enermy( 1'b0 ),
|
.player_enermy( 1'b0 ),
|
||||||
|
.item_faster( item_faster ),
|
||||||
.vgaV( vgaV ),
|
.vgaV( vgaV ),
|
||||||
.vgaH( vgaH ),
|
.vgaH( vgaH ),
|
||||||
.start( 1 ),
|
.start( 1 ),
|
||||||
|
|
@ -553,7 +553,7 @@ bullet_control bullet_player2(
|
||||||
.tank_dir( player2_tank_dir ),
|
.tank_dir( player2_tank_dir ),
|
||||||
.tank_fire( player2_fire ),
|
.tank_fire( player2_fire ),
|
||||||
.player_enermy( 1'b0 ),
|
.player_enermy( 1'b0 ),
|
||||||
|
.item_faster( item_faster ),
|
||||||
.vgaV( vgaV ),
|
.vgaV( vgaV ),
|
||||||
.vgaH( vgaH ),
|
.vgaH( vgaH ),
|
||||||
.start( 1 ),
|
.start( 1 ),
|
||||||
|
|
@ -573,7 +573,7 @@ bullet_control bullet_enermy1(
|
||||||
.tank_dir( enermy1_tank_dir ),
|
.tank_dir( enermy1_tank_dir ),
|
||||||
.tank_fire( enermy1_fire ),
|
.tank_fire( enermy1_fire ),
|
||||||
.player_enermy( 1'b1 ),
|
.player_enermy( 1'b1 ),
|
||||||
|
.item_faster( item_faster ),
|
||||||
.vgaV( vgaV ),
|
.vgaV( vgaV ),
|
||||||
.vgaH( vgaH ),
|
.vgaH( vgaH ),
|
||||||
.start( 1 ),
|
.start( 1 ),
|
||||||
|
|
@ -593,7 +593,7 @@ bullet_control bullet_enermy2(
|
||||||
.tank_dir( enermy2_tank_dir ),
|
.tank_dir( enermy2_tank_dir ),
|
||||||
.tank_fire( enermy2_fire ),
|
.tank_fire( enermy2_fire ),
|
||||||
.player_enermy( 1'b1 ),
|
.player_enermy( 1'b1 ),
|
||||||
|
.item_faster( item_faster ),
|
||||||
.vgaV( vgaV ),
|
.vgaV( vgaV ),
|
||||||
.vgaH( vgaH ),
|
.vgaH( vgaH ),
|
||||||
.start( 1 ),
|
.start( 1 ),
|
||||||
|
|
@ -613,7 +613,7 @@ bullet_control bullet_enermy3(
|
||||||
.tank_dir( enermy3_tank_dir ),
|
.tank_dir( enermy3_tank_dir ),
|
||||||
.tank_fire( enermy3_fire ),
|
.tank_fire( enermy3_fire ),
|
||||||
.player_enermy( 1'b1 ),
|
.player_enermy( 1'b1 ),
|
||||||
|
.item_faster( item_faster ),
|
||||||
.vgaV( vgaV ),
|
.vgaV( vgaV ),
|
||||||
.vgaH( vgaH ),
|
.vgaH( vgaH ),
|
||||||
.start( 1 ),
|
.start( 1 ),
|
||||||
|
|
@ -633,7 +633,7 @@ bullet_control bullet_enermy4(
|
||||||
.tank_dir( enermy4_tank_dir ),
|
.tank_dir( enermy4_tank_dir ),
|
||||||
.tank_fire( enermy4_fire ),
|
.tank_fire( enermy4_fire ),
|
||||||
.player_enermy( 1'b1 ),
|
.player_enermy( 1'b1 ),
|
||||||
|
.item_faster( item_faster ),
|
||||||
.vgaV( vgaV ),
|
.vgaV( vgaV ),
|
||||||
.vgaH( vgaH ),
|
.vgaH( vgaH ),
|
||||||
.start( 1 ),
|
.start( 1 ),
|
||||||
|
|
@ -681,7 +681,7 @@ vga_data_heart_gametips u_vga_data_heart_gametips(
|
||||||
.score_classic( score_classic ),
|
.score_classic( score_classic ),
|
||||||
.vgaData( heart_gametips_data )
|
.vgaData( heart_gametips_data )
|
||||||
);
|
);
|
||||||
assign item_faster = 0;
|
|
||||||
|
|
||||||
item_logic u_item_logic(
|
item_logic u_item_logic(
|
||||||
.clk( clk ),
|
.clk( clk ),
|
||||||
|
|
@ -704,6 +704,7 @@ item_logic u_item_logic(
|
||||||
.item_addHP( item_addHP ),
|
.item_addHP( item_addHP ),
|
||||||
.item_addtime( item_addtime ),
|
.item_addtime( item_addtime ),
|
||||||
.item_frozen( item_frozen ),
|
.item_frozen( item_frozen ),
|
||||||
|
.item_faster( item_faster ),
|
||||||
.which_player( which_player ),
|
.which_player( which_player ),
|
||||||
.VGA_data_reward( item_data )
|
.VGA_data_reward( item_data )
|
||||||
);
|
);
|
||||||
|
|
|
||||||
|
|
@ -16,7 +16,7 @@ module bullet_control(
|
||||||
input [ 10: 0 ] vgaH,
|
input [ 10: 0 ] vgaH,
|
||||||
input [ 10: 0 ] vgaV,
|
input [ 10: 0 ] vgaV,
|
||||||
input ready,
|
input ready,
|
||||||
|
input item_faster,
|
||||||
output [ 11: 0 ] bulletData,
|
output [ 11: 0 ] bulletData,
|
||||||
output reg [ 10: 0 ] bullet_H_feedback,
|
output reg [ 10: 0 ] bullet_H_feedback,
|
||||||
output reg [ 10: 0 ] bullet_V_feedback,
|
output reg [ 10: 0 ] bullet_V_feedback,
|
||||||
|
|
@ -123,7 +123,7 @@ end
|
||||||
|
|
||||||
reg bullet_move_en;
|
reg bullet_move_en;
|
||||||
wire [ 31: 0 ] bullet_speed;
|
wire [ 31: 0 ] bullet_speed;
|
||||||
assign bullet_speed = player_enermy ? 1_000_000 : 1_000_000;
|
assign bullet_speed = item_faster ? 600_000 : 1_000_000;
|
||||||
always @( posedge clk ) begin: counter_logic
|
always @( posedge clk ) begin: counter_logic
|
||||||
if ( !reset_n ) begin
|
if ( !reset_n ) begin
|
||||||
counter <= 0;
|
counter <= 0;
|
||||||
|
|
|
||||||
|
|
@ -22,7 +22,6 @@
|
||||||
|
|
||||||
module clock(
|
module clock(
|
||||||
input wire clk_100MHz,
|
input wire clk_100MHz,
|
||||||
input wire item_faster,
|
|
||||||
output reg clk_2Hz,
|
output reg clk_2Hz,
|
||||||
output reg clk_4Hz,
|
output reg clk_4Hz,
|
||||||
output reg clk_8Hz,
|
output reg clk_8Hz,
|
||||||
|
|
@ -90,12 +89,9 @@ always @( posedge clk_100MHz ) begin
|
||||||
end
|
end
|
||||||
|
|
||||||
always @( posedge clk_100MHz ) begin
|
always @( posedge clk_100MHz ) begin
|
||||||
if ( item_faster == 1'b1 ) begin
|
|
||||||
ending_4Hz <= 6250000;
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
ending_4Hz <= 12500000;
|
ending_4Hz <= 12500000;
|
||||||
end
|
|
||||||
end
|
end
|
||||||
|
|
||||||
always @( posedge clk_100MHz ) begin
|
always @( posedge clk_100MHz ) begin
|
||||||
|
|
|
||||||
|
|
@ -2,6 +2,7 @@
|
||||||
|
|
||||||
module control_signals(
|
module control_signals(
|
||||||
clk, reset_n,
|
clk, reset_n,
|
||||||
|
item_invincible,
|
||||||
player1_bullet_H, player1_bullet_V, player2_bullet_H, player2_bullet_V,
|
player1_bullet_H, player1_bullet_V, player2_bullet_H, player2_bullet_V,
|
||||||
enermy1_bullet_H, enermy1_bullet_V,
|
enermy1_bullet_H, enermy1_bullet_V,
|
||||||
enermy2_bullet_H, enermy2_bullet_V,
|
enermy2_bullet_H, enermy2_bullet_V,
|
||||||
|
|
@ -30,6 +31,7 @@ module control_signals(
|
||||||
// scorea1, scorea2, scoreb1, scoreb2, scorec1, scorec2, scored1, scored2
|
// scorea1, scorea2, scoreb1, scoreb2, scorec1, scorec2, scored1, scored2
|
||||||
);
|
);
|
||||||
input clk, reset_n;
|
input clk, reset_n;
|
||||||
|
input item_invincible;
|
||||||
input [ 10: 0 ] player1_bullet_H, player1_bullet_V, player2_bullet_H, player2_bullet_V;
|
input [ 10: 0 ] player1_bullet_H, player1_bullet_V, player2_bullet_H, player2_bullet_V;
|
||||||
input [ 10: 0 ] enermy1_bullet_H, enermy1_bullet_V,
|
input [ 10: 0 ] enermy1_bullet_H, enermy1_bullet_V,
|
||||||
enermy2_bullet_H, enermy2_bullet_V,
|
enermy2_bullet_H, enermy2_bullet_V,
|
||||||
|
|
@ -789,7 +791,7 @@ end
|
||||||
// end
|
// end
|
||||||
always @( posedge clk ) begin: player2_tank_enable_signal
|
always @( posedge clk ) begin: player2_tank_enable_signal
|
||||||
|
|
||||||
if ( player2_revive ) begin
|
if ( player2_revive || item_invincible ) begin
|
||||||
player2_tank_en_feedback <= 1;
|
player2_tank_en_feedback <= 1;
|
||||||
end
|
end
|
||||||
else if ( !reset_n ) begin
|
else if ( !reset_n ) begin
|
||||||
|
|
@ -808,7 +810,7 @@ end
|
||||||
|
|
||||||
|
|
||||||
always @( posedge clk ) begin: player1_tank_enable_signal
|
always @( posedge clk ) begin: player1_tank_enable_signal
|
||||||
if ( player1_revive ) begin
|
if ( player1_revive || item_invincible ) begin
|
||||||
player1_tank_en_feedback <= 1;
|
player1_tank_en_feedback <= 1;
|
||||||
end
|
end
|
||||||
else if ( !reset_n ) begin
|
else if ( !reset_n ) begin
|
||||||
|
|
|
||||||
|
|
@ -73,7 +73,7 @@ wire [ 10: 0 ] chase_tank_V = rand ? player1_V : player2_V;
|
||||||
|
|
||||||
reg Continue;
|
reg Continue;
|
||||||
reg [ 2: 0 ] Continue_num;
|
reg [ 2: 0 ] Continue_num;
|
||||||
|
reg enermy_fire_tmp;
|
||||||
assign enermy_moving = enermy_tank_en;
|
assign enermy_moving = enermy_tank_en;
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
|
|
@ -82,6 +82,7 @@ initial begin
|
||||||
rand <= flag[ 0 ];
|
rand <= flag[ 0 ];
|
||||||
Continue <= 0;
|
Continue <= 0;
|
||||||
Continue_num <= 0;
|
Continue_num <= 0;
|
||||||
|
enermy_fire_tmp <= 0;
|
||||||
end
|
end
|
||||||
|
|
||||||
Random u_Random(
|
Random u_Random(
|
||||||
|
|
@ -198,7 +199,7 @@ always @( posedge clk_2Hz ) begin
|
||||||
|
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
enermy_fire <= 1'b0;
|
enermy_fire_tmp <= 1'b0;
|
||||||
if ( rand ) begin
|
if ( rand ) begin
|
||||||
if ( enermy_V + TANK_HEIGHT / 2 <= chase_tank_V ) begin
|
if ( enermy_V + TANK_HEIGHT / 2 <= chase_tank_V ) begin
|
||||||
enermy_dir_feedback_tmp <= 2'b01;
|
enermy_dir_feedback_tmp <= 2'b01;
|
||||||
|
|
@ -207,7 +208,7 @@ always @( posedge clk_2Hz ) begin
|
||||||
enermy_dir_feedback_tmp <= 2'b00;
|
enermy_dir_feedback_tmp <= 2'b00;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
enermy_fire <= 1'b1;
|
enermy_fire_tmp <= 1'b1;
|
||||||
if ( enermy_H < chase_tank_H ) begin
|
if ( enermy_H < chase_tank_H ) begin
|
||||||
enermy_dir_feedback_tmp <= 2'b11;
|
enermy_dir_feedback_tmp <= 2'b11;
|
||||||
end
|
end
|
||||||
|
|
@ -224,7 +225,7 @@ always @( posedge clk_2Hz ) begin
|
||||||
enermy_dir_feedback_tmp <= 2'b10;
|
enermy_dir_feedback_tmp <= 2'b10;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
enermy_fire <= 1'b1;
|
enermy_fire_tmp <= 1'b1;
|
||||||
if ( enermy_V < chase_tank_V ) begin
|
if ( enermy_V < chase_tank_V ) begin
|
||||||
enermy_dir_feedback_tmp <= 2'b01;
|
enermy_dir_feedback_tmp <= 2'b01;
|
||||||
end
|
end
|
||||||
|
|
@ -247,10 +248,11 @@ always @( posedge clk_2Hz ) begin
|
||||||
rand <= rand_num[ 0 ] ;
|
rand <= rand_num[ 0 ] ;
|
||||||
end
|
end
|
||||||
Continue_num <= Continue_num + 1'b1;
|
Continue_num <= Continue_num + 1'b1;
|
||||||
if ( Continue_num == 4 ) begin
|
if ( Continue_num == 2 ) begin
|
||||||
Continue_num <= 0;
|
Continue_num <= 0;
|
||||||
Continue <= 0;
|
Continue <= 0;
|
||||||
end
|
end
|
||||||
|
enermy_fire <= enermy_fire_tmp;
|
||||||
|
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -95,10 +95,10 @@ infinity_info_180_24 u_infinity_info_180_24(
|
||||||
always @( posedge clk ) begin
|
always @( posedge clk ) begin
|
||||||
if ( enable_game_classic ) begin
|
if ( enable_game_classic ) begin
|
||||||
vga_en3 <= 1;
|
vga_en3 <= 1;
|
||||||
if ( vgaH >= 320 && vgaH < 480 && vgaV >= 1 && vgaV < 21 && ( vgaH - 320 ) < score_classic[ 3: 0 ] * 20 ) begin
|
if ( vgaH >= 320 && vgaH < 640 && vgaV >= 1 && vgaV < 21 && ( vgaH - 320 ) < score_classic[ 3: 0 ] * 20 ) begin
|
||||||
addr_redflag <= ( vgaH - 320 ) % 20 + ( vgaV - 1 ) * 20;
|
addr_redflag <= ( vgaH - 320 ) % 20 + ( vgaV - 1 ) * 20;
|
||||||
end
|
end
|
||||||
else if ( vgaH >= 320 && vgaH < 480 && vgaV >= 24 && vgaV < 44 && ( vgaH - 320 ) < score_classic[ 7: 4 ] * 20 ) begin
|
else if ( vgaH >= 320 && vgaH < 640 && vgaV >= 24 && vgaV < 44 && ( vgaH - 320 ) < score_classic[ 7: 4 ] * 20 ) begin
|
||||||
addr_redflag <= ( vgaH - 320 ) % 20 + ( vgaV - 24 ) * 20;
|
addr_redflag <= ( vgaH - 320 ) % 20 + ( vgaV - 24 ) * 20;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
|
|
|
||||||
|
|
@ -135,9 +135,9 @@ always @( posedge clk ) begin
|
||||||
score2 <= scorea2 + scoreb2 + scorec2 + scored2;
|
score2 <= scorea2 + scoreb2 + scorec2 + scored2;
|
||||||
score_classic[ 7: 4 ] <= score2[ 3: 0 ];
|
score_classic[ 7: 4 ] <= score2[ 3: 0 ];
|
||||||
score_classic[ 3: 0 ] <= score1[ 3: 0 ];
|
score_classic[ 3: 0 ] <= score1[ 3: 0 ];
|
||||||
if ( HP1_value == 0 || HP2_value == 0 || score1 >= 8 || score2 >= 8 ) begin
|
if ( HP1_value == 0 || HP2_value == 0 || score1 >= 14 || score2 >= 14 ) begin
|
||||||
gameover_classic <= 1;
|
gameover_classic <= 1;
|
||||||
if ( HP2_value == 0 || score1 >= 8 ) begin
|
if ( HP2_value == 0 || score1 >= 14 ) begin
|
||||||
winner <= 2'b10;
|
winner <= 2'b10;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
|
|
|
||||||
|
|
@ -26,7 +26,7 @@ module item_display(
|
||||||
input enable_reward,
|
input enable_reward,
|
||||||
input [ 10: 0 ] random_xpos,
|
input [ 10: 0 ] random_xpos,
|
||||||
input [ 10: 0 ] random_ypos,
|
input [ 10: 0 ] random_ypos,
|
||||||
input [ 1: 0 ] item_type,
|
input [ 2: 0 ] item_type,
|
||||||
input [ 10: 0 ] VGA_h,
|
input [ 10: 0 ] VGA_h,
|
||||||
input [ 10: 0 ] VGA_V,
|
input [ 10: 0 ] VGA_V,
|
||||||
input enable_game_classic,
|
input enable_game_classic,
|
||||||
|
|
@ -39,12 +39,12 @@ module item_display(
|
||||||
wire [ 5: 0 ] ITEM_WIDTH ;
|
wire [ 5: 0 ] ITEM_WIDTH ;
|
||||||
wire [ 5: 0 ] ITEM_HEIGHT;
|
wire [ 5: 0 ] ITEM_HEIGHT;
|
||||||
|
|
||||||
assign ITEM_WIDTH = item_type == 2'b11 ? 32 : 20;
|
assign ITEM_WIDTH = item_type == 3 ? 32 : 20;
|
||||||
assign ITEM_HEIGHT = item_type == 2'b11 ? 32 : 20;
|
assign ITEM_HEIGHT = item_type == 3 ? 32 : 20;
|
||||||
reg [ 8: 0 ] addra_add_heart, addra_add_timing, addra_frozen;
|
reg [ 8: 0 ] addra_add_heart, addra_add_timing, addra_frozen, addra_faster;
|
||||||
reg [ 9: 0 ] addra_invincible;
|
reg [ 9: 0 ] addra_invincible;
|
||||||
|
|
||||||
wire[ 11: 0 ] add_heart_pic, add_timing_pic, add_frozen_pic, invincible_pic;
|
wire[ 11: 0 ] add_heart_pic, add_timing_pic, add_frozen_pic, invincible_pic, faster_pic;
|
||||||
// reg [ 11: 0 ] add_heart_reg, add_timing_reg, add_frozen_reg, invincible_reg;
|
// reg [ 11: 0 ] add_heart_reg, add_timing_reg, add_frozen_reg, invincible_reg;
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -55,9 +55,10 @@ always @( posedge clk ) begin
|
||||||
addra_add_heart <= ( VGA_h - random_xpos ) + ( VGA_V - random_ypos ) * 20;
|
addra_add_heart <= ( VGA_h - random_xpos ) + ( VGA_V - random_ypos ) * 20;
|
||||||
addra_add_timing <= ( VGA_h - random_xpos ) + ( VGA_V - random_ypos ) * 20;
|
addra_add_timing <= ( VGA_h - random_xpos ) + ( VGA_V - random_ypos ) * 20;
|
||||||
addra_frozen <= ( VGA_h - random_xpos ) + ( VGA_V - random_ypos ) * 20;
|
addra_frozen <= ( VGA_h - random_xpos ) + ( VGA_V - random_ypos ) * 20;
|
||||||
|
addra_faster <= ( VGA_h - random_xpos ) + ( VGA_V - random_ypos ) * 20;
|
||||||
addra_invincible <= ( VGA_h - random_xpos ) + ( VGA_V - random_ypos ) * 32;
|
addra_invincible <= ( VGA_h - random_xpos ) + ( VGA_V - random_ypos ) * 32;
|
||||||
case ( item_type )
|
case ( item_type )
|
||||||
2'b01: begin
|
1: begin
|
||||||
if ( enable_game_classic == 1 ) begin
|
if ( enable_game_classic == 1 ) begin
|
||||||
VGA_data <= add_heart_pic;
|
VGA_data <= add_heart_pic;
|
||||||
end
|
end
|
||||||
|
|
@ -65,12 +66,15 @@ always @( posedge clk ) begin
|
||||||
VGA_data <= add_timing_pic;
|
VGA_data <= add_timing_pic;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
2'b10: begin
|
2: begin
|
||||||
VGA_data <= add_frozen_pic;
|
VGA_data <= add_frozen_pic;
|
||||||
end
|
end
|
||||||
2'b11: begin
|
3: begin
|
||||||
VGA_data <= invincible_pic;
|
VGA_data <= invincible_pic;
|
||||||
end
|
end
|
||||||
|
4: begin
|
||||||
|
VGA_data <= faster_pic;
|
||||||
|
end
|
||||||
default : begin
|
default : begin
|
||||||
VGA_data <= 0;
|
VGA_data <= 0;
|
||||||
end
|
end
|
||||||
|
|
@ -109,4 +113,11 @@ invincible_star_32_32 u_invincible_star(
|
||||||
.addra( addra_invincible ),
|
.addra( addra_invincible ),
|
||||||
.douta( invincible_pic )
|
.douta( invincible_pic )
|
||||||
);
|
);
|
||||||
|
|
||||||
|
lightning_20_20 u_lightning_20_20(
|
||||||
|
.clka( clk ),
|
||||||
|
.ena( 1'b1 ),
|
||||||
|
.addra( addra_faster ),
|
||||||
|
.douta( faster_pic )
|
||||||
|
);
|
||||||
endmodule
|
endmodule
|
||||||
|
|
|
||||||
|
|
@ -42,11 +42,12 @@ module item_logic(
|
||||||
output reg item_addtime,
|
output reg item_addtime,
|
||||||
output reg item_frozen,
|
output reg item_frozen,
|
||||||
output reg item_addHP,
|
output reg item_addHP,
|
||||||
|
output reg item_faster,
|
||||||
output reg which_player,
|
output reg which_player,
|
||||||
output [ 11: 0 ] VGA_data_reward
|
output [ 11: 0 ] VGA_data_reward
|
||||||
);
|
);
|
||||||
|
|
||||||
wire [ 1: 0 ] item_type;
|
wire [ 2: 0 ] item_type;
|
||||||
wire [ 10: 0 ] random_xpos, random_ypos;
|
wire [ 10: 0 ] random_xpos, random_ypos;
|
||||||
reg [ 31: 0 ] cnt;
|
reg [ 31: 0 ] cnt;
|
||||||
|
|
||||||
|
|
@ -63,6 +64,7 @@ initial begin
|
||||||
item_frozen <= 0;
|
item_frozen <= 0;
|
||||||
item_addHP <= 0;
|
item_addHP <= 0;
|
||||||
which_player <= 0;
|
which_player <= 0;
|
||||||
|
item_faster <= 0;
|
||||||
end
|
end
|
||||||
|
|
||||||
wire player1_tank_get, player1_tank_tmp;
|
wire player1_tank_get, player1_tank_tmp;
|
||||||
|
|
@ -112,11 +114,17 @@ always @( posedge clk ) begin
|
||||||
item_invincible <= 1'b1;
|
item_invincible <= 1'b1;
|
||||||
which_player <= player2_tank_get;
|
which_player <= player2_tank_get;
|
||||||
end
|
end
|
||||||
|
4: begin
|
||||||
|
item_faster <= 1'b1;
|
||||||
|
which_player <= player2_tank_get;
|
||||||
|
|
||||||
|
end
|
||||||
default : begin
|
default : begin
|
||||||
item_addHP <= 1'b0;
|
item_addHP <= 1'b0;
|
||||||
item_addtime <= 1'b0;
|
item_addtime <= 1'b0;
|
||||||
item_frozen <= 1'b0;
|
item_frozen <= 1'b0;
|
||||||
item_invincible <= 1'b0;
|
item_invincible <= 1'b0;
|
||||||
|
item_faster <= 1'b0;
|
||||||
end
|
end
|
||||||
|
|
||||||
endcase
|
endcase
|
||||||
|
|
@ -125,6 +133,13 @@ always @( posedge clk ) begin
|
||||||
else begin
|
else begin
|
||||||
set_finish <= 1'b0;
|
set_finish <= 1'b0;
|
||||||
end
|
end
|
||||||
|
if ( item_faster ) begin
|
||||||
|
cnt <= cnt + 1;
|
||||||
|
if ( cnt >= 900000000 ) begin
|
||||||
|
item_faster <= 1'b0;
|
||||||
|
cnt <= 0;
|
||||||
|
end
|
||||||
|
end
|
||||||
if ( item_invincible ) begin
|
if ( item_invincible ) begin
|
||||||
cnt <= cnt + 1;
|
cnt <= cnt + 1;
|
||||||
if ( cnt >= 800000000 ) begin
|
if ( cnt >= 800000000 ) begin
|
||||||
|
|
@ -159,6 +174,7 @@ always @( posedge clk ) begin
|
||||||
item_invincible <= 0;
|
item_invincible <= 0;
|
||||||
item_addtime <= 0;
|
item_addtime <= 0;
|
||||||
item_frozen <= 0;
|
item_frozen <= 0;
|
||||||
|
item_faster <= 0;
|
||||||
item_addHP <= 0;
|
item_addHP <= 0;
|
||||||
which_player <= 0;
|
which_player <= 0;
|
||||||
end
|
end
|
||||||
|
|
|
||||||
|
|
@ -27,7 +27,7 @@ module item_random_generator(
|
||||||
input enable,
|
input enable,
|
||||||
output reg dout,
|
output reg dout,
|
||||||
output reg set_require,
|
output reg set_require,
|
||||||
output reg [ 1: 0 ] item_type,
|
output reg [ 2: 0 ] item_type,
|
||||||
output reg [ 10: 0 ] random_xpos,
|
output reg [ 10: 0 ] random_xpos,
|
||||||
output reg [ 10: 0 ] random_ypos
|
output reg [ 10: 0 ] random_ypos
|
||||||
);
|
);
|
||||||
|
|
@ -81,7 +81,7 @@ always @( posedge clk ) begin
|
||||||
lock <= 1'b1;
|
lock <= 1'b1;
|
||||||
random_xpos <= random_num[ 14: 1 ] % ( WIDTH - TANK_WIDTH );
|
random_xpos <= random_num[ 14: 1 ] % ( WIDTH - TANK_WIDTH );
|
||||||
random_ypos <= random_num[ 13: 0 ] % ( HEIGHT - TANK_HEIGHT );
|
random_ypos <= random_num[ 13: 0 ] % ( HEIGHT - TANK_HEIGHT );
|
||||||
item_type <= ( random_num[ 14: 0 ] % 3 ) + 1;
|
item_type <= ( random_num[ 14: 0 ] % 4 ) + 1;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
|
|
|
||||||
|
|
@ -3,7 +3,7 @@
|
||||||
module tank_move(
|
module tank_move(
|
||||||
clk, reset_n, start,
|
clk, reset_n, start,
|
||||||
init_H, init_V,
|
init_H, init_V,
|
||||||
tank_dir, tank_en, tank_move_en, player_enermy, moving, item_frozen,
|
tank_dir, tank_en, tank_move_en, player_enermy, moving, item_frozen, item_faster,
|
||||||
tank_H, tank_V, tank_dir_feedback
|
tank_H, tank_V, tank_dir_feedback
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|
@ -17,6 +17,7 @@ input [ 10: 0 ] init_V;
|
||||||
input [ 1: 0 ] tank_dir;
|
input [ 1: 0 ] tank_dir;
|
||||||
input tank_en;
|
input tank_en;
|
||||||
input tank_move_en;
|
input tank_move_en;
|
||||||
|
input item_faster;
|
||||||
input player_enermy;
|
input player_enermy;
|
||||||
output reg [ 10: 0 ] tank_H;
|
output reg [ 10: 0 ] tank_H;
|
||||||
output reg [ 10: 0 ] tank_V;
|
output reg [ 10: 0 ] tank_V;
|
||||||
|
|
@ -170,7 +171,7 @@ always @( posedge clk ) begin: tank_move_logic
|
||||||
end
|
end
|
||||||
|
|
||||||
reg [ 31: 0 ] counter;
|
reg [ 31: 0 ] counter;
|
||||||
wire [ 31: 0 ] counter_num = player_enermy ? 2_000_000 : 2_000_000;
|
wire [ 31: 0 ] counter_num = item_faster ? 1_500_000 : 2_100_000;
|
||||||
always @( posedge clk ) begin
|
always @( posedge clk ) begin
|
||||||
if ( !reset_n ) begin
|
if ( !reset_n ) begin
|
||||||
counter <= 0;
|
counter <= 0;
|
||||||
|
|
|
||||||
|
|
@ -91,9 +91,9 @@ startpic_450_200 u_start_pic(
|
||||||
);
|
);
|
||||||
|
|
||||||
always@( posedge clk ) begin
|
always@( posedge clk ) begin
|
||||||
if ( sw_mode_sel ) begin
|
if ( !sw_mode_sel ) begin
|
||||||
if ( vgaH >= 229 && vgaH <= 233 && vgaV >= 233 && vgaV <= 237 ) begin
|
if ( vgaH >= 229 && vgaH <= 233 && vgaV >= 233 && vgaV <= 237 ) begin
|
||||||
VGA_data_cursor <= 12'hFF0;
|
VGA_data_cursor <= 12'h0F0;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
VGA_data_cursor <= 12'h0;
|
VGA_data_cursor <= 12'h0;
|
||||||
|
|
@ -101,7 +101,7 @@ always@( posedge clk ) begin
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
if ( vgaH >= 229 && vgaH <= 233 && vgaV >= 252 && vgaV <= 256 ) begin
|
if ( vgaH >= 229 && vgaH <= 233 && vgaV >= 252 && vgaV <= 256 ) begin
|
||||||
VGA_data_cursor <= 12'hFF0;
|
VGA_data_cursor <= 12'h0F0;
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
VGA_data_cursor <= 12'h0;
|
VGA_data_cursor <= 12'h0;
|
||||||
|
|
|
||||||
66
TankGame.xpr
66
TankGame.xpr
|
|
@ -36,13 +36,13 @@
|
||||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||||
<Option Name="WTXSimExportSim" Val="34"/>
|
<Option Name="WTXSimExportSim" Val="35"/>
|
||||||
<Option Name="WTModelSimExportSim" Val="34"/>
|
<Option Name="WTModelSimExportSim" Val="35"/>
|
||||||
<Option Name="WTQuestaExportSim" Val="34"/>
|
<Option Name="WTQuestaExportSim" Val="35"/>
|
||||||
<Option Name="WTIesExportSim" Val="34"/>
|
<Option Name="WTIesExportSim" Val="35"/>
|
||||||
<Option Name="WTVcsExportSim" Val="34"/>
|
<Option Name="WTVcsExportSim" Val="35"/>
|
||||||
<Option Name="WTRivieraExportSim" Val="34"/>
|
<Option Name="WTRivieraExportSim" Val="35"/>
|
||||||
<Option Name="WTActivehdlExportSim" Val="34"/>
|
<Option Name="WTActivehdlExportSim" Val="35"/>
|
||||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||||
<Option Name="XSimRadix" Val="hex"/>
|
<Option Name="XSimRadix" Val="hex"/>
|
||||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||||
|
|
@ -506,6 +506,12 @@
|
||||||
<Attr Name="UsedIn" Val="simulation"/>
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
</FileInfo>
|
</FileInfo>
|
||||||
</File>
|
</File>
|
||||||
|
<File Path="$PSRCDIR/pic/lightning_20_20.coe">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
<Config>
|
<Config>
|
||||||
<Option Name="DesignMode" Val="RTL"/>
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
<Option Name="TopModule" Val="Top"/>
|
<Option Name="TopModule" Val="Top"/>
|
||||||
|
|
@ -555,7 +561,7 @@
|
||||||
<File Path="$PSRCDIR/utils_1/imports/impl_1/Top_routed.dcp">
|
<File Path="$PSRCDIR/utils_1/imports/impl_1/Top_routed.dcp">
|
||||||
<FileInfo>
|
<FileInfo>
|
||||||
<Attr Name="ImportPath" Val="$PRUNDIR/impl_1/Top_routed.dcp"/>
|
<Attr Name="ImportPath" Val="$PRUNDIR/impl_1/Top_routed.dcp"/>
|
||||||
<Attr Name="ImportTime" Val="1609923161"/>
|
<Attr Name="ImportTime" Val="1609939059"/>
|
||||||
<Attr Name="UsedIn" Val="synthesis"/>
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
<Attr Name="UsedIn" Val="implementation"/>
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
<Attr Name="UsedInSteps" Val="impl_1"/>
|
<Attr Name="UsedInSteps" Val="impl_1"/>
|
||||||
|
|
@ -940,6 +946,19 @@
|
||||||
<Option Name="UseBlackboxStub" Val="1"/>
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||||||
</Config>
|
</Config>
|
||||||
</FileSet>
|
</FileSet>
|
||||||
|
<FileSet Name="lightning_20_20" Type="BlockSrcs" RelSrcDir="$PSRCDIR/lightning_20_20">
|
||||||
|
<File Path="$PSRCDIR/sources_1/ip/lightning_20_20/lightning_20_20.xci">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopModule" Val="lightning_20_20"/>
|
||||||
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
</FileSets>
|
</FileSets>
|
||||||
<Simulators>
|
<Simulators>
|
||||||
<Simulator Name="XSim">
|
<Simulator Name="XSim">
|
||||||
|
|
@ -1250,6 +1269,18 @@
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
<RQSFiles/>
|
<RQSFiles/>
|
||||||
</Run>
|
</Run>
|
||||||
|
<Run Id="lightning_20_20_synth_1" Type="Ft3:Synth" SrcSet="lightning_20_20" Part="xc7a100tcsg324-1" ConstrsSet="lightning_20_20" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/lightning_20_20_synth_1" IncludeInArchive="true">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/impl_1/Top_routed.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/impl_1/Top_routed.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||||
<Strategy Version="1" Minor="2">
|
<Strategy Version="1" Minor="2">
|
||||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||||
|
|
@ -1744,6 +1775,25 @@
|
||||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
<RQSFiles/>
|
<RQSFiles/>
|
||||||
</Run>
|
</Run>
|
||||||
|
<Run Id="lightning_20_20_impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="lightning_20_20" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="lightning_20_20_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design" EnableStepBool="1"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
</Runs>
|
</Runs>
|
||||||
<Board/>
|
<Board/>
|
||||||
<DashboardSummary Version="1" Minor="0">
|
<DashboardSummary Version="1" Minor="0">
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue