222 lines
7.7 KiB
Verilog
222 lines
7.7 KiB
Verilog
`timescale 1ns / 1ps
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module bullet_control(
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input clk,
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input reset_n,
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input start,
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input [10:0] tank_H,
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input [10:0] tank_V,
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input tank_en,
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input [1:0] tank_dir,
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input tank_fire,
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input [10:0] vgaH,
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input [10:0] vgaV,
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input ready,
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output [11:0] bulletData,
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output reg [10:0] bullet_H_feedback,
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output reg [10:0] bullet_V_feedback,
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output reg [2:0] bullet_direction
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);
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parameter BULLET_LONGER = 10;
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parameter BULLET_SHORTER = 5;
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parameter BULLET_LONGER_CENTER = 5;
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parameter BULLET_SHORTER_CENTER = 2;
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parameter HEIGHT = 480;
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parameter WIDTH = 640;
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parameter TANK_V_CENTER = 16;
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parameter TANK_H_CENTER = 16;
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parameter TANK_HEIGHT = 32, TANK_WIDTH = 32;
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localparam
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UP = 3'd0,
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DOWN = 3'd1,
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LEFT = 3'd2,
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RIGHT = 3'd3,
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WAIT = 3'd4,
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READY = 3'd5;
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reg counter_en;
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reg [31:0] counter;
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reg [2:0] current_state, next_state;
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always @(posedge clk) begin:state_flip_flop
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if(!reset_n) current_state <= WAIT;
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// else if(!tank_en) current_state <= WAIT;
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else current_state <= next_state;
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end
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always @(*) begin: state_table
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case(current_state)
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WAIT: next_state = start ? READY : WAIT;
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READY: begin
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if(!tank_fire)
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next_state = READY;
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else begin
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case(tank_dir)
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2'b00: next_state = UP;
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2'b01: next_state = DOWN;
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2'b10: next_state = LEFT;
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2'b11: next_state = RIGHT;
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endcase
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end
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end
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UP: next_state = ready ? READY : UP;
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DOWN: next_state = ready ? READY : DOWN;
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LEFT: next_state = ready ? READY : LEFT;
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RIGHT: next_state = ready ? READY : RIGHT;
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default: next_state = READY;
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endcase
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end
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always @(*) begin: bullet_logic
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counter_en = 0;
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bullet_direction = 3'b111;
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case(current_state)
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READY: begin
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counter_en = 0;
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bullet_direction = 3'b111;
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end
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UP: begin
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counter_en = 1;
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bullet_direction = 3'b000;
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end
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DOWN: begin
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counter_en = 1;
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bullet_direction = 3'b001;
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end
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LEFT: begin
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counter_en = 1;
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bullet_direction = 3'b010;
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end
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RIGHT: begin
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counter_en = 1;
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bullet_direction = 3'b011;
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end
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endcase
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end
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reg bullet_move_en;
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always @(posedge clk) begin: counter_logic
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if(!reset_n) begin
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counter <= 0;
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bullet_move_en <= 0;
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end
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else if(counter == 1_000_000) begin
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counter <= 0;
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bullet_move_en <= 1;
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end
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else if(counter_en == 0) begin
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counter <= 0;
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bullet_move_en <= 0;
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end
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else begin
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counter <= counter + 1;
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bullet_move_en <= 0;
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end
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end
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always @(posedge clk) begin: bullet_move
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if(bullet_direction[2]) begin //if no direction
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case(tank_dir)
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2'b00: begin
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bullet_H_feedback <= tank_H + TANK_H_CENTER - BULLET_SHORTER_CENTER;
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bullet_V_feedback <= ( (tank_V >= BULLET_LONGER) ? (tank_V - BULLET_LONGER) : 0);
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end
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2'b01: begin
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bullet_H_feedback <= tank_H + TANK_H_CENTER - BULLET_SHORTER_CENTER;
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bullet_V_feedback <= ( (tank_V + TANK_HEIGHT + BULLET_LONGER <= HEIGHT) ? (tank_V + TANK_HEIGHT + BULLET_LONGER) : HEIGHT);
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end
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2'b10: begin
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bullet_H_feedback <= ( (tank_H >= BULLET_LONGER) ? (tank_H - BULLET_LONGER) : 0);
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bullet_V_feedback <= tank_V + TANK_V_CENTER - BULLET_SHORTER_CENTER;
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end
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2'b11: begin
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bullet_H_feedback <= ( (tank_H + BULLET_LONGER + TANK_WIDTH <= WIDTH) ? (tank_H + BULLET_LONGER + TANK_WIDTH) : WIDTH ) ;
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bullet_V_feedback <= tank_V + TANK_V_CENTER - BULLET_SHORTER_CENTER;
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end
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endcase
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end
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else if(bullet_move_en) begin
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case(bullet_direction[1:0])
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2'b00:begin
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bullet_V_feedback <= bullet_V_feedback - 1;
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bullet_H_feedback <= bullet_H_feedback;
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end
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2'b01: begin
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bullet_V_feedback <= bullet_V_feedback + 1;
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bullet_H_feedback <= bullet_H_feedback;
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end
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2'b10: begin
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bullet_H_feedback <= bullet_H_feedback - 1;
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bullet_V_feedback <= bullet_V_feedback;
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end
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2'b11: begin
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bullet_H_feedback <= bullet_H_feedback + 1;
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bullet_V_feedback <= bullet_V_feedback;
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end
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endcase
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end
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else begin
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bullet_H_feedback <= bullet_H_feedback;
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bullet_V_feedback <= bullet_V_feedback;
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end
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end
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wire [11:0] UP_data, DOWN_data, LEFT_data, RIGHT_data;
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wire [7:0] bulletAddr;
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reg bullet_bound;
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always @(*) begin
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case(bullet_direction[1:0])
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2'b00: begin
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bullet_bound <= (bullet_H_feedback <= vgaH && bullet_H_feedback > vgaH - BULLET_SHORTER && bullet_V_feedback <= vgaV && bullet_V_feedback > vgaV - BULLET_LONGER) ? 1 : 0;
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end
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2'b01: begin
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bullet_bound <= (bullet_H_feedback <= vgaH && bullet_H_feedback > vgaH - BULLET_SHORTER && bullet_V_feedback <= vgaV && bullet_V_feedback > vgaV - BULLET_LONGER) ? 1 : 0;
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end
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2'b10: begin
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bullet_bound <= (bullet_H_feedback <= vgaH && bullet_H_feedback > vgaH - BULLET_LONGER && bullet_V_feedback > vgaV - BULLET_SHORTER) ? 1 : 0;
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end
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2'b11: begin
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bullet_bound <= (bullet_H_feedback <= vgaH && bullet_H_feedback > vgaH - BULLET_LONGER && bullet_V_feedback <= vgaV && bullet_V_feedback > vgaV - BULLET_SHORTER) ? 1 : 0;
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end
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endcase
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end
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reg [5:0] bullet_addr;
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always @(*) begin
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case(bullet_direction[1:0])
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2'b00: begin
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bullet_addr <= bullet_bound ? ( (vgaV - bullet_V_feedback) * BULLET_SHORTER + (vgaH - bullet_H_feedback) ) : 15;
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end
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2'b01: begin
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bullet_addr <= bullet_bound ? ( (vgaV - bullet_V_feedback) * BULLET_SHORTER + (vgaH - bullet_H_feedback) ) : 15;
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end
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2'b10: begin
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bullet_addr <= bullet_bound ? ( (vgaV - bullet_V_feedback) * BULLET_LONGER + (vgaH - bullet_H_feedback) ) : 15;
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end
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2'b11: begin
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bullet_addr <= bullet_bound ? ( (vgaV - bullet_V_feedback) * BULLET_LONGER + (vgaH - bullet_H_feedback) ): 15;
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end
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endcase
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end
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wire [11:0] outData;
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bullet_left_img left(.addra(bullet_addr), .clka(clk), .douta(LEFT_data), .ena(1'b1));
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bullet_right_img right(.addra(bullet_addr), .clka(clk), .douta(RIGHT_data), .ena(1'b1));
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bullet_up_img up(.addra(bullet_addr), .clka(clk), .douta(UP_data), .ena(1'b1));
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bullet_down_img down(.addra(bullet_addr), .clka(clk), .douta(DOWN_data), .ena(1'b1));
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tank_data_selector bullet_selector(.clk(clk), .UP(UP_data), .DOWN(DOWN_data), .LEFT(LEFT_data),
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.RIGHT(RIGHT_data), .Dir(bullet_dir_feedback), .tankData(outData));
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assign bulletData = (~ready & bullet_bound) ? outData : 0;
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endmodule
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